arch/arm64/include/asm/cputype.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_CPUTYPE_H
  17 #define __ASM_CPUTYPE_H
  18
  19 #define ID_MIDR_EL1             "midr_el1"
  20 #define ID_MPIDR_EL1            "mpidr_el1"
  21 #define ID_CTR_EL0              "ctr_el0"
  22
  23 #define ID_AA64PFR0_EL1         "id_aa64pfr0_el1"
  24 #define ID_AA64DFR0_EL1         "id_aa64dfr0_el1"
  25 #define ID_AA64AFR0_EL1         "id_aa64afr0_el1"
  26 #define ID_AA64ISAR0_EL1        "id_aa64isar0_el1"
  27 #define ID_AA64MMFR0_EL1        "id_aa64mmfr0_el1"
  28
  29 #define INVALID_HWID            ULONG_MAX
  30
  31 #define MPIDR_HWID_BITMASK      0xff00ffffff
  32
  33 #define MPIDR_LEVEL_BITS_SHIFT  3
  34 #define MPIDR_LEVEL_BITS        (1 << MPIDR_LEVEL_BITS_SHIFT)
  35 #define MPIDR_LEVEL_MASK        ((1 << MPIDR_LEVEL_BITS) - 1)
  36
  37 #define MPIDR_LEVEL_SHIFT(level) \
  38         (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
  39
  40 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  41         ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
  42
  43 #define read_cpuid(reg) ({                                              \
  44         u64 __val;                                                      \
  45         asm("mrs        %0, " reg : "=r" (__val));                      \
  46         __val;                                                          \
  47 })
  48
  49 #define ARM_CPU_IMP_ARM         0x41
  50 #define ARM_CPU_IMP_APM         0x50
  51
  52 #define ARM_CPU_PART_AEM_V8     0xD0F0
  53 #define ARM_CPU_PART_FOUNDATION 0xD000
  54 #define ARM_CPU_PART_CORTEX_A57 0xD070
  55
  56 #define APM_CPU_PART_POTENZA    0x0000
  57
  58 #ifndef __ASSEMBLY__
  59
  60 /*
  61  * The CPU ID never changes at run time, so we might as well tell the
  62  * compiler that it's constant.  Use this function to read the CPU ID
  63  * rather than directly reading processor_id or read_cpuid() directly.
  64  */
  65 static inline u32 __attribute_const__ read_cpuid_id(void)
  66 {
  67         return read_cpuid(ID_MIDR_EL1);
  68 }
  69
  70 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
  71 {
  72         return read_cpuid(ID_MPIDR_EL1);
  73 }
  74
  75 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
  76 {
  77         return (read_cpuid_id() & 0xFF000000) >> 24;
  78 }
  79
  80 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
  81 {
  82         return (read_cpuid_id() & 0xFFF0);
  83 }
  84
  85 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
  86 {
  87         return read_cpuid(ID_CTR_EL0);
  88 }
  89
  90 #endif /* __ASSEMBLY__ */
  91
  92 #endif