arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/mm.h>
  25 #include <linux/uaccess.h>
  26
  27 #include <asm/cacheflush.h>
  28 #include <asm/cputype.h>
  29 #include <asm/debug-monitors.h>
  30 #include <asm/esr.h>
  31 #include <asm/kvm_arm.h>
  32 #include <asm/kvm_asm.h>
  33 #include <asm/kvm_coproc.h>
  34 #include <asm/kvm_emulate.h>
  35 #include <asm/kvm_host.h>
  36 #include <asm/kvm_mmu.h>
  37
  38 #include <trace/events/kvm.h>
  39
  40 #include "sys_regs.h"
  41
  42 #include "trace.h"
  43
  44 /*
  45  * All of this file is extremly similar to the ARM coproc.c, but the
  46  * types are different. My gut feeling is that it should be pretty
  47  * easy to merge, but that would be an ABI breakage -- again. VFP
  48  * would also need to be abstracted.
  49  *
  50  * For AArch32, we only take care of what is being trapped. Anything
  51  * that has to do with init and userspace access has to go via the
  52  * 64bit interface.
  53  */
  54
  55 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  56 static u32 cache_levels;
  57
  58 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  59 #define CSSELR_MAX 12
  60
  61 /* Which cache CCSIDR represents depends on CSSELR value. */
  62 static u32 get_ccsidr(u32 csselr)
  63 {
  64         u32 ccsidr;
  65
  66         /* Make sure noone else changes CSSELR during this! */
  67         local_irq_disable();
  68         /* Put value into CSSELR */
  69         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  70         isb();
  71         /* Read result out of CCSIDR */
  72         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  73         local_irq_enable();
  74
  75         return ccsidr;
  76 }
  77
  78 /*
  79  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  80  */
  81 static bool access_dcsw(struct kvm_vcpu *vcpu,
  82                         struct sys_reg_params *p,
  83                         const struct sys_reg_desc *r)
  84 {
  85         if (!p->is_write)
  86                 return read_from_write_only(vcpu, p);
  87
  88         kvm_set_way_flush(vcpu);
  89         return true;
  90 }
  91
  92 /*
  93  * Generic accessor for VM registers. Only called as long as HCR_TVM
  94  * is set. If the guest enables the MMU, we stop trapping the VM
  95  * sys_regs and leave it in complete control of the caches.
  96  */
  97 static bool access_vm_reg(struct kvm_vcpu *vcpu,
  98                           struct sys_reg_params *p,
  99                           const struct sys_reg_desc *r)
 100 {
 101         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 102
 103         BUG_ON(!p->is_write);
 104
 105         if (!p->is_aarch32) {
 106                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 107         } else {
 108                 if (!p->is_32bit)
 109                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 110                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 111         }
 112
 113         kvm_toggle_cache(vcpu, was_enabled);
 114         return true;
 115 }
 116
 117 /*
 118  * Trap handler for the GICv3 SGI generation system register.
 119  * Forward the request to the VGIC emulation.
 120  * The cp15_64 code makes sure this automatically works
 121  * for both AArch64 and AArch32 accesses.
 122  */
 123 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 124                            struct sys_reg_params *p,
 125                            const struct sys_reg_desc *r)
 126 {
 127         if (!p->is_write)
 128                 return read_from_write_only(vcpu, p);
 129
 130         vgic_v3_dispatch_sgi(vcpu, p->regval);
 131
 132         return true;
 133 }
 134
 135 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 136                         struct sys_reg_params *p,
 137                         const struct sys_reg_desc *r)
 138 {
 139         if (p->is_write)
 140                 return ignore_write(vcpu, p);
 141         else
 142                 return read_zero(vcpu, p);
 143 }
 144
 145 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 146                            struct sys_reg_params *p,
 147                            const struct sys_reg_desc *r)
 148 {
 149         if (p->is_write) {
 150                 return ignore_write(vcpu, p);
 151         } else {
 152                 p->regval = (1 << 3);
 153                 return true;
 154         }
 155 }
 156
 157 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 158                                    struct sys_reg_params *p,
 159                                    const struct sys_reg_desc *r)
 160 {
 161         if (p->is_write) {
 162                 return ignore_write(vcpu, p);
 163         } else {
 164                 u32 val;
 165                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
 166                 p->regval = val;
 167                 return true;
 168         }
 169 }
 170
 171 /*
 172  * We want to avoid world-switching all the DBG registers all the
 173  * time:
 174  *
 175  * - If we've touched any debug register, it is likely that we're
 176  *   going to touch more of them. It then makes sense to disable the
 177  *   traps and start doing the save/restore dance
 178  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 179  *   then mandatory to save/restore the registers, as the guest
 180  *   depends on them.
 181  *
 182  * For this, we use a DIRTY bit, indicating the guest has modified the
 183  * debug registers, used as follow:
 184  *
 185  * On guest entry:
 186  * - If the dirty bit is set (because we're coming back from trapping),
 187  *   disable the traps, save host registers, restore guest registers.
 188  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 189  *   set the dirty bit, disable the traps, save host registers,
 190  *   restore guest registers.
 191  * - Otherwise, enable the traps
 192  *
 193  * On guest exit:
 194  * - If the dirty bit is set, save guest registers, restore host
 195  *   registers and clear the dirty bit. This ensure that the host can
 196  *   now use the debug registers.
 197  */
 198 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 199                             struct sys_reg_params *p,
 200                             const struct sys_reg_desc *r)
 201 {
 202         if (p->is_write) {
 203                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 204                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 205         } else {
 206                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 207         }
 208
 209         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 210
 211         return true;
 212 }
 213
 214 /*
 215  * reg_to_dbg/dbg_to_reg
 216  *
 217  * A 32 bit write to a debug register leave top bits alone
 218  * A 32 bit read from a debug register only returns the bottom bits
 219  *
 220  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 221  * hyp.S code switches between host and guest values in future.
 222  */
 223 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 224                        struct sys_reg_params *p,
 225                        u64 *dbg_reg)
 226 {
 227         u64 val = p->regval;
 228
 229         if (p->is_32bit) {
 230                 val &= 0xffffffffUL;
 231                 val |= ((*dbg_reg >> 32) << 32);
 232         }
 233
 234         *dbg_reg = val;
 235         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 236 }
 237
 238 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 239                        struct sys_reg_params *p,
 240                        u64 *dbg_reg)
 241 {
 242         p->regval = *dbg_reg;
 243         if (p->is_32bit)
 244                 p->regval &= 0xffffffffUL;
 245 }
 246
 247 static bool trap_bvr(struct kvm_vcpu *vcpu,
 248                      struct sys_reg_params *p,
 249                      const struct sys_reg_desc *rd)
 250 {
 251         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 252
 253         if (p->is_write)
 254                 reg_to_dbg(vcpu, p, dbg_reg);
 255         else
 256                 dbg_to_reg(vcpu, p, dbg_reg);
 257
 258         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 259
 260         return true;
 261 }
 262
 263 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 264                 const struct kvm_one_reg *reg, void __user *uaddr)
 265 {
 266         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 267
 268         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 269                 return -EFAULT;
 270         return 0;
 271 }
 272
 273 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 274         const struct kvm_one_reg *reg, void __user *uaddr)
 275 {
 276         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 277
 278         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 279                 return -EFAULT;
 280         return 0;
 281 }
 282
 283 static void reset_bvr(struct kvm_vcpu *vcpu,
 284                       const struct sys_reg_desc *rd)
 285 {
 286         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 287 }
 288
 289 static bool trap_bcr(struct kvm_vcpu *vcpu,
 290                      struct sys_reg_params *p,
 291                      const struct sys_reg_desc *rd)
 292 {
 293         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 294
 295         if (p->is_write)
 296                 reg_to_dbg(vcpu, p, dbg_reg);
 297         else
 298                 dbg_to_reg(vcpu, p, dbg_reg);
 299
 300         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 301
 302         return true;
 303 }
 304
 305 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 306                 const struct kvm_one_reg *reg, void __user *uaddr)
 307 {
 308         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 309
 310         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 311                 return -EFAULT;
 312
 313         return 0;
 314 }
 315
 316 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 317         const struct kvm_one_reg *reg, void __user *uaddr)
 318 {
 319         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 320
 321         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 322                 return -EFAULT;
 323         return 0;
 324 }
 325
 326 static void reset_bcr(struct kvm_vcpu *vcpu,
 327                       const struct sys_reg_desc *rd)
 328 {
 329         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 330 }
 331
 332 static bool trap_wvr(struct kvm_vcpu *vcpu,
 333                      struct sys_reg_params *p,
 334                      const struct sys_reg_desc *rd)
 335 {
 336         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 337
 338         if (p->is_write)
 339                 reg_to_dbg(vcpu, p, dbg_reg);
 340         else
 341                 dbg_to_reg(vcpu, p, dbg_reg);
 342
 343         trace_trap_reg(__func__, rd->reg, p->is_write,
 344                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 345
 346         return true;
 347 }
 348
 349 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 350                 const struct kvm_one_reg *reg, void __user *uaddr)
 351 {
 352         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 353
 354         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 355                 return -EFAULT;
 356         return 0;
 357 }
 358
 359 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 360         const struct kvm_one_reg *reg, void __user *uaddr)
 361 {
 362         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 363
 364         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 365                 return -EFAULT;
 366         return 0;
 367 }
 368
 369 static void reset_wvr(struct kvm_vcpu *vcpu,
 370                       const struct sys_reg_desc *rd)
 371 {
 372         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 373 }
 374
 375 static bool trap_wcr(struct kvm_vcpu *vcpu,
 376                      struct sys_reg_params *p,
 377                      const struct sys_reg_desc *rd)
 378 {
 379         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 380
 381         if (p->is_write)
 382                 reg_to_dbg(vcpu, p, dbg_reg);
 383         else
 384                 dbg_to_reg(vcpu, p, dbg_reg);
 385
 386         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 387
 388         return true;
 389 }
 390
 391 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 392                 const struct kvm_one_reg *reg, void __user *uaddr)
 393 {
 394         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 395
 396         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 397                 return -EFAULT;
 398         return 0;
 399 }
 400
 401 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 402         const struct kvm_one_reg *reg, void __user *uaddr)
 403 {
 404         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 405
 406         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 407                 return -EFAULT;
 408         return 0;
 409 }
 410
 411 static void reset_wcr(struct kvm_vcpu *vcpu,
 412                       const struct sys_reg_desc *rd)
 413 {
 414         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 415 }
 416
 417 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 418 {
 419         u64 amair;
 420
 421         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 422         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 423 }
 424
 425 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 426 {
 427         u64 mpidr;
 428
 429         /*
 430          * Map the vcpu_id into the first three affinity level fields of
 431          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 432          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 433          * of the GICv3 to be able to address each CPU directly when
 434          * sending IPIs.
 435          */
 436         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 437         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 438         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 439         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 440 }
 441
 442 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 443 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 444         /* DBGBVRn_EL1 */                                               \
 445         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 446           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 447         /* DBGBCRn_EL1 */                                               \
 448         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 449           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 450         /* DBGWVRn_EL1 */                                               \
 451         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 452           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 453         /* DBGWCRn_EL1 */                                               \
 454         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 455           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 456
 457 /*
 458  * Architected system registers.
 459  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 460  *
 461  * We could trap ID_DFR0 and tell the guest we don't support performance
 462  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 463  * NAKed, so it will read the PMCR anyway.
 464  *
 465  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 466  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 467  * all PM registers, which doesn't crash the guest kernel at least.
 468  *
 469  * Debug handling: We do trap most, if not all debug related system
 470  * registers. The implementation is good enough to ensure that a guest
 471  * can use these with minimal performance degradation. The drawback is
 472  * that we don't implement any of the external debug, none of the
 473  * OSlock protocol. This should be revisited if we ever encounter a
 474  * more demanding guest...
 475  */
 476 static const struct sys_reg_desc sys_reg_descs[] = {
 477         /* DC ISW */
 478         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 479           access_dcsw },
 480         /* DC CSW */
 481         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 482           access_dcsw },
 483         /* DC CISW */
 484         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 485           access_dcsw },
 486
 487         DBG_BCR_BVR_WCR_WVR_EL1(0),
 488         DBG_BCR_BVR_WCR_WVR_EL1(1),
 489         /* MDCCINT_EL1 */
 490         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 491           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 492         /* MDSCR_EL1 */
 493         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 494           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 495         DBG_BCR_BVR_WCR_WVR_EL1(2),
 496         DBG_BCR_BVR_WCR_WVR_EL1(3),
 497         DBG_BCR_BVR_WCR_WVR_EL1(4),
 498         DBG_BCR_BVR_WCR_WVR_EL1(5),
 499         DBG_BCR_BVR_WCR_WVR_EL1(6),
 500         DBG_BCR_BVR_WCR_WVR_EL1(7),
 501         DBG_BCR_BVR_WCR_WVR_EL1(8),
 502         DBG_BCR_BVR_WCR_WVR_EL1(9),
 503         DBG_BCR_BVR_WCR_WVR_EL1(10),
 504         DBG_BCR_BVR_WCR_WVR_EL1(11),
 505         DBG_BCR_BVR_WCR_WVR_EL1(12),
 506         DBG_BCR_BVR_WCR_WVR_EL1(13),
 507         DBG_BCR_BVR_WCR_WVR_EL1(14),
 508         DBG_BCR_BVR_WCR_WVR_EL1(15),
 509
 510         /* MDRAR_EL1 */
 511         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 512           trap_raz_wi },
 513         /* OSLAR_EL1 */
 514         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 515           trap_raz_wi },
 516         /* OSLSR_EL1 */
 517         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 518           trap_oslsr_el1 },
 519         /* OSDLR_EL1 */
 520         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 521           trap_raz_wi },
 522         /* DBGPRCR_EL1 */
 523         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 524           trap_raz_wi },
 525         /* DBGCLAIMSET_EL1 */
 526         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 527           trap_raz_wi },
 528         /* DBGCLAIMCLR_EL1 */
 529         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 530           trap_raz_wi },
 531         /* DBGAUTHSTATUS_EL1 */
 532         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 533           trap_dbgauthstatus_el1 },
 534
 535         /* MDCCSR_EL1 */
 536         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 537           trap_raz_wi },
 538         /* DBGDTR_EL0 */
 539         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 540           trap_raz_wi },
 541         /* DBGDTR[TR]X_EL0 */
 542         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 543           trap_raz_wi },
 544
 545         /* DBGVCR32_EL2 */
 546         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 547           NULL, reset_val, DBGVCR32_EL2, 0 },
 548
 549         /* MPIDR_EL1 */
 550         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 551           NULL, reset_mpidr, MPIDR_EL1 },
 552         /* SCTLR_EL1 */
 553         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 554           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 555         /* CPACR_EL1 */
 556         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 557           NULL, reset_val, CPACR_EL1, 0 },
 558         /* TTBR0_EL1 */
 559         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 560           access_vm_reg, reset_unknown, TTBR0_EL1 },
 561         /* TTBR1_EL1 */
 562         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 563           access_vm_reg, reset_unknown, TTBR1_EL1 },
 564         /* TCR_EL1 */
 565         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 566           access_vm_reg, reset_val, TCR_EL1, 0 },
 567
 568         /* AFSR0_EL1 */
 569         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 570           access_vm_reg, reset_unknown, AFSR0_EL1 },
 571         /* AFSR1_EL1 */
 572         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 573           access_vm_reg, reset_unknown, AFSR1_EL1 },
 574         /* ESR_EL1 */
 575         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 576           access_vm_reg, reset_unknown, ESR_EL1 },
 577         /* FAR_EL1 */
 578         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 579           access_vm_reg, reset_unknown, FAR_EL1 },
 580         /* PAR_EL1 */
 581         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 582           NULL, reset_unknown, PAR_EL1 },
 583
 584         /* PMINTENSET_EL1 */
 585         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 586           trap_raz_wi },
 587         /* PMINTENCLR_EL1 */
 588         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 589           trap_raz_wi },
 590
 591         /* MAIR_EL1 */
 592         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 593           access_vm_reg, reset_unknown, MAIR_EL1 },
 594         /* AMAIR_EL1 */
 595         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 596           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 597
 598         /* VBAR_EL1 */
 599         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 600           NULL, reset_val, VBAR_EL1, 0 },
 601
 602         /* ICC_SGI1R_EL1 */
 603         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
 604           access_gic_sgi },
 605         /* ICC_SRE_EL1 */
 606         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 607           trap_raz_wi },
 608
 609         /* CONTEXTIDR_EL1 */
 610         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 611           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 612         /* TPIDR_EL1 */
 613         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 614           NULL, reset_unknown, TPIDR_EL1 },
 615
 616         /* CNTKCTL_EL1 */
 617         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 618           NULL, reset_val, CNTKCTL_EL1, 0},
 619
 620         /* CSSELR_EL1 */
 621         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 622           NULL, reset_unknown, CSSELR_EL1 },
 623
 624         /* PMCR_EL0 */
 625         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 626           trap_raz_wi },
 627         /* PMCNTENSET_EL0 */
 628         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 629           trap_raz_wi },
 630         /* PMCNTENCLR_EL0 */
 631         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 632           trap_raz_wi },
 633         /* PMOVSCLR_EL0 */
 634         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 635           trap_raz_wi },
 636         /* PMSWINC_EL0 */
 637         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 638           trap_raz_wi },
 639         /* PMSELR_EL0 */
 640         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 641           trap_raz_wi },
 642         /* PMCEID0_EL0 */
 643         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 644           trap_raz_wi },
 645         /* PMCEID1_EL0 */
 646         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 647           trap_raz_wi },
 648         /* PMCCNTR_EL0 */
 649         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
 650           trap_raz_wi },
 651         /* PMXEVTYPER_EL0 */
 652         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
 653           trap_raz_wi },
 654         /* PMXEVCNTR_EL0 */
 655         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 656           trap_raz_wi },
 657         /* PMUSERENR_EL0 */
 658         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 659           trap_raz_wi },
 660         /* PMOVSSET_EL0 */
 661         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
 662           trap_raz_wi },
 663
 664         /* TPIDR_EL0 */
 665         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
 666           NULL, reset_unknown, TPIDR_EL0 },
 667         /* TPIDRRO_EL0 */
 668         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 669           NULL, reset_unknown, TPIDRRO_EL0 },
 670
 671         /* DACR32_EL2 */
 672         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 673           NULL, reset_unknown, DACR32_EL2 },
 674         /* IFSR32_EL2 */
 675         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
 676           NULL, reset_unknown, IFSR32_EL2 },
 677         /* FPEXC32_EL2 */
 678         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
 679           NULL, reset_val, FPEXC32_EL2, 0x70 },
 680 };
 681
 682 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
 683                         struct sys_reg_params *p,
 684                         const struct sys_reg_desc *r)
 685 {
 686         if (p->is_write) {
 687                 return ignore_write(vcpu, p);
 688         } else {
 689                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
 690                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
 691                 u32 el3 = !!cpuid_feature_extract_field(pfr, ID_AA64PFR0_EL3_SHIFT);
 692
 693                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
 694                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
 695                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
 696                              | (6 << 16) | (el3 << 14) | (el3 << 12));
 697                 return true;
 698         }
 699 }
 700
 701 static bool trap_debug32(struct kvm_vcpu *vcpu,
 702                          struct sys_reg_params *p,
 703                          const struct sys_reg_desc *r)
 704 {
 705         if (p->is_write) {
 706                 vcpu_cp14(vcpu, r->reg) = p->regval;
 707                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 708         } else {
 709                 p->regval = vcpu_cp14(vcpu, r->reg);
 710         }
 711
 712         return true;
 713 }
 714
 715 /* AArch32 debug register mappings
 716  *
 717  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
 718  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
 719  *
 720  * All control registers and watchpoint value registers are mapped to
 721  * the lower 32 bits of their AArch64 equivalents. We share the trap
 722  * handlers with the above AArch64 code which checks what mode the
 723  * system is in.
 724  */
 725
 726 static bool trap_xvr(struct kvm_vcpu *vcpu,
 727                      struct sys_reg_params *p,
 728                      const struct sys_reg_desc *rd)
 729 {
 730         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 731
 732         if (p->is_write) {
 733                 u64 val = *dbg_reg;
 734
 735                 val &= 0xffffffffUL;
 736                 val |= p->regval << 32;
 737                 *dbg_reg = val;
 738
 739                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 740         } else {
 741                 p->regval = *dbg_reg >> 32;
 742         }
 743
 744         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 745
 746         return true;
 747 }
 748
 749 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
 750         /* DBGBVRn */                                                   \
 751         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
 752         /* DBGBCRn */                                                   \
 753         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
 754         /* DBGWVRn */                                                   \
 755         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
 756         /* DBGWCRn */                                                   \
 757         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
 758
 759 #define DBGBXVR(n)                                                      \
 760         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
 761
 762 /*
 763  * Trapped cp14 registers. We generally ignore most of the external
 764  * debug, on the principle that they don't really make sense to a
 765  * guest. Revisit this one day, would this principle change.
 766  */
 767 static const struct sys_reg_desc cp14_regs[] = {
 768         /* DBGIDR */
 769         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
 770         /* DBGDTRRXext */
 771         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
 772
 773         DBG_BCR_BVR_WCR_WVR(0),
 774         /* DBGDSCRint */
 775         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
 776         DBG_BCR_BVR_WCR_WVR(1),
 777         /* DBGDCCINT */
 778         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
 779         /* DBGDSCRext */
 780         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
 781         DBG_BCR_BVR_WCR_WVR(2),
 782         /* DBGDTR[RT]Xint */
 783         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
 784         /* DBGDTR[RT]Xext */
 785         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
 786         DBG_BCR_BVR_WCR_WVR(3),
 787         DBG_BCR_BVR_WCR_WVR(4),
 788         DBG_BCR_BVR_WCR_WVR(5),
 789         /* DBGWFAR */
 790         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
 791         /* DBGOSECCR */
 792         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
 793         DBG_BCR_BVR_WCR_WVR(6),
 794         /* DBGVCR */
 795         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
 796         DBG_BCR_BVR_WCR_WVR(7),
 797         DBG_BCR_BVR_WCR_WVR(8),
 798         DBG_BCR_BVR_WCR_WVR(9),
 799         DBG_BCR_BVR_WCR_WVR(10),
 800         DBG_BCR_BVR_WCR_WVR(11),
 801         DBG_BCR_BVR_WCR_WVR(12),
 802         DBG_BCR_BVR_WCR_WVR(13),
 803         DBG_BCR_BVR_WCR_WVR(14),
 804         DBG_BCR_BVR_WCR_WVR(15),
 805
 806         /* DBGDRAR (32bit) */
 807         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
 808
 809         DBGBXVR(0),
 810         /* DBGOSLAR */
 811         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
 812         DBGBXVR(1),
 813         /* DBGOSLSR */
 814         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
 815         DBGBXVR(2),
 816         DBGBXVR(3),
 817         /* DBGOSDLR */
 818         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
 819         DBGBXVR(4),
 820         /* DBGPRCR */
 821         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
 822         DBGBXVR(5),
 823         DBGBXVR(6),
 824         DBGBXVR(7),
 825         DBGBXVR(8),
 826         DBGBXVR(9),
 827         DBGBXVR(10),
 828         DBGBXVR(11),
 829         DBGBXVR(12),
 830         DBGBXVR(13),
 831         DBGBXVR(14),
 832         DBGBXVR(15),
 833
 834         /* DBGDSAR (32bit) */
 835         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
 836
 837         /* DBGDEVID2 */
 838         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
 839         /* DBGDEVID1 */
 840         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
 841         /* DBGDEVID */
 842         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
 843         /* DBGCLAIMSET */
 844         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
 845         /* DBGCLAIMCLR */
 846         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
 847         /* DBGAUTHSTATUS */
 848         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
 849 };
 850
 851 /* Trapped cp14 64bit registers */
 852 static const struct sys_reg_desc cp14_64_regs[] = {
 853         /* DBGDRAR (64bit) */
 854         { Op1( 0), CRm( 1), .access = trap_raz_wi },
 855
 856         /* DBGDSAR (64bit) */
 857         { Op1( 0), CRm( 2), .access = trap_raz_wi },
 858 };
 859
 860 /*
 861  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 862  * depending on the way they are accessed (as a 32bit or a 64bit
 863  * register).
 864  */
 865 static const struct sys_reg_desc cp15_regs[] = {
 866         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
 867
 868         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
 869         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 870         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
 871         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
 872         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
 873         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
 874         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
 875         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
 876         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
 877         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
 878         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
 879
 880         /*
 881          * DC{C,I,CI}SW operations:
 882          */
 883         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
 884         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
 885         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 886
 887         /* PMU */
 888         { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
 889         { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 890         { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 891         { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
 892         { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
 893         { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 894         { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 895         { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
 896         { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
 897         { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
 898         { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 899         { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
 900         { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
 901
 902         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
 903         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
 904         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
 905         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 906
 907         /* ICC_SRE */
 908         { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
 909
 910         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 911 };
 912
 913 static const struct sys_reg_desc cp15_64_regs[] = {
 914         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 915         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
 916         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 917 };
 918
 919 /* Target specific emulation tables */
 920 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 921
 922 void kvm_register_target_sys_reg_table(unsigned int target,
 923                                        struct kvm_sys_reg_target_table *table)
 924 {
 925         target_tables[target] = table;
 926 }
 927
 928 /* Get specific register table for this target. */
 929 static const struct sys_reg_desc *get_target_table(unsigned target,
 930                                                    bool mode_is_64,
 931                                                    size_t *num)
 932 {
 933         struct kvm_sys_reg_target_table *table;
 934
 935         table = target_tables[target];
 936         if (mode_is_64) {
 937                 *num = table->table64.num;
 938                 return table->table64.table;
 939         } else {
 940                 *num = table->table32.num;
 941                 return table->table32.table;
 942         }
 943 }
 944
 945 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 946                                          const struct sys_reg_desc table[],
 947                                          unsigned int num)
 948 {
 949         unsigned int i;
 950
 951         for (i = 0; i < num; i++) {
 952                 const struct sys_reg_desc *r = &table[i];
 953
 954                 if (params->Op0 != r->Op0)
 955                         continue;
 956                 if (params->Op1 != r->Op1)
 957                         continue;
 958                 if (params->CRn != r->CRn)
 959                         continue;
 960                 if (params->CRm != r->CRm)
 961                         continue;
 962                 if (params->Op2 != r->Op2)
 963                         continue;
 964
 965                 return r;
 966         }
 967         return NULL;
 968 }
 969
 970 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 971 {
 972         kvm_inject_undefined(vcpu);
 973         return 1;
 974 }
 975
 976 /*
 977  * emulate_cp --  tries to match a sys_reg access in a handling table, and
 978  *                call the corresponding trap handler.
 979  *
 980  * @params: pointer to the descriptor of the access
 981  * @table: array of trap descriptors
 982  * @num: size of the trap descriptor array
 983  *
 984  * Return 0 if the access has been handled, and -1 if not.
 985  */
 986 static int emulate_cp(struct kvm_vcpu *vcpu,
 987                       struct sys_reg_params *params,
 988                       const struct sys_reg_desc *table,
 989                       size_t num)
 990 {
 991         const struct sys_reg_desc *r;
 992
 993         if (!table)
 994                 return -1;      /* Not handled */
 995
 996         r = find_reg(params, table, num);
 997
 998         if (r) {
 999                 /*
1000                  * Not having an accessor means that we have
1001                  * configured a trap that we don't know how to
1002                  * handle. This certainly qualifies as a gross bug
1003                  * that should be fixed right away.
1004                  */
1005                 BUG_ON(!r->access);
1006
1007                 if (likely(r->access(vcpu, params, r))) {
1008                         /* Skip instruction, since it was emulated */
1009                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1010                 }
1011
1012                 /* Handled */
1013                 return 0;
1014         }
1015
1016         /* Not handled */
1017         return -1;
1018 }
1019
1020 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1021                                 struct sys_reg_params *params)
1022 {
1023         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1024         int cp;
1025
1026         switch(hsr_ec) {
1027         case ESR_ELx_EC_CP15_32:
1028         case ESR_ELx_EC_CP15_64:
1029                 cp = 15;
1030                 break;
1031         case ESR_ELx_EC_CP14_MR:
1032         case ESR_ELx_EC_CP14_64:
1033                 cp = 14;
1034                 break;
1035         default:
1036                 WARN_ON((cp = -1));
1037         }
1038
1039         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1040                 cp, *vcpu_pc(vcpu));
1041         print_sys_reg_instr(params);
1042         kvm_inject_undefined(vcpu);
1043 }
1044
1045 /**
1046  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
1047  * @vcpu: The VCPU pointer
1048  * @run:  The kvm_run struct
1049  */
1050 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1051                             const struct sys_reg_desc *global,
1052                             size_t nr_global,
1053                             const struct sys_reg_desc *target_specific,
1054                             size_t nr_specific)
1055 {
1056         struct sys_reg_params params;
1057         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1058         int Rt = (hsr >> 5) & 0xf;
1059         int Rt2 = (hsr >> 10) & 0xf;
1060
1061         params.is_aarch32 = true;
1062         params.is_32bit = false;
1063         params.CRm = (hsr >> 1) & 0xf;
1064         params.is_write = ((hsr & 1) == 0);
1065
1066         params.Op0 = 0;
1067         params.Op1 = (hsr >> 16) & 0xf;
1068         params.Op2 = 0;
1069         params.CRn = 0;
1070
1071         /*
1072          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1073          * backends between AArch32 and AArch64, we get away with it.
1074          */
1075         if (params.is_write) {
1076                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1077                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1078         }
1079
1080         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1081                 goto out;
1082         if (!emulate_cp(vcpu, &params, global, nr_global))
1083                 goto out;
1084
1085         unhandled_cp_access(vcpu, &params);
1086
1087 out:
1088         /* Split up the value between registers for the read side */
1089         if (!params.is_write) {
1090                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1091                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1092         }
1093
1094         return 1;
1095 }
1096
1097 /**
1098  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
1099  * @vcpu: The VCPU pointer
1100  * @run:  The kvm_run struct
1101  */
1102 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1103                             const struct sys_reg_desc *global,
1104                             size_t nr_global,
1105                             const struct sys_reg_desc *target_specific,
1106                             size_t nr_specific)
1107 {
1108         struct sys_reg_params params;
1109         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1110         int Rt  = (hsr >> 5) & 0xf;
1111
1112         params.is_aarch32 = true;
1113         params.is_32bit = true;
1114         params.CRm = (hsr >> 1) & 0xf;
1115         params.regval = vcpu_get_reg(vcpu, Rt);
1116         params.is_write = ((hsr & 1) == 0);
1117         params.CRn = (hsr >> 10) & 0xf;
1118         params.Op0 = 0;
1119         params.Op1 = (hsr >> 14) & 0x7;
1120         params.Op2 = (hsr >> 17) & 0x7;
1121
1122         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1123             !emulate_cp(vcpu, &params, global, nr_global)) {
1124                 if (!params.is_write)
1125                         vcpu_set_reg(vcpu, Rt, params.regval);
1126                 return 1;
1127         }
1128
1129         unhandled_cp_access(vcpu, &params);
1130         return 1;
1131 }
1132
1133 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1134 {
1135         const struct sys_reg_desc *target_specific;
1136         size_t num;
1137
1138         target_specific = get_target_table(vcpu->arch.target, false, &num);
1139         return kvm_handle_cp_64(vcpu,
1140                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1141                                 target_specific, num);
1142 }
1143
1144 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1145 {
1146         const struct sys_reg_desc *target_specific;
1147         size_t num;
1148
1149         target_specific = get_target_table(vcpu->arch.target, false, &num);
1150         return kvm_handle_cp_32(vcpu,
1151                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1152                                 target_specific, num);
1153 }
1154
1155 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1156 {
1157         return kvm_handle_cp_64(vcpu,
1158                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1159                                 NULL, 0);
1160 }
1161
1162 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1163 {
1164         return kvm_handle_cp_32(vcpu,
1165                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1166                                 NULL, 0);
1167 }
1168
1169 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1170                            struct sys_reg_params *params)
1171 {
1172         size_t num;
1173         const struct sys_reg_desc *table, *r;
1174
1175         table = get_target_table(vcpu->arch.target, true, &num);
1176
1177         /* Search target-specific then generic table. */
1178         r = find_reg(params, table, num);
1179         if (!r)
1180                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1181
1182         if (likely(r)) {
1183                 /*
1184                  * Not having an accessor means that we have
1185                  * configured a trap that we don't know how to
1186                  * handle. This certainly qualifies as a gross bug
1187                  * that should be fixed right away.
1188                  */
1189                 BUG_ON(!r->access);
1190
1191                 if (likely(r->access(vcpu, params, r))) {
1192                         /* Skip instruction, since it was emulated */
1193                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1194                         return 1;
1195                 }
1196                 /* If access function fails, it should complain. */
1197         } else {
1198                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1199                         *vcpu_pc(vcpu));
1200                 print_sys_reg_instr(params);
1201         }
1202         kvm_inject_undefined(vcpu);
1203         return 1;
1204 }
1205
1206 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1207                               const struct sys_reg_desc *table, size_t num)
1208 {
1209         unsigned long i;
1210
1211         for (i = 0; i < num; i++)
1212                 if (table[i].reset)
1213                         table[i].reset(vcpu, &table[i]);
1214 }
1215
1216 /**
1217  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1218  * @vcpu: The VCPU pointer
1219  * @run:  The kvm_run struct
1220  */
1221 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1222 {
1223         struct sys_reg_params params;
1224         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1225         int Rt = (esr >> 5) & 0x1f;
1226         int ret;
1227
1228         trace_kvm_handle_sys_reg(esr);
1229
1230         params.is_aarch32 = false;
1231         params.is_32bit = false;
1232         params.Op0 = (esr >> 20) & 3;
1233         params.Op1 = (esr >> 14) & 0x7;
1234         params.CRn = (esr >> 10) & 0xf;
1235         params.CRm = (esr >> 1) & 0xf;
1236         params.Op2 = (esr >> 17) & 0x7;
1237         params.regval = vcpu_get_reg(vcpu, Rt);
1238         params.is_write = !(esr & 1);
1239
1240         ret = emulate_sys_reg(vcpu, &params);
1241
1242         if (!params.is_write)
1243                 vcpu_set_reg(vcpu, Rt, params.regval);
1244         return ret;
1245 }
1246
1247 /******************************************************************************
1248  * Userspace API
1249  *****************************************************************************/
1250
1251 static bool index_to_params(u64 id, struct sys_reg_params *params)
1252 {
1253         switch (id & KVM_REG_SIZE_MASK) {
1254         case KVM_REG_SIZE_U64:
1255                 /* Any unused index bits means it's not valid. */
1256                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1257                               | KVM_REG_ARM_COPROC_MASK
1258                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1259                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1260                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1261                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1262                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1263                         return false;
1264                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1265                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1266                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1267                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1268                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1269                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1270                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1271                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1272                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1273                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1274                 return true;
1275         default:
1276                 return false;
1277         }
1278 }
1279
1280 /* Decode an index value, and find the sys_reg_desc entry. */
1281 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1282                                                     u64 id)
1283 {
1284         size_t num;
1285         const struct sys_reg_desc *table, *r;
1286         struct sys_reg_params params;
1287
1288         /* We only do sys_reg for now. */
1289         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1290                 return NULL;
1291
1292         if (!index_to_params(id, &params))
1293                 return NULL;
1294
1295         table = get_target_table(vcpu->arch.target, true, &num);
1296         r = find_reg(&params, table, num);
1297         if (!r)
1298                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1299
1300         /* Not saved in the sys_reg array? */
1301         if (r && !r->reg)
1302                 r = NULL;
1303
1304         return r;
1305 }
1306
1307 /*
1308  * These are the invariant sys_reg registers: we let the guest see the
1309  * host versions of these, so they're part of the guest state.
1310  *
1311  * A future CPU may provide a mechanism to present different values to
1312  * the guest, or a future kvm may trap them.
1313  */
1314
1315 #define FUNCTION_INVARIANT(reg)                                         \
1316         static void get_##reg(struct kvm_vcpu *v,                       \
1317                               const struct sys_reg_desc *r)             \
1318         {                                                               \
1319                 u64 val;                                                \
1320                                                                         \
1321                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
1322                              : "=r" (val));                             \
1323                 ((struct sys_reg_desc *)r)->val = val;                  \
1324         }
1325
1326 FUNCTION_INVARIANT(midr_el1)
1327 FUNCTION_INVARIANT(ctr_el0)
1328 FUNCTION_INVARIANT(revidr_el1)
1329 FUNCTION_INVARIANT(id_pfr0_el1)
1330 FUNCTION_INVARIANT(id_pfr1_el1)
1331 FUNCTION_INVARIANT(id_dfr0_el1)
1332 FUNCTION_INVARIANT(id_afr0_el1)
1333 FUNCTION_INVARIANT(id_mmfr0_el1)
1334 FUNCTION_INVARIANT(id_mmfr1_el1)
1335 FUNCTION_INVARIANT(id_mmfr2_el1)
1336 FUNCTION_INVARIANT(id_mmfr3_el1)
1337 FUNCTION_INVARIANT(id_isar0_el1)
1338 FUNCTION_INVARIANT(id_isar1_el1)
1339 FUNCTION_INVARIANT(id_isar2_el1)
1340 FUNCTION_INVARIANT(id_isar3_el1)
1341 FUNCTION_INVARIANT(id_isar4_el1)
1342 FUNCTION_INVARIANT(id_isar5_el1)
1343 FUNCTION_INVARIANT(clidr_el1)
1344 FUNCTION_INVARIANT(aidr_el1)
1345
1346 /* ->val is filled in by kvm_sys_reg_table_init() */
1347 static struct sys_reg_desc invariant_sys_regs[] = {
1348         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1349           NULL, get_midr_el1 },
1350         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1351           NULL, get_revidr_el1 },
1352         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1353           NULL, get_id_pfr0_el1 },
1354         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1355           NULL, get_id_pfr1_el1 },
1356         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1357           NULL, get_id_dfr0_el1 },
1358         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1359           NULL, get_id_afr0_el1 },
1360         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1361           NULL, get_id_mmfr0_el1 },
1362         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1363           NULL, get_id_mmfr1_el1 },
1364         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1365           NULL, get_id_mmfr2_el1 },
1366         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1367           NULL, get_id_mmfr3_el1 },
1368         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1369           NULL, get_id_isar0_el1 },
1370         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1371           NULL, get_id_isar1_el1 },
1372         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1373           NULL, get_id_isar2_el1 },
1374         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1375           NULL, get_id_isar3_el1 },
1376         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1377           NULL, get_id_isar4_el1 },
1378         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1379           NULL, get_id_isar5_el1 },
1380         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1381           NULL, get_clidr_el1 },
1382         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1383           NULL, get_aidr_el1 },
1384         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1385           NULL, get_ctr_el0 },
1386 };
1387
1388 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1389 {
1390         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1391                 return -EFAULT;
1392         return 0;
1393 }
1394
1395 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1396 {
1397         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1398                 return -EFAULT;
1399         return 0;
1400 }
1401
1402 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1403 {
1404         struct sys_reg_params params;
1405         const struct sys_reg_desc *r;
1406
1407         if (!index_to_params(id, &params))
1408                 return -ENOENT;
1409
1410         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1411         if (!r)
1412                 return -ENOENT;
1413
1414         return reg_to_user(uaddr, &r->val, id);
1415 }
1416
1417 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1418 {
1419         struct sys_reg_params params;
1420         const struct sys_reg_desc *r;
1421         int err;
1422         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1423
1424         if (!index_to_params(id, &params))
1425                 return -ENOENT;
1426         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1427         if (!r)
1428                 return -ENOENT;
1429
1430         err = reg_from_user(&val, uaddr, id);
1431         if (err)
1432                 return err;
1433
1434         /* This is what we mean by invariant: you can't change it. */
1435         if (r->val != val)
1436                 return -EINVAL;
1437
1438         return 0;
1439 }
1440
1441 static bool is_valid_cache(u32 val)
1442 {
1443         u32 level, ctype;
1444
1445         if (val >= CSSELR_MAX)
1446                 return false;
1447
1448         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1449         level = (val >> 1);
1450         ctype = (cache_levels >> (level * 3)) & 7;
1451
1452         switch (ctype) {
1453         case 0: /* No cache */
1454                 return false;
1455         case 1: /* Instruction cache only */
1456                 return (val & 1);
1457         case 2: /* Data cache only */
1458         case 4: /* Unified cache */
1459                 return !(val & 1);
1460         case 3: /* Separate instruction and data caches */
1461                 return true;
1462         default: /* Reserved: we can't know instruction or data. */
1463                 return false;
1464         }
1465 }
1466
1467 static int demux_c15_get(u64 id, void __user *uaddr)
1468 {
1469         u32 val;
1470         u32 __user *uval = uaddr;
1471
1472         /* Fail if we have unknown bits set. */
1473         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1474                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1475                 return -ENOENT;
1476
1477         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1478         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1479                 if (KVM_REG_SIZE(id) != 4)
1480                         return -ENOENT;
1481                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1482                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1483                 if (!is_valid_cache(val))
1484                         return -ENOENT;
1485
1486                 return put_user(get_ccsidr(val), uval);
1487         default:
1488                 return -ENOENT;
1489         }
1490 }
1491
1492 static int demux_c15_set(u64 id, void __user *uaddr)
1493 {
1494         u32 val, newval;
1495         u32 __user *uval = uaddr;
1496
1497         /* Fail if we have unknown bits set. */
1498         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1499                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1500                 return -ENOENT;
1501
1502         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1503         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1504                 if (KVM_REG_SIZE(id) != 4)
1505                         return -ENOENT;
1506                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1507                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1508                 if (!is_valid_cache(val))
1509                         return -ENOENT;
1510
1511                 if (get_user(newval, uval))
1512                         return -EFAULT;
1513
1514                 /* This is also invariant: you can't change it. */
1515                 if (newval != get_ccsidr(val))
1516                         return -EINVAL;
1517                 return 0;
1518         default:
1519                 return -ENOENT;
1520         }
1521 }
1522
1523 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1524 {
1525         const struct sys_reg_desc *r;
1526         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1527
1528         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1529                 return demux_c15_get(reg->id, uaddr);
1530
1531         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1532                 return -ENOENT;
1533
1534         r = index_to_sys_reg_desc(vcpu, reg->id);
1535         if (!r)
1536                 return get_invariant_sys_reg(reg->id, uaddr);
1537
1538         if (r->get_user)
1539                 return (r->get_user)(vcpu, r, reg, uaddr);
1540
1541         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1542 }
1543
1544 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1545 {
1546         const struct sys_reg_desc *r;
1547         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1548
1549         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1550                 return demux_c15_set(reg->id, uaddr);
1551
1552         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1553                 return -ENOENT;
1554
1555         r = index_to_sys_reg_desc(vcpu, reg->id);
1556         if (!r)
1557                 return set_invariant_sys_reg(reg->id, uaddr);
1558
1559         if (r->set_user)
1560                 return (r->set_user)(vcpu, r, reg, uaddr);
1561
1562         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1563 }
1564
1565 static unsigned int num_demux_regs(void)
1566 {
1567         unsigned int i, count = 0;
1568
1569         for (i = 0; i < CSSELR_MAX; i++)
1570                 if (is_valid_cache(i))
1571                         count++;
1572
1573         return count;
1574 }
1575
1576 static int write_demux_regids(u64 __user *uindices)
1577 {
1578         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1579         unsigned int i;
1580
1581         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1582         for (i = 0; i < CSSELR_MAX; i++) {
1583                 if (!is_valid_cache(i))
1584                         continue;
1585                 if (put_user(val | i, uindices))
1586                         return -EFAULT;
1587                 uindices++;
1588         }
1589         return 0;
1590 }
1591
1592 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1593 {
1594         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1595                 KVM_REG_ARM64_SYSREG |
1596                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1597                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1598                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1599                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1600                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1601 }
1602
1603 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1604 {
1605         if (!*uind)
1606                 return true;
1607
1608         if (put_user(sys_reg_to_index(reg), *uind))
1609                 return false;
1610
1611         (*uind)++;
1612         return true;
1613 }
1614
1615 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1616 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1617 {
1618         const struct sys_reg_desc *i1, *i2, *end1, *end2;
1619         unsigned int total = 0;
1620         size_t num;
1621
1622         /* We check for duplicates here, to allow arch-specific overrides. */
1623         i1 = get_target_table(vcpu->arch.target, true, &num);
1624         end1 = i1 + num;
1625         i2 = sys_reg_descs;
1626         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1627
1628         BUG_ON(i1 == end1 || i2 == end2);
1629
1630         /* Walk carefully, as both tables may refer to the same register. */
1631         while (i1 || i2) {
1632                 int cmp = cmp_sys_reg(i1, i2);
1633                 /* target-specific overrides generic entry. */
1634                 if (cmp <= 0) {
1635                         /* Ignore registers we trap but don't save. */
1636                         if (i1->reg) {
1637                                 if (!copy_reg_to_user(i1, &uind))
1638                                         return -EFAULT;
1639                                 total++;
1640                         }
1641                 } else {
1642                         /* Ignore registers we trap but don't save. */
1643                         if (i2->reg) {
1644                                 if (!copy_reg_to_user(i2, &uind))
1645                                         return -EFAULT;
1646                                 total++;
1647                         }
1648                 }
1649
1650                 if (cmp <= 0 && ++i1 == end1)
1651                         i1 = NULL;
1652                 if (cmp >= 0 && ++i2 == end2)
1653                         i2 = NULL;
1654         }
1655         return total;
1656 }
1657
1658 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1659 {
1660         return ARRAY_SIZE(invariant_sys_regs)
1661                 + num_demux_regs()
1662                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1663 }
1664
1665 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1666 {
1667         unsigned int i;
1668         int err;
1669
1670         /* Then give them all the invariant registers' indices. */
1671         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1672                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1673                         return -EFAULT;
1674                 uindices++;
1675         }
1676
1677         err = walk_sys_regs(vcpu, uindices);
1678         if (err < 0)
1679                 return err;
1680         uindices += err;
1681
1682         return write_demux_regids(uindices);
1683 }
1684
1685 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1686 {
1687         unsigned int i;
1688
1689         for (i = 1; i < n; i++) {
1690                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1691                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1692                         return 1;
1693                 }
1694         }
1695
1696         return 0;
1697 }
1698
1699 void kvm_sys_reg_table_init(void)
1700 {
1701         unsigned int i;
1702         struct sys_reg_desc clidr;
1703
1704         /* Make sure tables are unique and in order. */
1705         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1706         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1707         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1708         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1709         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1710         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
1711
1712         /* We abuse the reset function to overwrite the table itself. */
1713         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1714                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1715
1716         /*
1717          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1718          *
1719          *   If software reads the Cache Type fields from Ctype1
1720          *   upwards, once it has seen a value of 0b000, no caches
1721          *   exist at further-out levels of the hierarchy. So, for
1722          *   example, if Ctype3 is the first Cache Type field with a
1723          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1724          *   ignored.
1725          */
1726         get_clidr_el1(NULL, &clidr); /* Ugly... */
1727         cache_levels = clidr.val;
1728         for (i = 0; i < 7; i++)
1729                 if (((cache_levels >> (i*3)) & 7) == 0)
1730                         break;
1731         /* Clear all higher bits. */
1732         cache_levels &= (1 << (i*3))-1;
1733 }
1734
1735 /**
1736  * kvm_reset_sys_regs - sets system registers to reset value
1737  * @vcpu: The VCPU pointer
1738  *
1739  * This function finds the right table above and sets the registers on the
1740  * virtual CPU struct to their architecturally defined reset values.
1741  */
1742 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1743 {
1744         size_t num;
1745         const struct sys_reg_desc *table;
1746
1747         /* Catch someone adding a register without putting in reset entry. */
1748         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1749
1750         /* Generic chip reset first (so target could override). */
1751         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1752
1753         table = get_target_table(vcpu->arch.target, true, &num);
1754         reset_sys_reg_descs(vcpu, table, num);
1755
1756         for (num = 1; num < NR_SYS_REGS; num++)
1757                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1758                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
1759 }