arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/uaccess.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/cputype.h>
  30 #include <asm/debug-monitors.h>
  31 #include <asm/esr.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_asm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_mmu.h>
  38 #include <asm/perf_event.h>
  39 #include <asm/sysreg.h>
  40
  41 #include <trace/events/kvm.h>
  42
  43 #include "sys_regs.h"
  44
  45 #include "trace.h"
  46
  47 /*
  48  * All of this file is extremly similar to the ARM coproc.c, but the
  49  * types are different. My gut feeling is that it should be pretty
  50  * easy to merge, but that would be an ABI breakage -- again. VFP
  51  * would also need to be abstracted.
  52  *
  53  * For AArch32, we only take care of what is being trapped. Anything
  54  * that has to do with init and userspace access has to go via the
  55  * 64bit interface.
  56  */
  57
  58 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  59 static u32 cache_levels;
  60
  61 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  62 #define CSSELR_MAX 12
  63
  64 /* Which cache CCSIDR represents depends on CSSELR value. */
  65 static u32 get_ccsidr(u32 csselr)
  66 {
  67         u32 ccsidr;
  68
  69         /* Make sure noone else changes CSSELR during this! */
  70         local_irq_disable();
  71         write_sysreg(csselr, csselr_el1);
  72         isb();
  73         ccsidr = read_sysreg(ccsidr_el1);
  74         local_irq_enable();
  75
  76         return ccsidr;
  77 }
  78
  79 /*
  80  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  81  */
  82 static bool access_dcsw(struct kvm_vcpu *vcpu,
  83                         struct sys_reg_params *p,
  84                         const struct sys_reg_desc *r)
  85 {
  86         if (!p->is_write)
  87                 return read_from_write_only(vcpu, p);
  88
  89         kvm_set_way_flush(vcpu);
  90         return true;
  91 }
  92
  93 /*
  94  * Generic accessor for VM registers. Only called as long as HCR_TVM
  95  * is set. If the guest enables the MMU, we stop trapping the VM
  96  * sys_regs and leave it in complete control of the caches.
  97  */
  98 static bool access_vm_reg(struct kvm_vcpu *vcpu,
  99                           struct sys_reg_params *p,
 100                           const struct sys_reg_desc *r)
 101 {
 102         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 103
 104         BUG_ON(!p->is_write);
 105
 106         if (!p->is_aarch32) {
 107                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 108         } else {
 109                 if (!p->is_32bit)
 110                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 111                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 112         }
 113
 114         kvm_toggle_cache(vcpu, was_enabled);
 115         return true;
 116 }
 117
 118 /*
 119  * Trap handler for the GICv3 SGI generation system register.
 120  * Forward the request to the VGIC emulation.
 121  * The cp15_64 code makes sure this automatically works
 122  * for both AArch64 and AArch32 accesses.
 123  */
 124 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 125                            struct sys_reg_params *p,
 126                            const struct sys_reg_desc *r)
 127 {
 128         if (!p->is_write)
 129                 return read_from_write_only(vcpu, p);
 130
 131         vgic_v3_dispatch_sgi(vcpu, p->regval);
 132
 133         return true;
 134 }
 135
 136 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 137                            struct sys_reg_params *p,
 138                            const struct sys_reg_desc *r)
 139 {
 140         if (p->is_write)
 141                 return ignore_write(vcpu, p);
 142
 143         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 144         return true;
 145 }
 146
 147 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 148                         struct sys_reg_params *p,
 149                         const struct sys_reg_desc *r)
 150 {
 151         if (p->is_write)
 152                 return ignore_write(vcpu, p);
 153         else
 154                 return read_zero(vcpu, p);
 155 }
 156
 157 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 158                            struct sys_reg_params *p,
 159                            const struct sys_reg_desc *r)
 160 {
 161         if (p->is_write) {
 162                 return ignore_write(vcpu, p);
 163         } else {
 164                 p->regval = (1 << 3);
 165                 return true;
 166         }
 167 }
 168
 169 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 170                                    struct sys_reg_params *p,
 171                                    const struct sys_reg_desc *r)
 172 {
 173         if (p->is_write) {
 174                 return ignore_write(vcpu, p);
 175         } else {
 176                 p->regval = read_sysreg(dbgauthstatus_el1);
 177                 return true;
 178         }
 179 }
 180
 181 /*
 182  * We want to avoid world-switching all the DBG registers all the
 183  * time:
 184  *
 185  * - If we've touched any debug register, it is likely that we're
 186  *   going to touch more of them. It then makes sense to disable the
 187  *   traps and start doing the save/restore dance
 188  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 189  *   then mandatory to save/restore the registers, as the guest
 190  *   depends on them.
 191  *
 192  * For this, we use a DIRTY bit, indicating the guest has modified the
 193  * debug registers, used as follow:
 194  *
 195  * On guest entry:
 196  * - If the dirty bit is set (because we're coming back from trapping),
 197  *   disable the traps, save host registers, restore guest registers.
 198  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 199  *   set the dirty bit, disable the traps, save host registers,
 200  *   restore guest registers.
 201  * - Otherwise, enable the traps
 202  *
 203  * On guest exit:
 204  * - If the dirty bit is set, save guest registers, restore host
 205  *   registers and clear the dirty bit. This ensure that the host can
 206  *   now use the debug registers.
 207  */
 208 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 209                             struct sys_reg_params *p,
 210                             const struct sys_reg_desc *r)
 211 {
 212         if (p->is_write) {
 213                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 214                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 215         } else {
 216                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 217         }
 218
 219         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 220
 221         return true;
 222 }
 223
 224 /*
 225  * reg_to_dbg/dbg_to_reg
 226  *
 227  * A 32 bit write to a debug register leave top bits alone
 228  * A 32 bit read from a debug register only returns the bottom bits
 229  *
 230  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 231  * hyp.S code switches between host and guest values in future.
 232  */
 233 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 234                        struct sys_reg_params *p,
 235                        u64 *dbg_reg)
 236 {
 237         u64 val = p->regval;
 238
 239         if (p->is_32bit) {
 240                 val &= 0xffffffffUL;
 241                 val |= ((*dbg_reg >> 32) << 32);
 242         }
 243
 244         *dbg_reg = val;
 245         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 246 }
 247
 248 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 249                        struct sys_reg_params *p,
 250                        u64 *dbg_reg)
 251 {
 252         p->regval = *dbg_reg;
 253         if (p->is_32bit)
 254                 p->regval &= 0xffffffffUL;
 255 }
 256
 257 static bool trap_bvr(struct kvm_vcpu *vcpu,
 258                      struct sys_reg_params *p,
 259                      const struct sys_reg_desc *rd)
 260 {
 261         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 262
 263         if (p->is_write)
 264                 reg_to_dbg(vcpu, p, dbg_reg);
 265         else
 266                 dbg_to_reg(vcpu, p, dbg_reg);
 267
 268         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 269
 270         return true;
 271 }
 272
 273 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 274                 const struct kvm_one_reg *reg, void __user *uaddr)
 275 {
 276         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 277
 278         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 279                 return -EFAULT;
 280         return 0;
 281 }
 282
 283 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 284         const struct kvm_one_reg *reg, void __user *uaddr)
 285 {
 286         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 287
 288         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 289                 return -EFAULT;
 290         return 0;
 291 }
 292
 293 static void reset_bvr(struct kvm_vcpu *vcpu,
 294                       const struct sys_reg_desc *rd)
 295 {
 296         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 297 }
 298
 299 static bool trap_bcr(struct kvm_vcpu *vcpu,
 300                      struct sys_reg_params *p,
 301                      const struct sys_reg_desc *rd)
 302 {
 303         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 304
 305         if (p->is_write)
 306                 reg_to_dbg(vcpu, p, dbg_reg);
 307         else
 308                 dbg_to_reg(vcpu, p, dbg_reg);
 309
 310         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 311
 312         return true;
 313 }
 314
 315 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 316                 const struct kvm_one_reg *reg, void __user *uaddr)
 317 {
 318         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 319
 320         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 321                 return -EFAULT;
 322
 323         return 0;
 324 }
 325
 326 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 327         const struct kvm_one_reg *reg, void __user *uaddr)
 328 {
 329         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 330
 331         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 332                 return -EFAULT;
 333         return 0;
 334 }
 335
 336 static void reset_bcr(struct kvm_vcpu *vcpu,
 337                       const struct sys_reg_desc *rd)
 338 {
 339         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 340 }
 341
 342 static bool trap_wvr(struct kvm_vcpu *vcpu,
 343                      struct sys_reg_params *p,
 344                      const struct sys_reg_desc *rd)
 345 {
 346         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 347
 348         if (p->is_write)
 349                 reg_to_dbg(vcpu, p, dbg_reg);
 350         else
 351                 dbg_to_reg(vcpu, p, dbg_reg);
 352
 353         trace_trap_reg(__func__, rd->reg, p->is_write,
 354                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 355
 356         return true;
 357 }
 358
 359 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 360                 const struct kvm_one_reg *reg, void __user *uaddr)
 361 {
 362         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 363
 364         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 365                 return -EFAULT;
 366         return 0;
 367 }
 368
 369 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 370         const struct kvm_one_reg *reg, void __user *uaddr)
 371 {
 372         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 373
 374         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 375                 return -EFAULT;
 376         return 0;
 377 }
 378
 379 static void reset_wvr(struct kvm_vcpu *vcpu,
 380                       const struct sys_reg_desc *rd)
 381 {
 382         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 383 }
 384
 385 static bool trap_wcr(struct kvm_vcpu *vcpu,
 386                      struct sys_reg_params *p,
 387                      const struct sys_reg_desc *rd)
 388 {
 389         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 390
 391         if (p->is_write)
 392                 reg_to_dbg(vcpu, p, dbg_reg);
 393         else
 394                 dbg_to_reg(vcpu, p, dbg_reg);
 395
 396         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 397
 398         return true;
 399 }
 400
 401 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 402                 const struct kvm_one_reg *reg, void __user *uaddr)
 403 {
 404         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 405
 406         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 407                 return -EFAULT;
 408         return 0;
 409 }
 410
 411 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 412         const struct kvm_one_reg *reg, void __user *uaddr)
 413 {
 414         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 415
 416         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 417                 return -EFAULT;
 418         return 0;
 419 }
 420
 421 static void reset_wcr(struct kvm_vcpu *vcpu,
 422                       const struct sys_reg_desc *rd)
 423 {
 424         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 425 }
 426
 427 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 428 {
 429         vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
 430 }
 431
 432 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 433 {
 434         u64 mpidr;
 435
 436         /*
 437          * Map the vcpu_id into the first three affinity level fields of
 438          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 439          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 440          * of the GICv3 to be able to address each CPU directly when
 441          * sending IPIs.
 442          */
 443         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 444         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 445         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 446         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 447 }
 448
 449 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 450 {
 451         u64 pmcr, val;
 452
 453         pmcr = read_sysreg(pmcr_el0);
 454         /*
 455          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 456          * except PMCR.E resetting to zero.
 457          */
 458         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 459                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 460         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 461 }
 462
 463 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 464 {
 465         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 466
 467         return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
 468 }
 469
 470 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 471 {
 472         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 473
 474         return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
 475                  || vcpu_mode_priv(vcpu));
 476 }
 477
 478 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 479 {
 480         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 481
 482         return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
 483                  || vcpu_mode_priv(vcpu));
 484 }
 485
 486 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 487 {
 488         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 489
 490         return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
 491                  || vcpu_mode_priv(vcpu));
 492 }
 493
 494 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 495                         const struct sys_reg_desc *r)
 496 {
 497         u64 val;
 498
 499         if (!kvm_arm_pmu_v3_ready(vcpu))
 500                 return trap_raz_wi(vcpu, p, r);
 501
 502         if (pmu_access_el0_disabled(vcpu))
 503                 return false;
 504
 505         if (p->is_write) {
 506                 /* Only update writeable bits of PMCR */
 507                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
 508                 val &= ~ARMV8_PMU_PMCR_MASK;
 509                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 510                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 511                 kvm_pmu_handle_pmcr(vcpu, val);
 512         } else {
 513                 /* PMCR.P & PMCR.C are RAZ */
 514                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
 515                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 516                 p->regval = val;
 517         }
 518
 519         return true;
 520 }
 521
 522 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 523                           const struct sys_reg_desc *r)
 524 {
 525         if (!kvm_arm_pmu_v3_ready(vcpu))
 526                 return trap_raz_wi(vcpu, p, r);
 527
 528         if (pmu_access_event_counter_el0_disabled(vcpu))
 529                 return false;
 530
 531         if (p->is_write)
 532                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 533         else
 534                 /* return PMSELR.SEL field */
 535                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
 536                             & ARMV8_PMU_COUNTER_MASK;
 537
 538         return true;
 539 }
 540
 541 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 542                           const struct sys_reg_desc *r)
 543 {
 544         u64 pmceid;
 545
 546         if (!kvm_arm_pmu_v3_ready(vcpu))
 547                 return trap_raz_wi(vcpu, p, r);
 548
 549         BUG_ON(p->is_write);
 550
 551         if (pmu_access_el0_disabled(vcpu))
 552                 return false;
 553
 554         if (!(p->Op2 & 1))
 555                 pmceid = read_sysreg(pmceid0_el0);
 556         else
 557                 pmceid = read_sysreg(pmceid1_el0);
 558
 559         p->regval = pmceid;
 560
 561         return true;
 562 }
 563
 564 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 565 {
 566         u64 pmcr, val;
 567
 568         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
 569         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 570         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
 571                 return false;
 572
 573         return true;
 574 }
 575
 576 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 577                               struct sys_reg_params *p,
 578                               const struct sys_reg_desc *r)
 579 {
 580         u64 idx;
 581
 582         if (!kvm_arm_pmu_v3_ready(vcpu))
 583                 return trap_raz_wi(vcpu, p, r);
 584
 585         if (r->CRn == 9 && r->CRm == 13) {
 586                 if (r->Op2 == 2) {
 587                         /* PMXEVCNTR_EL0 */
 588                         if (pmu_access_event_counter_el0_disabled(vcpu))
 589                                 return false;
 590
 591                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
 592                               & ARMV8_PMU_COUNTER_MASK;
 593                 } else if (r->Op2 == 0) {
 594                         /* PMCCNTR_EL0 */
 595                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 596                                 return false;
 597
 598                         idx = ARMV8_PMU_CYCLE_IDX;
 599                 } else {
 600                         BUG();
 601                 }
 602         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 603                 /* PMEVCNTRn_EL0 */
 604                 if (pmu_access_event_counter_el0_disabled(vcpu))
 605                         return false;
 606
 607                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 608         } else {
 609                 BUG();
 610         }
 611
 612         if (!pmu_counter_idx_valid(vcpu, idx))
 613                 return false;
 614
 615         if (p->is_write) {
 616                 if (pmu_access_el0_disabled(vcpu))
 617                         return false;
 618
 619                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 620         } else {
 621                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 622         }
 623
 624         return true;
 625 }
 626
 627 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 628                                const struct sys_reg_desc *r)
 629 {
 630         u64 idx, reg;
 631
 632         if (!kvm_arm_pmu_v3_ready(vcpu))
 633                 return trap_raz_wi(vcpu, p, r);
 634
 635         if (pmu_access_el0_disabled(vcpu))
 636                 return false;
 637
 638         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 639                 /* PMXEVTYPER_EL0 */
 640                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 641                 reg = PMEVTYPER0_EL0 + idx;
 642         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 643                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 644                 if (idx == ARMV8_PMU_CYCLE_IDX)
 645                         reg = PMCCFILTR_EL0;
 646                 else
 647                         /* PMEVTYPERn_EL0 */
 648                         reg = PMEVTYPER0_EL0 + idx;
 649         } else {
 650                 BUG();
 651         }
 652
 653         if (!pmu_counter_idx_valid(vcpu, idx))
 654                 return false;
 655
 656         if (p->is_write) {
 657                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 658                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 659         } else {
 660                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 661         }
 662
 663         return true;
 664 }
 665
 666 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 667                            const struct sys_reg_desc *r)
 668 {
 669         u64 val, mask;
 670
 671         if (!kvm_arm_pmu_v3_ready(vcpu))
 672                 return trap_raz_wi(vcpu, p, r);
 673
 674         if (pmu_access_el0_disabled(vcpu))
 675                 return false;
 676
 677         mask = kvm_pmu_valid_counter_mask(vcpu);
 678         if (p->is_write) {
 679                 val = p->regval & mask;
 680                 if (r->Op2 & 0x1) {
 681                         /* accessing PMCNTENSET_EL0 */
 682                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 683                         kvm_pmu_enable_counter(vcpu, val);
 684                 } else {
 685                         /* accessing PMCNTENCLR_EL0 */
 686                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 687                         kvm_pmu_disable_counter(vcpu, val);
 688                 }
 689         } else {
 690                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 691         }
 692
 693         return true;
 694 }
 695
 696 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 697                            const struct sys_reg_desc *r)
 698 {
 699         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 700
 701         if (!kvm_arm_pmu_v3_ready(vcpu))
 702                 return trap_raz_wi(vcpu, p, r);
 703
 704         if (!vcpu_mode_priv(vcpu))
 705                 return false;
 706
 707         if (p->is_write) {
 708                 u64 val = p->regval & mask;
 709
 710                 if (r->Op2 & 0x1)
 711                         /* accessing PMINTENSET_EL1 */
 712                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 713                 else
 714                         /* accessing PMINTENCLR_EL1 */
 715                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 716         } else {
 717                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 718         }
 719
 720         return true;
 721 }
 722
 723 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 724                          const struct sys_reg_desc *r)
 725 {
 726         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 727
 728         if (!kvm_arm_pmu_v3_ready(vcpu))
 729                 return trap_raz_wi(vcpu, p, r);
 730
 731         if (pmu_access_el0_disabled(vcpu))
 732                 return false;
 733
 734         if (p->is_write) {
 735                 if (r->CRm & 0x2)
 736                         /* accessing PMOVSSET_EL0 */
 737                         kvm_pmu_overflow_set(vcpu, p->regval & mask);
 738                 else
 739                         /* accessing PMOVSCLR_EL0 */
 740                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 741         } else {
 742                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 743         }
 744
 745         return true;
 746 }
 747
 748 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 749                            const struct sys_reg_desc *r)
 750 {
 751         u64 mask;
 752
 753         if (!kvm_arm_pmu_v3_ready(vcpu))
 754                 return trap_raz_wi(vcpu, p, r);
 755
 756         if (pmu_write_swinc_el0_disabled(vcpu))
 757                 return false;
 758
 759         if (p->is_write) {
 760                 mask = kvm_pmu_valid_counter_mask(vcpu);
 761                 kvm_pmu_software_increment(vcpu, p->regval & mask);
 762                 return true;
 763         }
 764
 765         return false;
 766 }
 767
 768 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 769                              const struct sys_reg_desc *r)
 770 {
 771         if (!kvm_arm_pmu_v3_ready(vcpu))
 772                 return trap_raz_wi(vcpu, p, r);
 773
 774         if (p->is_write) {
 775                 if (!vcpu_mode_priv(vcpu))
 776                         return false;
 777
 778                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
 779                                                     & ARMV8_PMU_USERENR_MASK;
 780         } else {
 781                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 782                             & ARMV8_PMU_USERENR_MASK;
 783         }
 784
 785         return true;
 786 }
 787
 788 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 789 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 790         /* DBGBVRn_EL1 */                                               \
 791         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 792           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 793         /* DBGBCRn_EL1 */                                               \
 794         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 795           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 796         /* DBGWVRn_EL1 */                                               \
 797         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 798           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 799         /* DBGWCRn_EL1 */                                               \
 800         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 801           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 802
 803 /* Macro to expand the PMEVCNTRn_EL0 register */
 804 #define PMU_PMEVCNTR_EL0(n)                                             \
 805         /* PMEVCNTRn_EL0 */                                             \
 806         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 807           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 808           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 809
 810 /* Macro to expand the PMEVTYPERn_EL0 register */
 811 #define PMU_PMEVTYPER_EL0(n)                                            \
 812         /* PMEVTYPERn_EL0 */                                            \
 813         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 814           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 815           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 816
 817 /*
 818  * Architected system registers.
 819  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 820  *
 821  * Debug handling: We do trap most, if not all debug related system
 822  * registers. The implementation is good enough to ensure that a guest
 823  * can use these with minimal performance degradation. The drawback is
 824  * that we don't implement any of the external debug, none of the
 825  * OSlock protocol. This should be revisited if we ever encounter a
 826  * more demanding guest...
 827  */
 828 static const struct sys_reg_desc sys_reg_descs[] = {
 829         /* DC ISW */
 830         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 831           access_dcsw },
 832         /* DC CSW */
 833         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 834           access_dcsw },
 835         /* DC CISW */
 836         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 837           access_dcsw },
 838
 839         DBG_BCR_BVR_WCR_WVR_EL1(0),
 840         DBG_BCR_BVR_WCR_WVR_EL1(1),
 841         /* MDCCINT_EL1 */
 842         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 843           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 844         /* MDSCR_EL1 */
 845         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 846           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 847         DBG_BCR_BVR_WCR_WVR_EL1(2),
 848         DBG_BCR_BVR_WCR_WVR_EL1(3),
 849         DBG_BCR_BVR_WCR_WVR_EL1(4),
 850         DBG_BCR_BVR_WCR_WVR_EL1(5),
 851         DBG_BCR_BVR_WCR_WVR_EL1(6),
 852         DBG_BCR_BVR_WCR_WVR_EL1(7),
 853         DBG_BCR_BVR_WCR_WVR_EL1(8),
 854         DBG_BCR_BVR_WCR_WVR_EL1(9),
 855         DBG_BCR_BVR_WCR_WVR_EL1(10),
 856         DBG_BCR_BVR_WCR_WVR_EL1(11),
 857         DBG_BCR_BVR_WCR_WVR_EL1(12),
 858         DBG_BCR_BVR_WCR_WVR_EL1(13),
 859         DBG_BCR_BVR_WCR_WVR_EL1(14),
 860         DBG_BCR_BVR_WCR_WVR_EL1(15),
 861
 862         /* MDRAR_EL1 */
 863         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 864           trap_raz_wi },
 865         /* OSLAR_EL1 */
 866         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 867           trap_raz_wi },
 868         /* OSLSR_EL1 */
 869         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 870           trap_oslsr_el1 },
 871         /* OSDLR_EL1 */
 872         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 873           trap_raz_wi },
 874         /* DBGPRCR_EL1 */
 875         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 876           trap_raz_wi },
 877         /* DBGCLAIMSET_EL1 */
 878         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 879           trap_raz_wi },
 880         /* DBGCLAIMCLR_EL1 */
 881         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 882           trap_raz_wi },
 883         /* DBGAUTHSTATUS_EL1 */
 884         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 885           trap_dbgauthstatus_el1 },
 886
 887         /* MDCCSR_EL1 */
 888         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 889           trap_raz_wi },
 890         /* DBGDTR_EL0 */
 891         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 892           trap_raz_wi },
 893         /* DBGDTR[TR]X_EL0 */
 894         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 895           trap_raz_wi },
 896
 897         /* DBGVCR32_EL2 */
 898         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 899           NULL, reset_val, DBGVCR32_EL2, 0 },
 900
 901         /* MPIDR_EL1 */
 902         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 903           NULL, reset_mpidr, MPIDR_EL1 },
 904         /* SCTLR_EL1 */
 905         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 906           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 907         /* CPACR_EL1 */
 908         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 909           NULL, reset_val, CPACR_EL1, 0 },
 910         /* TTBR0_EL1 */
 911         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 912           access_vm_reg, reset_unknown, TTBR0_EL1 },
 913         /* TTBR1_EL1 */
 914         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 915           access_vm_reg, reset_unknown, TTBR1_EL1 },
 916         /* TCR_EL1 */
 917         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 918           access_vm_reg, reset_val, TCR_EL1, 0 },
 919
 920         /* AFSR0_EL1 */
 921         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 922           access_vm_reg, reset_unknown, AFSR0_EL1 },
 923         /* AFSR1_EL1 */
 924         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 925           access_vm_reg, reset_unknown, AFSR1_EL1 },
 926         /* ESR_EL1 */
 927         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 928           access_vm_reg, reset_unknown, ESR_EL1 },
 929         /* FAR_EL1 */
 930         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 931           access_vm_reg, reset_unknown, FAR_EL1 },
 932         /* PAR_EL1 */
 933         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 934           NULL, reset_unknown, PAR_EL1 },
 935
 936         /* PMINTENSET_EL1 */
 937         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 938           access_pminten, reset_unknown, PMINTENSET_EL1 },
 939         /* PMINTENCLR_EL1 */
 940         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 941           access_pminten, NULL, PMINTENSET_EL1 },
 942
 943         /* MAIR_EL1 */
 944         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 945           access_vm_reg, reset_unknown, MAIR_EL1 },
 946         /* AMAIR_EL1 */
 947         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 948           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 949
 950         /* VBAR_EL1 */
 951         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 952           NULL, reset_val, VBAR_EL1, 0 },
 953
 954         /* ICC_SGI1R_EL1 */
 955         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
 956           access_gic_sgi },
 957         /* ICC_SRE_EL1 */
 958         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 959           access_gic_sre },
 960
 961         /* CONTEXTIDR_EL1 */
 962         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 963           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 964         /* TPIDR_EL1 */
 965         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 966           NULL, reset_unknown, TPIDR_EL1 },
 967
 968         /* CNTKCTL_EL1 */
 969         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 970           NULL, reset_val, CNTKCTL_EL1, 0},
 971
 972         /* CSSELR_EL1 */
 973         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 974           NULL, reset_unknown, CSSELR_EL1 },
 975
 976         /* PMCR_EL0 */
 977         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 978           access_pmcr, reset_pmcr, },
 979         /* PMCNTENSET_EL0 */
 980         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 981           access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
 982         /* PMCNTENCLR_EL0 */
 983         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 984           access_pmcnten, NULL, PMCNTENSET_EL0 },
 985         /* PMOVSCLR_EL0 */
 986         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 987           access_pmovs, NULL, PMOVSSET_EL0 },
 988         /* PMSWINC_EL0 */
 989         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 990           access_pmswinc, reset_unknown, PMSWINC_EL0 },
 991         /* PMSELR_EL0 */
 992         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 993           access_pmselr, reset_unknown, PMSELR_EL0 },
 994         /* PMCEID0_EL0 */
 995         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 996           access_pmceid },
 997         /* PMCEID1_EL0 */
 998         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 999           access_pmceid },
1000         /* PMCCNTR_EL0 */
1001         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
1002           access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1003         /* PMXEVTYPER_EL0 */
1004         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
1005           access_pmu_evtyper },
1006         /* PMXEVCNTR_EL0 */
1007         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
1008           access_pmu_evcntr },
1009         /* PMUSERENR_EL0
1010          * This register resets as unknown in 64bit mode while it resets as zero
1011          * in 32bit mode. Here we choose to reset it as zero for consistency.
1012          */
1013         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
1014           access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1015         /* PMOVSSET_EL0 */
1016         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
1017           access_pmovs, reset_unknown, PMOVSSET_EL0 },
1018
1019         /* TPIDR_EL0 */
1020         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1021           NULL, reset_unknown, TPIDR_EL0 },
1022         /* TPIDRRO_EL0 */
1023         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1024           NULL, reset_unknown, TPIDRRO_EL0 },
1025
1026         /* PMEVCNTRn_EL0 */
1027         PMU_PMEVCNTR_EL0(0),
1028         PMU_PMEVCNTR_EL0(1),
1029         PMU_PMEVCNTR_EL0(2),
1030         PMU_PMEVCNTR_EL0(3),
1031         PMU_PMEVCNTR_EL0(4),
1032         PMU_PMEVCNTR_EL0(5),
1033         PMU_PMEVCNTR_EL0(6),
1034         PMU_PMEVCNTR_EL0(7),
1035         PMU_PMEVCNTR_EL0(8),
1036         PMU_PMEVCNTR_EL0(9),
1037         PMU_PMEVCNTR_EL0(10),
1038         PMU_PMEVCNTR_EL0(11),
1039         PMU_PMEVCNTR_EL0(12),
1040         PMU_PMEVCNTR_EL0(13),
1041         PMU_PMEVCNTR_EL0(14),
1042         PMU_PMEVCNTR_EL0(15),
1043         PMU_PMEVCNTR_EL0(16),
1044         PMU_PMEVCNTR_EL0(17),
1045         PMU_PMEVCNTR_EL0(18),
1046         PMU_PMEVCNTR_EL0(19),
1047         PMU_PMEVCNTR_EL0(20),
1048         PMU_PMEVCNTR_EL0(21),
1049         PMU_PMEVCNTR_EL0(22),
1050         PMU_PMEVCNTR_EL0(23),
1051         PMU_PMEVCNTR_EL0(24),
1052         PMU_PMEVCNTR_EL0(25),
1053         PMU_PMEVCNTR_EL0(26),
1054         PMU_PMEVCNTR_EL0(27),
1055         PMU_PMEVCNTR_EL0(28),
1056         PMU_PMEVCNTR_EL0(29),
1057         PMU_PMEVCNTR_EL0(30),
1058         /* PMEVTYPERn_EL0 */
1059         PMU_PMEVTYPER_EL0(0),
1060         PMU_PMEVTYPER_EL0(1),
1061         PMU_PMEVTYPER_EL0(2),
1062         PMU_PMEVTYPER_EL0(3),
1063         PMU_PMEVTYPER_EL0(4),
1064         PMU_PMEVTYPER_EL0(5),
1065         PMU_PMEVTYPER_EL0(6),
1066         PMU_PMEVTYPER_EL0(7),
1067         PMU_PMEVTYPER_EL0(8),
1068         PMU_PMEVTYPER_EL0(9),
1069         PMU_PMEVTYPER_EL0(10),
1070         PMU_PMEVTYPER_EL0(11),
1071         PMU_PMEVTYPER_EL0(12),
1072         PMU_PMEVTYPER_EL0(13),
1073         PMU_PMEVTYPER_EL0(14),
1074         PMU_PMEVTYPER_EL0(15),
1075         PMU_PMEVTYPER_EL0(16),
1076         PMU_PMEVTYPER_EL0(17),
1077         PMU_PMEVTYPER_EL0(18),
1078         PMU_PMEVTYPER_EL0(19),
1079         PMU_PMEVTYPER_EL0(20),
1080         PMU_PMEVTYPER_EL0(21),
1081         PMU_PMEVTYPER_EL0(22),
1082         PMU_PMEVTYPER_EL0(23),
1083         PMU_PMEVTYPER_EL0(24),
1084         PMU_PMEVTYPER_EL0(25),
1085         PMU_PMEVTYPER_EL0(26),
1086         PMU_PMEVTYPER_EL0(27),
1087         PMU_PMEVTYPER_EL0(28),
1088         PMU_PMEVTYPER_EL0(29),
1089         PMU_PMEVTYPER_EL0(30),
1090         /* PMCCFILTR_EL0
1091          * This register resets as unknown in 64bit mode while it resets as zero
1092          * in 32bit mode. Here we choose to reset it as zero for consistency.
1093          */
1094         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1095           access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1096
1097         /* DACR32_EL2 */
1098         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1099           NULL, reset_unknown, DACR32_EL2 },
1100         /* IFSR32_EL2 */
1101         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1102           NULL, reset_unknown, IFSR32_EL2 },
1103         /* FPEXC32_EL2 */
1104         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1105           NULL, reset_val, FPEXC32_EL2, 0x70 },
1106 };
1107
1108 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1109                         struct sys_reg_params *p,
1110                         const struct sys_reg_desc *r)
1111 {
1112         if (p->is_write) {
1113                 return ignore_write(vcpu, p);
1114         } else {
1115                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1116                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1117                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1118
1119                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1120                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1121                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1122                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1123                 return true;
1124         }
1125 }
1126
1127 static bool trap_debug32(struct kvm_vcpu *vcpu,
1128                          struct sys_reg_params *p,
1129                          const struct sys_reg_desc *r)
1130 {
1131         if (p->is_write) {
1132                 vcpu_cp14(vcpu, r->reg) = p->regval;
1133                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1134         } else {
1135                 p->regval = vcpu_cp14(vcpu, r->reg);
1136         }
1137
1138         return true;
1139 }
1140
1141 /* AArch32 debug register mappings
1142  *
1143  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1144  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1145  *
1146  * All control registers and watchpoint value registers are mapped to
1147  * the lower 32 bits of their AArch64 equivalents. We share the trap
1148  * handlers with the above AArch64 code which checks what mode the
1149  * system is in.
1150  */
1151
1152 static bool trap_xvr(struct kvm_vcpu *vcpu,
1153                      struct sys_reg_params *p,
1154                      const struct sys_reg_desc *rd)
1155 {
1156         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1157
1158         if (p->is_write) {
1159                 u64 val = *dbg_reg;
1160
1161                 val &= 0xffffffffUL;
1162                 val |= p->regval << 32;
1163                 *dbg_reg = val;
1164
1165                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1166         } else {
1167                 p->regval = *dbg_reg >> 32;
1168         }
1169
1170         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1171
1172         return true;
1173 }
1174
1175 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1176         /* DBGBVRn */                                                   \
1177         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1178         /* DBGBCRn */                                                   \
1179         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1180         /* DBGWVRn */                                                   \
1181         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1182         /* DBGWCRn */                                                   \
1183         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1184
1185 #define DBGBXVR(n)                                                      \
1186         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1187
1188 /*
1189  * Trapped cp14 registers. We generally ignore most of the external
1190  * debug, on the principle that they don't really make sense to a
1191  * guest. Revisit this one day, would this principle change.
1192  */
1193 static const struct sys_reg_desc cp14_regs[] = {
1194         /* DBGIDR */
1195         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1196         /* DBGDTRRXext */
1197         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1198
1199         DBG_BCR_BVR_WCR_WVR(0),
1200         /* DBGDSCRint */
1201         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1202         DBG_BCR_BVR_WCR_WVR(1),
1203         /* DBGDCCINT */
1204         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1205         /* DBGDSCRext */
1206         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1207         DBG_BCR_BVR_WCR_WVR(2),
1208         /* DBGDTR[RT]Xint */
1209         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1210         /* DBGDTR[RT]Xext */
1211         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1212         DBG_BCR_BVR_WCR_WVR(3),
1213         DBG_BCR_BVR_WCR_WVR(4),
1214         DBG_BCR_BVR_WCR_WVR(5),
1215         /* DBGWFAR */
1216         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1217         /* DBGOSECCR */
1218         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1219         DBG_BCR_BVR_WCR_WVR(6),
1220         /* DBGVCR */
1221         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1222         DBG_BCR_BVR_WCR_WVR(7),
1223         DBG_BCR_BVR_WCR_WVR(8),
1224         DBG_BCR_BVR_WCR_WVR(9),
1225         DBG_BCR_BVR_WCR_WVR(10),
1226         DBG_BCR_BVR_WCR_WVR(11),
1227         DBG_BCR_BVR_WCR_WVR(12),
1228         DBG_BCR_BVR_WCR_WVR(13),
1229         DBG_BCR_BVR_WCR_WVR(14),
1230         DBG_BCR_BVR_WCR_WVR(15),
1231
1232         /* DBGDRAR (32bit) */
1233         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1234
1235         DBGBXVR(0),
1236         /* DBGOSLAR */
1237         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1238         DBGBXVR(1),
1239         /* DBGOSLSR */
1240         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1241         DBGBXVR(2),
1242         DBGBXVR(3),
1243         /* DBGOSDLR */
1244         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1245         DBGBXVR(4),
1246         /* DBGPRCR */
1247         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1248         DBGBXVR(5),
1249         DBGBXVR(6),
1250         DBGBXVR(7),
1251         DBGBXVR(8),
1252         DBGBXVR(9),
1253         DBGBXVR(10),
1254         DBGBXVR(11),
1255         DBGBXVR(12),
1256         DBGBXVR(13),
1257         DBGBXVR(14),
1258         DBGBXVR(15),
1259
1260         /* DBGDSAR (32bit) */
1261         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1262
1263         /* DBGDEVID2 */
1264         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1265         /* DBGDEVID1 */
1266         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1267         /* DBGDEVID */
1268         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1269         /* DBGCLAIMSET */
1270         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1271         /* DBGCLAIMCLR */
1272         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1273         /* DBGAUTHSTATUS */
1274         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1275 };
1276
1277 /* Trapped cp14 64bit registers */
1278 static const struct sys_reg_desc cp14_64_regs[] = {
1279         /* DBGDRAR (64bit) */
1280         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1281
1282         /* DBGDSAR (64bit) */
1283         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1284 };
1285
1286 /* Macro to expand the PMEVCNTRn register */
1287 #define PMU_PMEVCNTR(n)                                                 \
1288         /* PMEVCNTRn */                                                 \
1289         { Op1(0), CRn(0b1110),                                          \
1290           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1291           access_pmu_evcntr }
1292
1293 /* Macro to expand the PMEVTYPERn register */
1294 #define PMU_PMEVTYPER(n)                                                \
1295         /* PMEVTYPERn */                                                \
1296         { Op1(0), CRn(0b1110),                                          \
1297           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1298           access_pmu_evtyper }
1299
1300 /*
1301  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1302  * depending on the way they are accessed (as a 32bit or a 64bit
1303  * register).
1304  */
1305 static const struct sys_reg_desc cp15_regs[] = {
1306         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1307
1308         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1309         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1310         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1311         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1312         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1313         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1314         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1315         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1316         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1317         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1318         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1319
1320         /*
1321          * DC{C,I,CI}SW operations:
1322          */
1323         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1324         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1325         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1326
1327         /* PMU */
1328         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1329         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1330         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1331         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1332         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1333         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1334         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1335         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1336         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1337         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1338         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1339         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1340         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1341         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1342         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1343
1344         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1345         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1346         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1347         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1348
1349         /* ICC_SRE */
1350         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1351
1352         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1353
1354         /* PMEVCNTRn */
1355         PMU_PMEVCNTR(0),
1356         PMU_PMEVCNTR(1),
1357         PMU_PMEVCNTR(2),
1358         PMU_PMEVCNTR(3),
1359         PMU_PMEVCNTR(4),
1360         PMU_PMEVCNTR(5),
1361         PMU_PMEVCNTR(6),
1362         PMU_PMEVCNTR(7),
1363         PMU_PMEVCNTR(8),
1364         PMU_PMEVCNTR(9),
1365         PMU_PMEVCNTR(10),
1366         PMU_PMEVCNTR(11),
1367         PMU_PMEVCNTR(12),
1368         PMU_PMEVCNTR(13),
1369         PMU_PMEVCNTR(14),
1370         PMU_PMEVCNTR(15),
1371         PMU_PMEVCNTR(16),
1372         PMU_PMEVCNTR(17),
1373         PMU_PMEVCNTR(18),
1374         PMU_PMEVCNTR(19),
1375         PMU_PMEVCNTR(20),
1376         PMU_PMEVCNTR(21),
1377         PMU_PMEVCNTR(22),
1378         PMU_PMEVCNTR(23),
1379         PMU_PMEVCNTR(24),
1380         PMU_PMEVCNTR(25),
1381         PMU_PMEVCNTR(26),
1382         PMU_PMEVCNTR(27),
1383         PMU_PMEVCNTR(28),
1384         PMU_PMEVCNTR(29),
1385         PMU_PMEVCNTR(30),
1386         /* PMEVTYPERn */
1387         PMU_PMEVTYPER(0),
1388         PMU_PMEVTYPER(1),
1389         PMU_PMEVTYPER(2),
1390         PMU_PMEVTYPER(3),
1391         PMU_PMEVTYPER(4),
1392         PMU_PMEVTYPER(5),
1393         PMU_PMEVTYPER(6),
1394         PMU_PMEVTYPER(7),
1395         PMU_PMEVTYPER(8),
1396         PMU_PMEVTYPER(9),
1397         PMU_PMEVTYPER(10),
1398         PMU_PMEVTYPER(11),
1399         PMU_PMEVTYPER(12),
1400         PMU_PMEVTYPER(13),
1401         PMU_PMEVTYPER(14),
1402         PMU_PMEVTYPER(15),
1403         PMU_PMEVTYPER(16),
1404         PMU_PMEVTYPER(17),
1405         PMU_PMEVTYPER(18),
1406         PMU_PMEVTYPER(19),
1407         PMU_PMEVTYPER(20),
1408         PMU_PMEVTYPER(21),
1409         PMU_PMEVTYPER(22),
1410         PMU_PMEVTYPER(23),
1411         PMU_PMEVTYPER(24),
1412         PMU_PMEVTYPER(25),
1413         PMU_PMEVTYPER(26),
1414         PMU_PMEVTYPER(27),
1415         PMU_PMEVTYPER(28),
1416         PMU_PMEVTYPER(29),
1417         PMU_PMEVTYPER(30),
1418         /* PMCCFILTR */
1419         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1420 };
1421
1422 static const struct sys_reg_desc cp15_64_regs[] = {
1423         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1424         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1425         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1426         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1427 };
1428
1429 /* Target specific emulation tables */
1430 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1431
1432 void kvm_register_target_sys_reg_table(unsigned int target,
1433                                        struct kvm_sys_reg_target_table *table)
1434 {
1435         target_tables[target] = table;
1436 }
1437
1438 /* Get specific register table for this target. */
1439 static const struct sys_reg_desc *get_target_table(unsigned target,
1440                                                    bool mode_is_64,
1441                                                    size_t *num)
1442 {
1443         struct kvm_sys_reg_target_table *table;
1444
1445         table = target_tables[target];
1446         if (mode_is_64) {
1447                 *num = table->table64.num;
1448                 return table->table64.table;
1449         } else {
1450                 *num = table->table32.num;
1451                 return table->table32.table;
1452         }
1453 }
1454
1455 #define reg_to_match_value(x)                                           \
1456         ({                                                              \
1457                 unsigned long val;                                      \
1458                 val  = (x)->Op0 << 14;                                  \
1459                 val |= (x)->Op1 << 11;                                  \
1460                 val |= (x)->CRn << 7;                                   \
1461                 val |= (x)->CRm << 3;                                   \
1462                 val |= (x)->Op2;                                        \
1463                 val;                                                    \
1464          })
1465
1466 static int match_sys_reg(const void *key, const void *elt)
1467 {
1468         const unsigned long pval = (unsigned long)key;
1469         const struct sys_reg_desc *r = elt;
1470
1471         return pval - reg_to_match_value(r);
1472 }
1473
1474 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1475                                          const struct sys_reg_desc table[],
1476                                          unsigned int num)
1477 {
1478         unsigned long pval = reg_to_match_value(params);
1479
1480         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1481 }
1482
1483 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1484 {
1485         kvm_inject_undefined(vcpu);
1486         return 1;
1487 }
1488
1489 /*
1490  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1491  *                call the corresponding trap handler.
1492  *
1493  * @params: pointer to the descriptor of the access
1494  * @table: array of trap descriptors
1495  * @num: size of the trap descriptor array
1496  *
1497  * Return 0 if the access has been handled, and -1 if not.
1498  */
1499 static int emulate_cp(struct kvm_vcpu *vcpu,
1500                       struct sys_reg_params *params,
1501                       const struct sys_reg_desc *table,
1502                       size_t num)
1503 {
1504         const struct sys_reg_desc *r;
1505
1506         if (!table)
1507                 return -1;      /* Not handled */
1508
1509         r = find_reg(params, table, num);
1510
1511         if (r) {
1512                 /*
1513                  * Not having an accessor means that we have
1514                  * configured a trap that we don't know how to
1515                  * handle. This certainly qualifies as a gross bug
1516                  * that should be fixed right away.
1517                  */
1518                 BUG_ON(!r->access);
1519
1520                 if (likely(r->access(vcpu, params, r))) {
1521                         /* Skip instruction, since it was emulated */
1522                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1523                         /* Handled */
1524                         return 0;
1525                 }
1526         }
1527
1528         /* Not handled */
1529         return -1;
1530 }
1531
1532 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1533                                 struct sys_reg_params *params)
1534 {
1535         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1536         int cp = -1;
1537
1538         switch(hsr_ec) {
1539         case ESR_ELx_EC_CP15_32:
1540         case ESR_ELx_EC_CP15_64:
1541                 cp = 15;
1542                 break;
1543         case ESR_ELx_EC_CP14_MR:
1544         case ESR_ELx_EC_CP14_64:
1545                 cp = 14;
1546                 break;
1547         default:
1548                 WARN_ON(1);
1549         }
1550
1551         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1552                 cp, *vcpu_pc(vcpu));
1553         print_sys_reg_instr(params);
1554         kvm_inject_undefined(vcpu);
1555 }
1556
1557 /**
1558  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1559  * @vcpu: The VCPU pointer
1560  * @run:  The kvm_run struct
1561  */
1562 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1563                             const struct sys_reg_desc *global,
1564                             size_t nr_global,
1565                             const struct sys_reg_desc *target_specific,
1566                             size_t nr_specific)
1567 {
1568         struct sys_reg_params params;
1569         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1570         int Rt = (hsr >> 5) & 0xf;
1571         int Rt2 = (hsr >> 10) & 0xf;
1572
1573         params.is_aarch32 = true;
1574         params.is_32bit = false;
1575         params.CRm = (hsr >> 1) & 0xf;
1576         params.is_write = ((hsr & 1) == 0);
1577
1578         params.Op0 = 0;
1579         params.Op1 = (hsr >> 16) & 0xf;
1580         params.Op2 = 0;
1581         params.CRn = 0;
1582
1583         /*
1584          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1585          * backends between AArch32 and AArch64, we get away with it.
1586          */
1587         if (params.is_write) {
1588                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1589                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1590         }
1591
1592         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1593                 goto out;
1594         if (!emulate_cp(vcpu, &params, global, nr_global))
1595                 goto out;
1596
1597         unhandled_cp_access(vcpu, &params);
1598
1599 out:
1600         /* Split up the value between registers for the read side */
1601         if (!params.is_write) {
1602                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1603                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1604         }
1605
1606         return 1;
1607 }
1608
1609 /**
1610  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1611  * @vcpu: The VCPU pointer
1612  * @run:  The kvm_run struct
1613  */
1614 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1615                             const struct sys_reg_desc *global,
1616                             size_t nr_global,
1617                             const struct sys_reg_desc *target_specific,
1618                             size_t nr_specific)
1619 {
1620         struct sys_reg_params params;
1621         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1622         int Rt  = (hsr >> 5) & 0xf;
1623
1624         params.is_aarch32 = true;
1625         params.is_32bit = true;
1626         params.CRm = (hsr >> 1) & 0xf;
1627         params.regval = vcpu_get_reg(vcpu, Rt);
1628         params.is_write = ((hsr & 1) == 0);
1629         params.CRn = (hsr >> 10) & 0xf;
1630         params.Op0 = 0;
1631         params.Op1 = (hsr >> 14) & 0x7;
1632         params.Op2 = (hsr >> 17) & 0x7;
1633
1634         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1635             !emulate_cp(vcpu, &params, global, nr_global)) {
1636                 if (!params.is_write)
1637                         vcpu_set_reg(vcpu, Rt, params.regval);
1638                 return 1;
1639         }
1640
1641         unhandled_cp_access(vcpu, &params);
1642         return 1;
1643 }
1644
1645 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1646 {
1647         const struct sys_reg_desc *target_specific;
1648         size_t num;
1649
1650         target_specific = get_target_table(vcpu->arch.target, false, &num);
1651         return kvm_handle_cp_64(vcpu,
1652                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1653                                 target_specific, num);
1654 }
1655
1656 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1657 {
1658         const struct sys_reg_desc *target_specific;
1659         size_t num;
1660
1661         target_specific = get_target_table(vcpu->arch.target, false, &num);
1662         return kvm_handle_cp_32(vcpu,
1663                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1664                                 target_specific, num);
1665 }
1666
1667 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1668 {
1669         return kvm_handle_cp_64(vcpu,
1670                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1671                                 NULL, 0);
1672 }
1673
1674 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1675 {
1676         return kvm_handle_cp_32(vcpu,
1677                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1678                                 NULL, 0);
1679 }
1680
1681 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1682                            struct sys_reg_params *params)
1683 {
1684         size_t num;
1685         const struct sys_reg_desc *table, *r;
1686
1687         table = get_target_table(vcpu->arch.target, true, &num);
1688
1689         /* Search target-specific then generic table. */
1690         r = find_reg(params, table, num);
1691         if (!r)
1692                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1693
1694         if (likely(r)) {
1695                 /*
1696                  * Not having an accessor means that we have
1697                  * configured a trap that we don't know how to
1698                  * handle. This certainly qualifies as a gross bug
1699                  * that should be fixed right away.
1700                  */
1701                 BUG_ON(!r->access);
1702
1703                 if (likely(r->access(vcpu, params, r))) {
1704                         /* Skip instruction, since it was emulated */
1705                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1706                         return 1;
1707                 }
1708                 /* If access function fails, it should complain. */
1709         } else {
1710                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1711                         *vcpu_pc(vcpu));
1712                 print_sys_reg_instr(params);
1713         }
1714         kvm_inject_undefined(vcpu);
1715         return 1;
1716 }
1717
1718 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1719                               const struct sys_reg_desc *table, size_t num)
1720 {
1721         unsigned long i;
1722
1723         for (i = 0; i < num; i++)
1724                 if (table[i].reset)
1725                         table[i].reset(vcpu, &table[i]);
1726 }
1727
1728 /**
1729  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1730  * @vcpu: The VCPU pointer
1731  * @run:  The kvm_run struct
1732  */
1733 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1734 {
1735         struct sys_reg_params params;
1736         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1737         int Rt = (esr >> 5) & 0x1f;
1738         int ret;
1739
1740         trace_kvm_handle_sys_reg(esr);
1741
1742         params.is_aarch32 = false;
1743         params.is_32bit = false;
1744         params.Op0 = (esr >> 20) & 3;
1745         params.Op1 = (esr >> 14) & 0x7;
1746         params.CRn = (esr >> 10) & 0xf;
1747         params.CRm = (esr >> 1) & 0xf;
1748         params.Op2 = (esr >> 17) & 0x7;
1749         params.regval = vcpu_get_reg(vcpu, Rt);
1750         params.is_write = !(esr & 1);
1751
1752         ret = emulate_sys_reg(vcpu, &params);
1753
1754         if (!params.is_write)
1755                 vcpu_set_reg(vcpu, Rt, params.regval);
1756         return ret;
1757 }
1758
1759 /******************************************************************************
1760  * Userspace API
1761  *****************************************************************************/
1762
1763 static bool index_to_params(u64 id, struct sys_reg_params *params)
1764 {
1765         switch (id & KVM_REG_SIZE_MASK) {
1766         case KVM_REG_SIZE_U64:
1767                 /* Any unused index bits means it's not valid. */
1768                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1769                               | KVM_REG_ARM_COPROC_MASK
1770                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1771                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1772                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1773                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1774                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1775                         return false;
1776                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1777                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1778                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1779                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1780                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1781                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1782                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1783                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1784                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1785                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1786                 return true;
1787         default:
1788                 return false;
1789         }
1790 }
1791
1792 /* Decode an index value, and find the sys_reg_desc entry. */
1793 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1794                                                     u64 id)
1795 {
1796         size_t num;
1797         const struct sys_reg_desc *table, *r;
1798         struct sys_reg_params params;
1799
1800         /* We only do sys_reg for now. */
1801         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1802                 return NULL;
1803
1804         if (!index_to_params(id, &params))
1805                 return NULL;
1806
1807         table = get_target_table(vcpu->arch.target, true, &num);
1808         r = find_reg(&params, table, num);
1809         if (!r)
1810                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1811
1812         /* Not saved in the sys_reg array? */
1813         if (r && !r->reg)
1814                 r = NULL;
1815
1816         return r;
1817 }
1818
1819 /*
1820  * These are the invariant sys_reg registers: we let the guest see the
1821  * host versions of these, so they're part of the guest state.
1822  *
1823  * A future CPU may provide a mechanism to present different values to
1824  * the guest, or a future kvm may trap them.
1825  */
1826
1827 #define FUNCTION_INVARIANT(reg)                                         \
1828         static void get_##reg(struct kvm_vcpu *v,                       \
1829                               const struct sys_reg_desc *r)             \
1830         {                                                               \
1831                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
1832         }
1833
1834 FUNCTION_INVARIANT(midr_el1)
1835 FUNCTION_INVARIANT(ctr_el0)
1836 FUNCTION_INVARIANT(revidr_el1)
1837 FUNCTION_INVARIANT(id_pfr0_el1)
1838 FUNCTION_INVARIANT(id_pfr1_el1)
1839 FUNCTION_INVARIANT(id_dfr0_el1)
1840 FUNCTION_INVARIANT(id_afr0_el1)
1841 FUNCTION_INVARIANT(id_mmfr0_el1)
1842 FUNCTION_INVARIANT(id_mmfr1_el1)
1843 FUNCTION_INVARIANT(id_mmfr2_el1)
1844 FUNCTION_INVARIANT(id_mmfr3_el1)
1845 FUNCTION_INVARIANT(id_isar0_el1)
1846 FUNCTION_INVARIANT(id_isar1_el1)
1847 FUNCTION_INVARIANT(id_isar2_el1)
1848 FUNCTION_INVARIANT(id_isar3_el1)
1849 FUNCTION_INVARIANT(id_isar4_el1)
1850 FUNCTION_INVARIANT(id_isar5_el1)
1851 FUNCTION_INVARIANT(clidr_el1)
1852 FUNCTION_INVARIANT(aidr_el1)
1853
1854 /* ->val is filled in by kvm_sys_reg_table_init() */
1855 static struct sys_reg_desc invariant_sys_regs[] = {
1856         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1857           NULL, get_midr_el1 },
1858         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1859           NULL, get_revidr_el1 },
1860         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1861           NULL, get_id_pfr0_el1 },
1862         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1863           NULL, get_id_pfr1_el1 },
1864         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1865           NULL, get_id_dfr0_el1 },
1866         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1867           NULL, get_id_afr0_el1 },
1868         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1869           NULL, get_id_mmfr0_el1 },
1870         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1871           NULL, get_id_mmfr1_el1 },
1872         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1873           NULL, get_id_mmfr2_el1 },
1874         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1875           NULL, get_id_mmfr3_el1 },
1876         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1877           NULL, get_id_isar0_el1 },
1878         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1879           NULL, get_id_isar1_el1 },
1880         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1881           NULL, get_id_isar2_el1 },
1882         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1883           NULL, get_id_isar3_el1 },
1884         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1885           NULL, get_id_isar4_el1 },
1886         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1887           NULL, get_id_isar5_el1 },
1888         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1889           NULL, get_clidr_el1 },
1890         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1891           NULL, get_aidr_el1 },
1892         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1893           NULL, get_ctr_el0 },
1894 };
1895
1896 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1897 {
1898         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1899                 return -EFAULT;
1900         return 0;
1901 }
1902
1903 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1904 {
1905         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1906                 return -EFAULT;
1907         return 0;
1908 }
1909
1910 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1911 {
1912         struct sys_reg_params params;
1913         const struct sys_reg_desc *r;
1914
1915         if (!index_to_params(id, &params))
1916                 return -ENOENT;
1917
1918         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1919         if (!r)
1920                 return -ENOENT;
1921
1922         return reg_to_user(uaddr, &r->val, id);
1923 }
1924
1925 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1926 {
1927         struct sys_reg_params params;
1928         const struct sys_reg_desc *r;
1929         int err;
1930         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1931
1932         if (!index_to_params(id, &params))
1933                 return -ENOENT;
1934         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1935         if (!r)
1936                 return -ENOENT;
1937
1938         err = reg_from_user(&val, uaddr, id);
1939         if (err)
1940                 return err;
1941
1942         /* This is what we mean by invariant: you can't change it. */
1943         if (r->val != val)
1944                 return -EINVAL;
1945
1946         return 0;
1947 }
1948
1949 static bool is_valid_cache(u32 val)
1950 {
1951         u32 level, ctype;
1952
1953         if (val >= CSSELR_MAX)
1954                 return false;
1955
1956         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1957         level = (val >> 1);
1958         ctype = (cache_levels >> (level * 3)) & 7;
1959
1960         switch (ctype) {
1961         case 0: /* No cache */
1962                 return false;
1963         case 1: /* Instruction cache only */
1964                 return (val & 1);
1965         case 2: /* Data cache only */
1966         case 4: /* Unified cache */
1967                 return !(val & 1);
1968         case 3: /* Separate instruction and data caches */
1969                 return true;
1970         default: /* Reserved: we can't know instruction or data. */
1971                 return false;
1972         }
1973 }
1974
1975 static int demux_c15_get(u64 id, void __user *uaddr)
1976 {
1977         u32 val;
1978         u32 __user *uval = uaddr;
1979
1980         /* Fail if we have unknown bits set. */
1981         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1982                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1983                 return -ENOENT;
1984
1985         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1986         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1987                 if (KVM_REG_SIZE(id) != 4)
1988                         return -ENOENT;
1989                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1990                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1991                 if (!is_valid_cache(val))
1992                         return -ENOENT;
1993
1994                 return put_user(get_ccsidr(val), uval);
1995         default:
1996                 return -ENOENT;
1997         }
1998 }
1999
2000 static int demux_c15_set(u64 id, void __user *uaddr)
2001 {
2002         u32 val, newval;
2003         u32 __user *uval = uaddr;
2004
2005         /* Fail if we have unknown bits set. */
2006         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2007                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2008                 return -ENOENT;
2009
2010         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2011         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2012                 if (KVM_REG_SIZE(id) != 4)
2013                         return -ENOENT;
2014                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2015                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2016                 if (!is_valid_cache(val))
2017                         return -ENOENT;
2018
2019                 if (get_user(newval, uval))
2020                         return -EFAULT;
2021
2022                 /* This is also invariant: you can't change it. */
2023                 if (newval != get_ccsidr(val))
2024                         return -EINVAL;
2025                 return 0;
2026         default:
2027                 return -ENOENT;
2028         }
2029 }
2030
2031 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2032 {
2033         const struct sys_reg_desc *r;
2034         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2035
2036         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2037                 return demux_c15_get(reg->id, uaddr);
2038
2039         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2040                 return -ENOENT;
2041
2042         r = index_to_sys_reg_desc(vcpu, reg->id);
2043         if (!r)
2044                 return get_invariant_sys_reg(reg->id, uaddr);
2045
2046         if (r->get_user)
2047                 return (r->get_user)(vcpu, r, reg, uaddr);
2048
2049         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2050 }
2051
2052 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2053 {
2054         const struct sys_reg_desc *r;
2055         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2056
2057         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2058                 return demux_c15_set(reg->id, uaddr);
2059
2060         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2061                 return -ENOENT;
2062
2063         r = index_to_sys_reg_desc(vcpu, reg->id);
2064         if (!r)
2065                 return set_invariant_sys_reg(reg->id, uaddr);
2066
2067         if (r->set_user)
2068                 return (r->set_user)(vcpu, r, reg, uaddr);
2069
2070         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2071 }
2072
2073 static unsigned int num_demux_regs(void)
2074 {
2075         unsigned int i, count = 0;
2076
2077         for (i = 0; i < CSSELR_MAX; i++)
2078                 if (is_valid_cache(i))
2079                         count++;
2080
2081         return count;
2082 }
2083
2084 static int write_demux_regids(u64 __user *uindices)
2085 {
2086         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2087         unsigned int i;
2088
2089         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2090         for (i = 0; i < CSSELR_MAX; i++) {
2091                 if (!is_valid_cache(i))
2092                         continue;
2093                 if (put_user(val | i, uindices))
2094                         return -EFAULT;
2095                 uindices++;
2096         }
2097         return 0;
2098 }
2099
2100 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2101 {
2102         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2103                 KVM_REG_ARM64_SYSREG |
2104                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2105                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2106                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2107                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2108                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2109 }
2110
2111 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2112 {
2113         if (!*uind)
2114                 return true;
2115
2116         if (put_user(sys_reg_to_index(reg), *uind))
2117                 return false;
2118
2119         (*uind)++;
2120         return true;
2121 }
2122
2123 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2124 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2125 {
2126         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2127         unsigned int total = 0;
2128         size_t num;
2129
2130         /* We check for duplicates here, to allow arch-specific overrides. */
2131         i1 = get_target_table(vcpu->arch.target, true, &num);
2132         end1 = i1 + num;
2133         i2 = sys_reg_descs;
2134         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2135
2136         BUG_ON(i1 == end1 || i2 == end2);
2137
2138         /* Walk carefully, as both tables may refer to the same register. */
2139         while (i1 || i2) {
2140                 int cmp = cmp_sys_reg(i1, i2);
2141                 /* target-specific overrides generic entry. */
2142                 if (cmp <= 0) {
2143                         /* Ignore registers we trap but don't save. */
2144                         if (i1->reg) {
2145                                 if (!copy_reg_to_user(i1, &uind))
2146                                         return -EFAULT;
2147                                 total++;
2148                         }
2149                 } else {
2150                         /* Ignore registers we trap but don't save. */
2151                         if (i2->reg) {
2152                                 if (!copy_reg_to_user(i2, &uind))
2153                                         return -EFAULT;
2154                                 total++;
2155                         }
2156                 }
2157
2158                 if (cmp <= 0 && ++i1 == end1)
2159                         i1 = NULL;
2160                 if (cmp >= 0 && ++i2 == end2)
2161                         i2 = NULL;
2162         }
2163         return total;
2164 }
2165
2166 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2167 {
2168         return ARRAY_SIZE(invariant_sys_regs)
2169                 + num_demux_regs()
2170                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2171 }
2172
2173 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2174 {
2175         unsigned int i;
2176         int err;
2177
2178         /* Then give them all the invariant registers' indices. */
2179         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2180                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2181                         return -EFAULT;
2182                 uindices++;
2183         }
2184
2185         err = walk_sys_regs(vcpu, uindices);
2186         if (err < 0)
2187                 return err;
2188         uindices += err;
2189
2190         return write_demux_regids(uindices);
2191 }
2192
2193 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2194 {
2195         unsigned int i;
2196
2197         for (i = 1; i < n; i++) {
2198                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2199                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2200                         return 1;
2201                 }
2202         }
2203
2204         return 0;
2205 }
2206
2207 void kvm_sys_reg_table_init(void)
2208 {
2209         unsigned int i;
2210         struct sys_reg_desc clidr;
2211
2212         /* Make sure tables are unique and in order. */
2213         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2214         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2215         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2216         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2217         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2218         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2219
2220         /* We abuse the reset function to overwrite the table itself. */
2221         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2222                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2223
2224         /*
2225          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2226          *
2227          *   If software reads the Cache Type fields from Ctype1
2228          *   upwards, once it has seen a value of 0b000, no caches
2229          *   exist at further-out levels of the hierarchy. So, for
2230          *   example, if Ctype3 is the first Cache Type field with a
2231          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2232          *   ignored.
2233          */
2234         get_clidr_el1(NULL, &clidr); /* Ugly... */
2235         cache_levels = clidr.val;
2236         for (i = 0; i < 7; i++)
2237                 if (((cache_levels >> (i*3)) & 7) == 0)
2238                         break;
2239         /* Clear all higher bits. */
2240         cache_levels &= (1 << (i*3))-1;
2241 }
2242
2243 /**
2244  * kvm_reset_sys_regs - sets system registers to reset value
2245  * @vcpu: The VCPU pointer
2246  *
2247  * This function finds the right table above and sets the registers on the
2248  * virtual CPU struct to their architecturally defined reset values.
2249  */
2250 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2251 {
2252         size_t num;
2253         const struct sys_reg_desc *table;
2254
2255         /* Catch someone adding a register without putting in reset entry. */
2256         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2257
2258         /* Generic chip reset first (so target could override). */
2259         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2260
2261         table = get_target_table(vcpu->arch.target, true, &num);
2262         reset_sys_reg_descs(vcpu, table, num);
2263
2264         for (num = 1; num < NR_SYS_REGS; num++)
2265                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2266                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2267 }