2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_pci.h>
34 #include <linux/export.h>
36 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
41 static DEFINE_SPINLOCK(hose_spinlock);
44 /* XXX kill that some day ... */
45 static int global_phb_number; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base;
50 unsigned long isa_io_base;
51 EXPORT_SYMBOL(isa_io_base);
53 static int pci_bus_count;
55 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
57 struct pci_controller *phb;
59 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
62 spin_lock(&hose_spinlock);
63 phb->global_number = global_phb_number++;
64 list_add_tail(&phb->list_node, &hose_list);
65 spin_unlock(&hose_spinlock);
67 phb->is_dynamic = mem_init_done;
71 void pcibios_free_controller(struct pci_controller *phb)
73 spin_lock(&hose_spinlock);
74 list_del(&phb->list_node);
75 spin_unlock(&hose_spinlock);
81 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
83 return resource_size(&hose->io_resource);
86 int pcibios_vaddr_is_ioport(void __iomem *address)
89 struct pci_controller *hose;
92 spin_lock(&hose_spinlock);
93 list_for_each_entry(hose, &hose_list, list_node) {
94 size = pcibios_io_size(hose);
95 if (address >= hose->io_base_virt &&
96 address < (hose->io_base_virt + size)) {
101 spin_unlock(&hose_spinlock);
105 unsigned long pci_address_to_pio(phys_addr_t address)
107 struct pci_controller *hose;
108 resource_size_t size;
109 unsigned long ret = ~0;
111 spin_lock(&hose_spinlock);
112 list_for_each_entry(hose, &hose_list, list_node) {
113 size = pcibios_io_size(hose);
114 if (address >= hose->io_base_phys &&
115 address < (hose->io_base_phys + size)) {
117 (unsigned long)hose->io_base_virt - _IO_BASE;
118 ret = base + (address - hose->io_base_phys);
122 spin_unlock(&hose_spinlock);
126 EXPORT_SYMBOL_GPL(pci_address_to_pio);
128 /* This routine is meant to be used early during boot, when the
129 * PCI bus numbers have not yet been assigned, and you need to
130 * issue PCI config cycles to an OF device.
131 * It could also be used to "fix" RTAS config cycles if you want
132 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
135 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
138 struct pci_controller *hose, *tmp;
139 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
140 if (hose->dn == node)
147 void pcibios_set_master(struct pci_dev *dev)
149 /* No special bus mastering setup handling */
153 * Platform support for /proc/bus/pci/X/Y mmap()s,
154 * modelled on the sparc64 implementation by Dave Miller.
159 * Adjust vm_pgoff of VMA such that it is the physical page offset
160 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
162 * Basically, the user finds the base address for his device which he wishes
163 * to mmap. They read the 32-bit value from the config space base register,
164 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
165 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
167 * Returns negative error code on failure, zero on success.
169 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
170 resource_size_t *offset,
171 enum pci_mmap_state mmap_state)
173 struct pci_controller *hose = pci_bus_to_host(dev->bus);
174 unsigned long io_offset = 0;
178 return NULL; /* should never happen */
180 /* If memory, add on the PCI bridge address offset */
181 if (mmap_state == pci_mmap_mem) {
182 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
183 *offset += hose->pci_mem_offset;
185 res_bit = IORESOURCE_MEM;
187 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
188 *offset += io_offset;
189 res_bit = IORESOURCE_IO;
193 * Check that the offset requested corresponds to one of the
194 * resources of the device.
196 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
197 struct resource *rp = &dev->resource[i];
198 int flags = rp->flags;
200 /* treat ROM as memory (should be already) */
201 if (i == PCI_ROM_RESOURCE)
202 flags |= IORESOURCE_MEM;
204 /* Active and same type? */
205 if ((flags & res_bit) == 0)
208 /* In the range of this resource? */
209 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
212 /* found it! construct the final physical address */
213 if (mmap_state == pci_mmap_io)
214 *offset += hose->io_base_phys - io_offset;
222 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
225 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
227 enum pci_mmap_state mmap_state,
230 pgprot_t prot = protection;
232 /* Write combine is always 0 on non-memory space mappings. On
233 * memory space, if the user didn't pass 1, we check for a
234 * "prefetchable" resource. This is a bit hackish, but we use
235 * this to workaround the inability of /sysfs to provide a write
238 if (mmap_state != pci_mmap_mem)
240 else if (write_combine == 0) {
241 if (rp->flags & IORESOURCE_PREFETCH)
245 return pgprot_noncached(prot);
249 * This one is used by /dev/mem and fbdev who have no clue about the
250 * PCI device, it tries to find the PCI device first and calls the
253 pgprot_t pci_phys_mem_access_prot(struct file *file,
258 struct pci_dev *pdev = NULL;
259 struct resource *found = NULL;
260 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
263 if (page_is_ram(pfn))
266 prot = pgprot_noncached(prot);
267 for_each_pci_dev(pdev) {
268 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
269 struct resource *rp = &pdev->resource[i];
270 int flags = rp->flags;
272 /* Active and same type? */
273 if ((flags & IORESOURCE_MEM) == 0)
275 /* In the range of this resource? */
276 if (offset < (rp->start & PAGE_MASK) ||
286 if (found->flags & IORESOURCE_PREFETCH)
287 prot = pgprot_noncached_wc(prot);
291 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
292 (unsigned long long)offset, pgprot_val(prot));
298 * Perform the actual remap of the pages for a PCI device mapping, as
299 * appropriate for this architecture. The region in the process to map
300 * is described by vm_start and vm_end members of VMA, the base physical
301 * address is found in vm_pgoff.
302 * The pci device structure is provided so that architectures may make mapping
303 * decisions on a per-device or per-bus basis.
305 * Returns a negative error code on failure, zero on success.
307 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
308 enum pci_mmap_state mmap_state, int write_combine)
310 resource_size_t offset =
311 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
315 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
319 vma->vm_pgoff = offset >> PAGE_SHIFT;
320 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
322 mmap_state, write_combine);
324 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
325 vma->vm_end - vma->vm_start, vma->vm_page_prot);
330 /* This provides legacy IO read access on a bus */
331 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
333 unsigned long offset;
334 struct pci_controller *hose = pci_bus_to_host(bus);
335 struct resource *rp = &hose->io_resource;
338 /* Check if port can be supported by that bus. We only check
339 * the ranges of the PHB though, not the bus itself as the rules
340 * for forwarding legacy cycles down bridges are not our problem
341 * here. So if the host bridge supports it, we do it.
343 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
346 if (!(rp->flags & IORESOURCE_IO))
348 if (offset < rp->start || (offset + size) > rp->end)
350 addr = hose->io_base_virt + port;
354 *((u8 *)val) = in_8(addr);
359 *((u16 *)val) = in_le16(addr);
364 *((u32 *)val) = in_le32(addr);
370 /* This provides legacy IO write access on a bus */
371 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
373 unsigned long offset;
374 struct pci_controller *hose = pci_bus_to_host(bus);
375 struct resource *rp = &hose->io_resource;
378 /* Check if port can be supported by that bus. We only check
379 * the ranges of the PHB though, not the bus itself as the rules
380 * for forwarding legacy cycles down bridges are not our problem
381 * here. So if the host bridge supports it, we do it.
383 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
386 if (!(rp->flags & IORESOURCE_IO))
388 if (offset < rp->start || (offset + size) > rp->end)
390 addr = hose->io_base_virt + port;
392 /* WARNING: The generic code is idiotic. It gets passed a pointer
393 * to what can be a 1, 2 or 4 byte quantity and always reads that
394 * as a u32, which means that we have to correct the location of
395 * the data read within those 32 bits for size 1 and 2
399 out_8(addr, val >> 24);
404 out_le16(addr, val >> 16);
415 /* This provides legacy IO or memory mmap access on a bus */
416 int pci_mmap_legacy_page_range(struct pci_bus *bus,
417 struct vm_area_struct *vma,
418 enum pci_mmap_state mmap_state)
420 struct pci_controller *hose = pci_bus_to_host(bus);
421 resource_size_t offset =
422 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
423 resource_size_t size = vma->vm_end - vma->vm_start;
426 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
427 pci_domain_nr(bus), bus->number,
428 mmap_state == pci_mmap_mem ? "MEM" : "IO",
429 (unsigned long long)offset,
430 (unsigned long long)(offset + size - 1));
432 if (mmap_state == pci_mmap_mem) {
435 * Because X is lame and can fail starting if it gets an error
436 * trying to mmap legacy_mem (instead of just moving on without
437 * legacy memory access) we fake it here by giving it anonymous
438 * memory, effectively behaving just like /dev/zero
440 if ((offset + size) > hose->isa_mem_size) {
442 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
443 current->comm, current->pid);
444 pr_debug("legacy memory for 0%04x:%02x\n",
445 pci_domain_nr(bus), bus->number);
447 if (vma->vm_flags & VM_SHARED)
448 return shmem_zero_setup(vma);
451 offset += hose->isa_mem_phys;
453 unsigned long io_offset = (unsigned long)hose->io_base_virt -
455 unsigned long roffset = offset + io_offset;
456 rp = &hose->io_resource;
457 if (!(rp->flags & IORESOURCE_IO))
459 if (roffset < rp->start || (roffset + size) > rp->end)
461 offset += hose->io_base_phys;
463 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
465 vma->vm_pgoff = offset >> PAGE_SHIFT;
466 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
467 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
468 vma->vm_end - vma->vm_start,
472 void pci_resource_to_user(const struct pci_dev *dev, int bar,
473 const struct resource *rsrc,
474 resource_size_t *start, resource_size_t *end)
476 struct pci_controller *hose = pci_bus_to_host(dev->bus);
477 resource_size_t offset = 0;
482 if (rsrc->flags & IORESOURCE_IO)
483 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
485 /* We pass a fully fixed up address to userland for MMIO instead of
486 * a BAR value because X is lame and expects to be able to use that
487 * to pass to /dev/mem !
489 * That means that we'll have potentially 64 bits values where some
490 * userland apps only expect 32 (like X itself since it thinks only
491 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
494 * Hopefully, the sysfs insterface is immune to that gunk. Once X
495 * has been fixed (and the fix spread enough), we can re-enable the
496 * 2 lines below and pass down a BAR value to userland. In that case
497 * we'll also have to re-enable the matching code in
498 * __pci_mmap_make_offset().
503 else if (rsrc->flags & IORESOURCE_MEM)
504 offset = hose->pci_mem_offset;
507 *start = rsrc->start - offset;
508 *end = rsrc->end - offset;
512 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
513 * @hose: newly allocated pci_controller to be setup
514 * @dev: device node of the host bridge
515 * @primary: set if primary bus (32 bits only, soon to be deprecated)
517 * This function will parse the "ranges" property of a PCI host bridge device
518 * node and setup the resource mapping of a pci controller based on its
521 * Life would be boring if it wasn't for a few issues that we have to deal
524 * - We can only cope with one IO space range and up to 3 Memory space
525 * ranges. However, some machines (thanks Apple !) tend to split their
526 * space into lots of small contiguous ranges. So we have to coalesce.
528 * - We can only cope with all memory ranges having the same offset
529 * between CPU addresses and PCI addresses. Unfortunately, some bridges
530 * are setup for a large 1:1 mapping along with a small "window" which
531 * maps PCI address 0 to some arbitrary high address of the CPU space in
532 * order to give access to the ISA memory hole.
533 * The way out of here that I've chosen for now is to always set the
534 * offset based on the first resource found, then override it if we
535 * have a different offset and the previous was set by an ISA hole.
537 * - Some busses have IO space not starting at 0, which causes trouble with
538 * the way we do our IO resource renumbering. The code somewhat deals with
539 * it for 64 bits but I would expect problems on 32 bits.
541 * - Some 32 bits platforms such as 4xx can have physical space larger than
542 * 32 bits so we need to use 64 bits values for the parsing
544 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
545 struct device_node *dev, int primary)
547 int memno = 0, isa_hole = -1;
548 unsigned long long isa_mb = 0;
549 struct resource *res;
550 struct of_pci_range range;
551 struct of_pci_range_parser parser;
553 pr_info("PCI host bridge %s %s ranges:\n",
554 dev->full_name, primary ? "(primary)" : "");
556 /* Check for ranges property */
557 if (of_pci_range_parser_init(&parser, dev))
560 pr_debug("Parsing ranges property...\n");
561 for_each_of_pci_range(&parser, &range) {
562 /* Read next ranges element */
563 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
564 range.pci_space, range.pci_addr);
565 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
566 range.cpu_addr, range.size);
568 /* If we failed translation or got a zero-sized region
569 * (some FW try to feed us with non sensical zero sized regions
570 * such as power3 which look like some kind of attempt
571 * at exposing the VGA memory hole)
573 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
576 /* Act based on address space type */
578 switch (range.flags & IORESOURCE_TYPE_BITS) {
580 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
581 range.cpu_addr, range.cpu_addr + range.size - 1,
584 /* We support only one IO range */
585 if (hose->pci_io_size) {
586 pr_info(" \\--> Skipped (too many) !\n");
589 /* On 32 bits, limit I/O space to 16MB */
590 if (range.size > 0x01000000)
591 range.size = 0x01000000;
593 /* 32 bits needs to map IOs here */
594 hose->io_base_virt = ioremap(range.cpu_addr,
597 /* Expect trouble if pci_addr is not 0 */
600 (unsigned long)hose->io_base_virt;
601 /* pci_io_size and io_base_phys always represent IO
602 * space starting at 0 so we factor in pci_addr
604 hose->pci_io_size = range.pci_addr + range.size;
605 hose->io_base_phys = range.cpu_addr - range.pci_addr;
608 res = &hose->io_resource;
609 range.cpu_addr = range.pci_addr;
613 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
614 range.cpu_addr, range.cpu_addr + range.size - 1,
616 (range.pci_space & 0x40000000) ?
619 /* We support only 3 memory ranges */
621 pr_info(" \\--> Skipped (too many) !\n");
624 /* Handles ISA memory hole space here */
625 if (range.pci_addr == 0) {
626 isa_mb = range.cpu_addr;
628 if (primary || isa_mem_base == 0)
629 isa_mem_base = range.cpu_addr;
630 hose->isa_mem_phys = range.cpu_addr;
631 hose->isa_mem_size = range.size;
634 /* We get the PCI/Mem offset from the first range or
635 * the, current one if the offset came from an ISA
636 * hole. If they don't match, bugger.
639 (isa_hole >= 0 && range.pci_addr != 0 &&
640 hose->pci_mem_offset == isa_mb))
641 hose->pci_mem_offset = range.cpu_addr -
643 else if (range.pci_addr != 0 &&
644 hose->pci_mem_offset != range.cpu_addr -
646 pr_info(" \\--> Skipped (offset mismatch) !\n");
651 res = &hose->mem_resources[memno++];
655 res->name = dev->full_name;
656 res->flags = range.flags;
657 res->start = range.cpu_addr;
658 res->end = range.cpu_addr + range.size - 1;
659 res->parent = res->child = res->sibling = NULL;
663 /* If there's an ISA hole and the pci_mem_offset is -not- matching
664 * the ISA hole offset, then we need to remove the ISA hole from
665 * the resource list for that brige
667 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
668 unsigned int next = isa_hole + 1;
669 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
671 memmove(&hose->mem_resources[isa_hole],
672 &hose->mem_resources[next],
673 sizeof(struct resource) * (memno - next));
674 hose->mem_resources[--memno].flags = 0;
678 /* Decide whether to display the domain number in /proc */
679 int pci_proc_domain(struct pci_bus *bus)
684 /* This header fixup will do the resource fixup for all devices as they are
685 * probed, but not for bridge ranges
687 static void pcibios_fixup_resources(struct pci_dev *dev)
689 struct pci_controller *hose = pci_bus_to_host(dev->bus);
693 pr_err("No host bridge for PCI dev %s !\n",
697 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
698 struct resource *res = dev->resource + i;
701 if (res->start == 0) {
702 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
704 (unsigned long long)res->start,
705 (unsigned long long)res->end,
706 (unsigned int)res->flags);
707 pr_debug("is unassigned\n");
708 res->end -= res->start;
710 res->flags |= IORESOURCE_UNSET;
714 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
716 (unsigned long long)res->start,
717 (unsigned long long)res->end,
718 (unsigned int)res->flags);
721 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
723 /* This function tries to figure out if a bridge resource has been initialized
724 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
725 * things go more smoothly when it gets it right. It should covers cases such
726 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
728 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
729 struct resource *res)
731 struct pci_controller *hose = pci_bus_to_host(bus);
732 struct pci_dev *dev = bus->self;
733 resource_size_t offset;
737 /* Job is a bit different between memory and IO */
738 if (res->flags & IORESOURCE_MEM) {
739 /* If the BAR is non-0 (res != pci_mem_offset) then it's
740 * probably been initialized by somebody
742 if (res->start != hose->pci_mem_offset)
745 /* The BAR is 0, let's check if memory decoding is enabled on
746 * the bridge. If not, we consider it unassigned
748 pci_read_config_word(dev, PCI_COMMAND, &command);
749 if ((command & PCI_COMMAND_MEMORY) == 0)
752 /* Memory decoding is enabled and the BAR is 0. If any of
753 * the bridge resources covers that starting address (0 then
754 * it's good enough for us for memory
756 for (i = 0; i < 3; i++) {
757 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
758 hose->mem_resources[i].start == hose->pci_mem_offset)
762 /* Well, it starts at 0 and we know it will collide so we may as
763 * well consider it as unassigned. That covers the Apple case.
767 /* If the BAR is non-0, then we consider it assigned */
768 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
769 if (((res->start - offset) & 0xfffffffful) != 0)
772 /* Here, we are a bit different than memory as typically IO
773 * space starting at low addresses -is- valid. What we do
774 * instead if that we consider as unassigned anything that
775 * doesn't have IO enabled in the PCI command register,
778 pci_read_config_word(dev, PCI_COMMAND, &command);
779 if (command & PCI_COMMAND_IO)
782 /* It's starting at 0 and IO is disabled in the bridge, consider
789 /* Fixup resources of a PCI<->PCI bridge */
790 static void pcibios_fixup_bridge(struct pci_bus *bus)
792 struct resource *res;
795 struct pci_dev *dev = bus->self;
797 pci_bus_for_each_resource(bus, res, i) {
802 if (i >= 3 && bus->self->transparent)
805 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
807 (unsigned long long)res->start,
808 (unsigned long long)res->end,
809 (unsigned int)res->flags);
811 /* Try to detect uninitialized P2P bridge resources,
812 * and clear them out so they get re-assigned later
814 if (pcibios_uninitialized_bridge_resource(bus, res)) {
816 pr_debug("PCI:%s (unassigned)\n",
819 pr_debug("PCI:%s %016llx-%016llx\n",
821 (unsigned long long)res->start,
822 (unsigned long long)res->end);
827 void pcibios_setup_bus_self(struct pci_bus *bus)
829 /* Fix up the bus resources for P2P bridges */
830 if (bus->self != NULL)
831 pcibios_fixup_bridge(bus);
834 void pcibios_setup_bus_devices(struct pci_bus *bus)
838 pr_debug("PCI: Fixup bus devices %d (%s)\n",
839 bus->number, bus->self ? pci_name(bus->self) : "PHB");
841 list_for_each_entry(dev, &bus->devices, bus_list) {
842 /* Setup OF node pointer in archdata */
843 dev->dev.of_node = pci_device_to_OF_node(dev);
845 /* Fixup NUMA node as it may not be setup yet by the generic
846 * code and is needed by the DMA init
848 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
850 /* Read default IRQs and fixup if necessary */
851 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
855 void pcibios_fixup_bus(struct pci_bus *bus)
859 EXPORT_SYMBOL(pcibios_fixup_bus);
862 * We need to avoid collisions with `mirrored' VGA ports
863 * and other strange ISA hardware, so we always want the
864 * addresses to be allocated in the 0x000-0x0ff region
867 * Why? Because some silly external IO cards only decode
868 * the low 10 bits of the IO address. The 0x00-0xff region
869 * is reserved for motherboard devices that decode all 16
870 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
871 * but we want to try to avoid allocating at 0x2900-0x2bff
872 * which might have be mirrored at 0x0100-0x03ff..
874 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
875 resource_size_t size, resource_size_t align)
879 EXPORT_SYMBOL(pcibios_align_resource);
881 int pcibios_add_device(struct pci_dev *dev)
883 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
887 EXPORT_SYMBOL(pcibios_add_device);
890 * Reparent resource children of pr that conflict with res
891 * under res, and make res replace those children.
893 static int __init reparent_resources(struct resource *parent,
894 struct resource *res)
896 struct resource *p, **pp;
897 struct resource **firstpp = NULL;
899 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
900 if (p->end < res->start)
902 if (res->end < p->start)
904 if (p->start < res->start || p->end > res->end)
905 return -1; /* not completely contained */
910 return -1; /* didn't find any conflicting entries? */
911 res->parent = parent;
912 res->child = *firstpp;
916 for (p = res->child; p != NULL; p = p->sibling) {
918 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
920 (unsigned long long)p->start,
921 (unsigned long long)p->end, res->name);
927 * Handle resources of PCI devices. If the world were perfect, we could
928 * just allocate all the resource regions and do nothing more. It isn't.
929 * On the other hand, we cannot just re-allocate all devices, as it would
930 * require us to know lots of host bridge internals. So we attempt to
931 * keep as much of the original configuration as possible, but tweak it
932 * when it's found to be wrong.
934 * Known BIOS problems we have to work around:
935 * - I/O or memory regions not configured
936 * - regions configured, but not enabled in the command register
937 * - bogus I/O addresses above 64K used
938 * - expansion ROMs left enabled (this may sound harmless, but given
939 * the fact the PCI specs explicitly allow address decoders to be
940 * shared between expansion ROMs and other resource regions, it's
941 * at least dangerous)
944 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
945 * This gives us fixed barriers on where we can allocate.
946 * (2) Allocate resources for all enabled devices. If there is
947 * a collision, just mark the resource as unallocated. Also
948 * disable expansion ROMs during this step.
949 * (3) Try to allocate resources for disabled devices. If the
950 * resources were assigned correctly, everything goes well,
951 * if they weren't, they won't disturb allocation of other
953 * (4) Assign new addresses to resources which were either
954 * not configured at all or misconfigured. If explicitly
955 * requested by the user, configure expansion ROM address
959 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
963 struct resource *res, *pr;
965 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
966 pci_domain_nr(bus), bus->number);
968 pci_bus_for_each_resource(bus, res, i) {
969 if (!res || !res->flags
970 || res->start > res->end || res->parent)
972 if (bus->parent == NULL)
973 pr = (res->flags & IORESOURCE_IO) ?
974 &ioport_resource : &iomem_resource;
976 /* Don't bother with non-root busses when
977 * re-assigning all resources. We clear the
978 * resource flags as if they were colliding
979 * and as such ensure proper re-allocation
982 pr = pci_find_parent_resource(bus->self, res);
984 /* this happens when the generic PCI
985 * code (wrongly) decides that this
986 * bridge is transparent -- paulus
992 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
993 bus->self ? pci_name(bus->self) : "PHB",
995 (unsigned long long)res->start,
996 (unsigned long long)res->end);
997 pr_debug("[0x%x], parent %p (%s)\n",
998 (unsigned int)res->flags,
999 pr, (pr && pr->name) ? pr->name : "nil");
1001 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1002 struct pci_dev *dev = bus->self;
1004 if (request_resource(pr, res) == 0)
1007 * Must be a conflict with an existing entry.
1008 * Move that entry (or entries) under the
1009 * bridge resource and try again.
1011 if (reparent_resources(pr, res) == 0)
1014 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1015 pci_claim_bridge_resource(dev,
1016 i + PCI_BRIDGE_RESOURCES) == 0)
1020 pr_warn("PCI: Cannot allocate resource region ");
1021 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1022 res->start = res->end = 0;
1026 list_for_each_entry(b, &bus->children, node)
1027 pcibios_allocate_bus_resources(b);
1030 static inline void alloc_resource(struct pci_dev *dev, int idx)
1032 struct resource *pr, *r = &dev->resource[idx];
1034 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1036 (unsigned long long)r->start,
1037 (unsigned long long)r->end,
1038 (unsigned int)r->flags);
1040 pr = pci_find_parent_resource(dev, r);
1041 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1042 request_resource(pr, r) < 0) {
1043 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1044 pr_cont("of device %s, will remap\n", pci_name(dev));
1046 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1048 (unsigned long long)pr->start,
1049 (unsigned long long)pr->end,
1050 (unsigned int)pr->flags);
1051 /* We'll assign a new address later */
1052 r->flags |= IORESOURCE_UNSET;
1058 static void __init pcibios_allocate_resources(int pass)
1060 struct pci_dev *dev = NULL;
1065 for_each_pci_dev(dev) {
1066 pci_read_config_word(dev, PCI_COMMAND, &command);
1067 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1068 r = &dev->resource[idx];
1069 if (r->parent) /* Already allocated */
1071 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1072 continue; /* Not assigned at all */
1073 /* We only allocate ROMs on pass 1 just in case they
1074 * have been screwed up by firmware
1076 if (idx == PCI_ROM_RESOURCE)
1078 if (r->flags & IORESOURCE_IO)
1079 disabled = !(command & PCI_COMMAND_IO);
1081 disabled = !(command & PCI_COMMAND_MEMORY);
1082 if (pass == disabled)
1083 alloc_resource(dev, idx);
1087 r = &dev->resource[PCI_ROM_RESOURCE];
1089 /* Turn the ROM off, leave the resource region,
1090 * but keep it unregistered.
1093 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1094 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1095 pr_debug("PCI: Switching off ROM of %s\n",
1097 r->flags &= ~IORESOURCE_ROM_ENABLE;
1098 pci_write_config_dword(dev, dev->rom_base_reg,
1099 reg & ~PCI_ROM_ADDRESS_ENABLE);
1105 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1107 struct pci_controller *hose = pci_bus_to_host(bus);
1108 resource_size_t offset;
1109 struct resource *res, *pres;
1112 pr_debug("Reserving legacy ranges for domain %04x\n",
1113 pci_domain_nr(bus));
1116 if (!(hose->io_resource.flags & IORESOURCE_IO))
1118 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1119 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1120 BUG_ON(res == NULL);
1121 res->name = "Legacy IO";
1122 res->flags = IORESOURCE_IO;
1123 res->start = offset;
1124 res->end = (offset + 0xfff) & 0xfffffffful;
1125 pr_debug("Candidate legacy IO: %pR\n", res);
1126 if (request_resource(&hose->io_resource, res)) {
1127 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1128 pci_domain_nr(bus), bus->number, res);
1133 /* Check for memory */
1134 offset = hose->pci_mem_offset;
1135 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1136 for (i = 0; i < 3; i++) {
1137 pres = &hose->mem_resources[i];
1138 if (!(pres->flags & IORESOURCE_MEM))
1140 pr_debug("hose mem res: %pR\n", pres);
1141 if ((pres->start - offset) <= 0xa0000 &&
1142 (pres->end - offset) >= 0xbffff)
1147 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1148 BUG_ON(res == NULL);
1149 res->name = "Legacy VGA memory";
1150 res->flags = IORESOURCE_MEM;
1151 res->start = 0xa0000 + offset;
1152 res->end = 0xbffff + offset;
1153 pr_debug("Candidate VGA memory: %pR\n", res);
1154 if (request_resource(pres, res)) {
1155 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1156 pci_domain_nr(bus), bus->number, res);
1161 void __init pcibios_resource_survey(void)
1165 /* Allocate and assign resources. If we re-assign everything, then
1166 * we skip the allocate phase
1168 list_for_each_entry(b, &pci_root_buses, node)
1169 pcibios_allocate_bus_resources(b);
1171 pcibios_allocate_resources(0);
1172 pcibios_allocate_resources(1);
1174 /* Before we start assigning unassigned resource, we try to reserve
1175 * the low IO area and the VGA memory area if they intersect the
1176 * bus available resources to avoid allocating things on top of them
1178 list_for_each_entry(b, &pci_root_buses, node)
1179 pcibios_reserve_legacy_regions(b);
1181 /* Now proceed to assigning things that were left unassigned */
1182 pr_debug("PCI: Assigning unassigned resources...\n");
1183 pci_assign_unassigned_resources();
1186 /* This is used by the PCI hotplug driver to allocate resource
1187 * of newly plugged busses. We can try to consolidate with the
1188 * rest of the code later, for now, keep it as-is as our main
1189 * resource allocation function doesn't deal with sub-trees yet.
1191 void pcibios_claim_one_bus(struct pci_bus *bus)
1193 struct pci_dev *dev;
1194 struct pci_bus *child_bus;
1196 list_for_each_entry(dev, &bus->devices, bus_list) {
1199 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1200 struct resource *r = &dev->resource[i];
1202 if (r->parent || !r->start || !r->flags)
1205 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1206 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1207 i, (unsigned long long)r->start,
1208 (unsigned long long)r->end,
1209 (unsigned int)r->flags);
1211 if (pci_claim_resource(dev, i) == 0)
1214 pci_claim_bridge_resource(dev, i);
1218 list_for_each_entry(child_bus, &bus->children, node)
1219 pcibios_claim_one_bus(child_bus);
1221 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1224 /* pcibios_finish_adding_to_bus
1226 * This is to be called by the hotplug code after devices have been
1227 * added to a bus, this include calling it for a PHB that is just
1230 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1232 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1233 pci_domain_nr(bus), bus->number);
1235 /* Allocate bus and devices resources */
1236 pcibios_allocate_bus_resources(bus);
1237 pcibios_claim_one_bus(bus);
1239 /* Add new devices to global lists. Register in proc, sysfs. */
1240 pci_bus_add_devices(bus);
1243 /* eeh_add_device_tree_late(bus); */
1245 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1247 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1248 struct list_head *resources)
1250 unsigned long io_offset;
1251 struct resource *res;
1254 /* Hookup PHB IO resource */
1255 res = &hose->io_resource;
1257 /* Fixup IO space offset */
1258 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1259 res->start = (res->start + io_offset) & 0xffffffffu;
1260 res->end = (res->end + io_offset) & 0xffffffffu;
1263 pr_warn("PCI: I/O resource not set for host ");
1264 pr_cont("bridge %s (domain %d)\n",
1265 hose->dn->full_name, hose->global_number);
1266 /* Workaround for lack of IO resource only on 32-bit */
1267 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1268 res->end = res->start + IO_SPACE_LIMIT;
1269 res->flags = IORESOURCE_IO;
1271 pci_add_resource_offset(resources, res,
1272 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1274 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1275 (unsigned long long)res->start,
1276 (unsigned long long)res->end,
1277 (unsigned long)res->flags);
1279 /* Hookup PHB Memory resources */
1280 for (i = 0; i < 3; ++i) {
1281 res = &hose->mem_resources[i];
1285 pr_err("PCI: Memory resource 0 not set for ");
1286 pr_cont("host bridge %s (domain %d)\n",
1287 hose->dn->full_name, hose->global_number);
1289 /* Workaround for lack of MEM resource only on 32-bit */
1290 res->start = hose->pci_mem_offset;
1291 res->end = (resource_size_t)-1LL;
1292 res->flags = IORESOURCE_MEM;
1295 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1297 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1298 i, (unsigned long long)res->start,
1299 (unsigned long long)res->end,
1300 (unsigned long)res->flags);
1303 pr_debug("PCI: PHB MEM offset = %016llx\n",
1304 (unsigned long long)hose->pci_mem_offset);
1305 pr_debug("PCI: PHB IO offset = %08lx\n",
1306 (unsigned long)hose->io_base_virt - _IO_BASE);
1309 static void pcibios_scan_phb(struct pci_controller *hose)
1311 LIST_HEAD(resources);
1312 struct pci_bus *bus;
1313 struct device_node *node = hose->dn;
1315 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1317 pcibios_setup_phb_resources(hose, &resources);
1319 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1320 hose->ops, hose, &resources);
1322 pr_err("Failed to create bus for PCI domain %04x\n",
1323 hose->global_number);
1324 pci_free_resource_list(&resources);
1327 bus->busn_res.start = hose->first_busno;
1330 hose->last_busno = bus->busn_res.end;
1333 static int __init pcibios_init(void)
1335 struct pci_controller *hose, *tmp;
1338 pr_info("PCI: Probing PCI hardware\n");
1340 /* Scan all of the recorded PCI controllers. */
1341 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1342 hose->last_busno = 0xff;
1343 pcibios_scan_phb(hose);
1344 if (next_busno <= hose->last_busno)
1345 next_busno = hose->last_busno + 1;
1347 pci_bus_count = next_busno;
1349 /* Call common code to handle resource allocation */
1350 pcibios_resource_survey();
1351 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1353 pci_bus_add_devices(hose->bus);
1359 subsys_initcall(pcibios_init);
1361 static struct pci_controller *pci_bus_to_hose(int bus)
1363 struct pci_controller *hose, *tmp;
1365 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1366 if (bus >= hose->first_busno && bus <= hose->last_busno)
1371 /* Provide information on locations of various I/O regions in physical
1372 * memory. Do this on a per-card basis so that we choose the right
1374 * Note that the returned IO or memory base is a physical address
1377 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1379 struct pci_controller *hose;
1380 long result = -EOPNOTSUPP;
1382 hose = pci_bus_to_hose(bus);
1387 case IOBASE_BRIDGE_NUMBER:
1388 return (long)hose->first_busno;
1390 return (long)hose->pci_mem_offset;
1392 return (long)hose->io_base_phys;
1394 return (long)isa_io_base;
1395 case IOBASE_ISA_MEM:
1396 return (long)isa_mem_base;
1403 * Null PCI config access functions, for the case when we can't
1406 #define NULL_PCI_OP(rw, size, type) \
1408 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1410 return PCIBIOS_DEVICE_NOT_FOUND; \
1414 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1417 return PCIBIOS_DEVICE_NOT_FOUND;
1421 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1424 return PCIBIOS_DEVICE_NOT_FOUND;
1427 static struct pci_ops null_pci_ops = {
1428 .read = null_read_config,
1429 .write = null_write_config,
1433 * These functions are used early on before PCI scanning is done
1434 * and all of the pci_dev and pci_bus structures have been created.
1436 static struct pci_bus *
1437 fake_pci_bus(struct pci_controller *hose, int busnr)
1439 static struct pci_bus bus;
1442 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1446 bus.ops = hose ? hose->ops : &null_pci_ops;
1450 #define EARLY_PCI_OP(rw, size, type) \
1451 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1452 int devfn, int offset, type value) \
1454 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1455 devfn, offset, value); \
1458 EARLY_PCI_OP(read, byte, u8 *)
1459 EARLY_PCI_OP(read, word, u16 *)
1460 EARLY_PCI_OP(read, dword, u32 *)
1461 EARLY_PCI_OP(write, byte, u8)
1462 EARLY_PCI_OP(write, word, u16)
1463 EARLY_PCI_OP(write, dword, u32)
1465 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1468 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);