2 * DBAu1300 init and platform device setup.
4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/gpio.h>
10 #include <linux/gpio_keys.h>
11 #include <linux/init.h>
12 #include <linux/input.h> /* KEY_* codes */
13 #include <linux/i2c.h>
15 #include <linux/leds.h>
16 #include <linux/ata_platform.h>
17 #include <linux/mmc/host.h>
18 #include <linux/module.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
23 #include <linux/smsc911x.h>
25 #include <asm/mach-au1x00/au1000.h>
26 #include <asm/mach-au1x00/au1100_mmc.h>
27 #include <asm/mach-au1x00/au1200fb.h>
28 #include <asm/mach-au1x00/au1xxx_dbdma.h>
29 #include <asm/mach-au1x00/au1xxx_psc.h>
30 #include <asm/mach-db1x00/bcsr.h>
31 #include <asm/mach-au1x00/prom.h>
35 /* FPGA (external mux) interrupt sources */
36 #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
37 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
38 #define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
39 #define DB1300_CF_INT (DB1300_FIRST_INT + 2)
40 #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
41 #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
42 #define DB1300_DC_INT (DB1300_FIRST_INT + 6)
43 #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
44 #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
45 #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
46 #define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
47 #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
48 #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
49 #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
50 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
51 #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
52 #define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
55 #define DB1300_ETH_PHYS_ADDR 0x19000000
56 #define DB1300_ETH_PHYS_END 0x197fffff
59 #define DB1300_IDE_PHYS_ADDR 0x18800000
60 #define DB1300_IDE_REG_SHIFT 5
61 #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
64 #define DB1300_NAND_PHYS_ADDR 0x20000000
65 #define DB1300_NAND_PHYS_END 0x20000fff
68 static struct i2c_board_info db1300_i2c_devs[] __initdata = {
69 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
70 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
73 /* multifunction pins to assign to GPIO controller */
74 static int db1300_gpio_pins[] __initdata = {
75 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
76 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
81 /* multifunction pins to assign to device functions */
82 static int db1300_dev_pins[] __initdata = {
83 /* wake-from-str pins 0-3 */
85 /* external clock sources for PSC0 */
87 /* 8bit MMC interface on SD0: 6-9 */
88 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
90 /* UART1 pins: 11-18 */
91 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
92 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
93 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
94 /* UART0 pins: 19-24 */
95 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
96 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
98 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
100 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
101 /* LCD controller PWMs, ext pixclock: 30-31 */
102 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
103 /* SD1 interface: 32-37 */
104 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
105 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
106 /* SD2 interface: 38-43 */
107 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
108 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
109 /* PSC0/1 clocks: 44-45 */
110 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
111 /* PSCs: 46-49/50-53/54-57/58-61 */
112 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
114 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
116 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
118 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
120 /* PCMCIA interface: 62-70 */
121 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
122 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
123 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
124 /* camera interface H/V sync inputs: 71-72 */
125 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
126 /* PSC2/3 clocks: 73-74 */
127 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
131 static void __init db1300_gpio_config(void)
135 i = &db1300_dev_pins[0];
137 au1300_pinfunc_to_dev(*i++);
139 i = &db1300_gpio_pins[0];
141 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
143 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
146 /**********************************************************************/
148 static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
151 struct nand_chip *this = mtd->priv;
152 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
154 ioaddr &= 0xffffff00;
156 if (ctrl & NAND_CLE) {
157 ioaddr += MEM_STNAND_CMD;
158 } else if (ctrl & NAND_ALE) {
159 ioaddr += MEM_STNAND_ADDR;
161 /* assume we want to r/w real data by default */
162 ioaddr += MEM_STNAND_DATA;
164 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
165 if (cmd != NAND_CMD_NONE) {
166 __raw_writeb(cmd, this->IO_ADDR_W);
171 static int au1300_nand_device_ready(struct mtd_info *mtd)
173 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
176 static struct mtd_partition db1300_nand_parts[] = {
180 .size = 8 * 1024 * 1024,
184 .offset = MTDPART_OFS_APPEND,
185 .size = MTDPART_SIZ_FULL
189 struct platform_nand_data db1300_nand_platdata = {
193 .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
194 .partitions = db1300_nand_parts,
198 .dev_ready = au1300_nand_device_ready,
199 .cmd_ctrl = au1300_nand_cmd_ctrl,
203 static struct resource db1300_nand_res[] = {
205 .start = DB1300_NAND_PHYS_ADDR,
206 .end = DB1300_NAND_PHYS_ADDR + 0xff,
207 .flags = IORESOURCE_MEM,
211 static struct platform_device db1300_nand_dev = {
213 .num_resources = ARRAY_SIZE(db1300_nand_res),
214 .resource = db1300_nand_res,
217 .platform_data = &db1300_nand_platdata,
221 /**********************************************************************/
223 static struct resource db1300_eth_res[] = {
225 .start = DB1300_ETH_PHYS_ADDR,
226 .end = DB1300_ETH_PHYS_END,
227 .flags = IORESOURCE_MEM,
230 .start = DB1300_ETH_INT,
231 .end = DB1300_ETH_INT,
232 .flags = IORESOURCE_IRQ,
236 static struct smsc911x_platform_config db1300_eth_config = {
237 .phy_interface = PHY_INTERFACE_MODE_MII,
238 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
239 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
240 .flags = SMSC911X_USE_32BIT,
243 static struct platform_device db1300_eth_dev = {
246 .num_resources = ARRAY_SIZE(db1300_eth_res),
247 .resource = db1300_eth_res,
249 .platform_data = &db1300_eth_config,
253 /**********************************************************************/
255 static struct resource au1300_psc1_res[] = {
257 .start = AU1300_PSC1_PHYS_ADDR,
258 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
259 .flags = IORESOURCE_MEM,
262 .start = AU1300_PSC1_INT,
263 .end = AU1300_PSC1_INT,
264 .flags = IORESOURCE_IRQ,
267 .start = AU1300_DSCR_CMD0_PSC1_TX,
268 .end = AU1300_DSCR_CMD0_PSC1_TX,
269 .flags = IORESOURCE_DMA,
272 .start = AU1300_DSCR_CMD0_PSC1_RX,
273 .end = AU1300_DSCR_CMD0_PSC1_RX,
274 .flags = IORESOURCE_DMA,
278 static struct platform_device db1300_ac97_dev = {
279 .name = "au1xpsc_ac97",
280 .id = 1, /* PSC ID. match with AC97 codec ID! */
281 .num_resources = ARRAY_SIZE(au1300_psc1_res),
282 .resource = au1300_psc1_res,
285 /**********************************************************************/
287 static struct resource au1300_psc2_res[] = {
289 .start = AU1300_PSC2_PHYS_ADDR,
290 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
291 .flags = IORESOURCE_MEM,
294 .start = AU1300_PSC2_INT,
295 .end = AU1300_PSC2_INT,
296 .flags = IORESOURCE_IRQ,
299 .start = AU1300_DSCR_CMD0_PSC2_TX,
300 .end = AU1300_DSCR_CMD0_PSC2_TX,
301 .flags = IORESOURCE_DMA,
304 .start = AU1300_DSCR_CMD0_PSC2_RX,
305 .end = AU1300_DSCR_CMD0_PSC2_RX,
306 .flags = IORESOURCE_DMA,
310 static struct platform_device db1300_i2s_dev = {
311 .name = "au1xpsc_i2s",
312 .id = 2, /* PSC ID */
313 .num_resources = ARRAY_SIZE(au1300_psc2_res),
314 .resource = au1300_psc2_res,
317 /**********************************************************************/
319 static struct resource au1300_psc3_res[] = {
321 .start = AU1300_PSC3_PHYS_ADDR,
322 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
323 .flags = IORESOURCE_MEM,
326 .start = AU1300_PSC3_INT,
327 .end = AU1300_PSC3_INT,
328 .flags = IORESOURCE_IRQ,
331 .start = AU1300_DSCR_CMD0_PSC3_TX,
332 .end = AU1300_DSCR_CMD0_PSC3_TX,
333 .flags = IORESOURCE_DMA,
336 .start = AU1300_DSCR_CMD0_PSC3_RX,
337 .end = AU1300_DSCR_CMD0_PSC3_RX,
338 .flags = IORESOURCE_DMA,
342 static struct platform_device db1300_i2c_dev = {
343 .name = "au1xpsc_smbus",
344 .id = 0, /* bus number */
345 .num_resources = ARRAY_SIZE(au1300_psc3_res),
346 .resource = au1300_psc3_res,
349 /**********************************************************************/
351 /* proper key assignments when facing the LCD panel. For key assignments
352 * according to the schematics swap up with down and left with right.
353 * I chose to use it to emulate the arrow keys of a keyboard.
355 static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
358 .gpio = AU1300_PIN_LCDPWM0,
360 .debounce_interval = 1,
362 .desc = "5waysw-down",
366 .gpio = AU1300_PIN_PSC2SYNC1,
368 .debounce_interval = 1,
374 .gpio = AU1300_PIN_WAKE3,
376 .debounce_interval = 1,
378 .desc = "5waysw-right",
382 .gpio = AU1300_PIN_WAKE2,
384 .debounce_interval = 1,
386 .desc = "5waysw-left",
390 .gpio = AU1300_PIN_WAKE1,
392 .debounce_interval = 1,
394 .desc = "5waysw-push",
398 static struct gpio_keys_platform_data db1300_5waysw_data = {
399 .buttons = db1300_5waysw_arrowkeys,
400 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
402 .name = "db1300-5wayswitch",
405 static struct platform_device db1300_5waysw_dev = {
408 .platform_data = &db1300_5waysw_data,
412 /**********************************************************************/
414 static struct pata_platform_info db1300_ide_info = {
415 .ioport_shift = DB1300_IDE_REG_SHIFT,
418 #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
419 static struct resource db1300_ide_res[] = {
421 .start = DB1300_IDE_PHYS_ADDR,
422 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
423 .flags = IORESOURCE_MEM,
426 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
427 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
428 .flags = IORESOURCE_MEM,
431 .start = DB1300_IDE_INT,
432 .end = DB1300_IDE_INT,
433 .flags = IORESOURCE_IRQ,
437 static struct platform_device db1300_ide_dev = {
439 .platform_data = &db1300_ide_info,
441 .name = "pata_platform",
442 .resource = db1300_ide_res,
443 .num_resources = ARRAY_SIZE(db1300_ide_res),
446 /**********************************************************************/
448 static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
450 void(*mmc_cd)(struct mmc_host *, unsigned long);
452 /* disable the one currently screaming. No other way to shut it up */
453 if (irq == DB1300_SD1_INSERT_INT) {
454 disable_irq_nosync(DB1300_SD1_INSERT_INT);
455 enable_irq(DB1300_SD1_EJECT_INT);
457 disable_irq_nosync(DB1300_SD1_EJECT_INT);
458 enable_irq(DB1300_SD1_INSERT_INT);
461 /* link against CONFIG_MMC=m. We can only be called once MMC core has
462 * initialized the controller, so symbol_get() should always succeed.
464 mmc_cd = symbol_get(mmc_detect_change);
465 mmc_cd(ptr, msecs_to_jiffies(500));
466 symbol_put(mmc_detect_change);
471 static int db1300_mmc_card_readonly(void *mmc_host)
473 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
474 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
477 static int db1300_mmc_card_inserted(void *mmc_host)
479 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
482 static int db1300_mmc_cd_setup(void *mmc_host, int en)
487 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
488 "sd_insert", mmc_host);
492 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
493 "sd_eject", mmc_host);
495 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
499 if (db1300_mmc_card_inserted(mmc_host))
500 enable_irq(DB1300_SD1_EJECT_INT);
502 enable_irq(DB1300_SD1_INSERT_INT);
505 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
506 free_irq(DB1300_SD1_EJECT_INT, mmc_host);
513 static void db1300_mmcled_set(struct led_classdev *led,
514 enum led_brightness brightness)
516 if (brightness != LED_OFF)
517 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
519 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
522 static struct led_classdev db1300_mmc_led = {
523 .brightness_set = db1300_mmcled_set,
526 struct au1xmmc_platform_data db1300_sd1_platdata = {
527 .cd_setup = db1300_mmc_cd_setup,
528 .card_inserted = db1300_mmc_card_inserted,
529 .card_readonly = db1300_mmc_card_readonly,
530 .led = &db1300_mmc_led,
533 static struct resource au1300_sd1_res[] = {
535 .start = AU1300_SD1_PHYS_ADDR,
536 .end = AU1300_SD1_PHYS_ADDR,
537 .flags = IORESOURCE_MEM,
540 .start = AU1300_SD1_INT,
541 .end = AU1300_SD1_INT,
542 .flags = IORESOURCE_IRQ,
545 .start = AU1300_DSCR_CMD0_SDMS_TX1,
546 .end = AU1300_DSCR_CMD0_SDMS_TX1,
547 .flags = IORESOURCE_DMA,
550 .start = AU1300_DSCR_CMD0_SDMS_RX1,
551 .end = AU1300_DSCR_CMD0_SDMS_RX1,
552 .flags = IORESOURCE_DMA,
556 static struct platform_device db1300_sd1_dev = {
558 .platform_data = &db1300_sd1_platdata,
560 .name = "au1xxx-mmc",
562 .resource = au1300_sd1_res,
563 .num_resources = ARRAY_SIZE(au1300_sd1_res),
566 /**********************************************************************/
568 static int db1300_movinand_inserted(void *mmc_host)
570 return 0; /* disable for now, it doesn't work yet */
573 static int db1300_movinand_readonly(void *mmc_host)
578 static void db1300_movinand_led_set(struct led_classdev *led,
579 enum led_brightness brightness)
581 if (brightness != LED_OFF)
582 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
584 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
587 static struct led_classdev db1300_movinand_led = {
588 .brightness_set = db1300_movinand_led_set,
591 struct au1xmmc_platform_data db1300_sd0_platdata = {
592 .card_inserted = db1300_movinand_inserted,
593 .card_readonly = db1300_movinand_readonly,
594 .led = &db1300_movinand_led,
595 .mask_host_caps = MMC_CAP_NEEDS_POLL,
598 static struct resource au1300_sd0_res[] = {
600 .start = AU1100_SD0_PHYS_ADDR,
601 .end = AU1100_SD0_PHYS_ADDR,
602 .flags = IORESOURCE_MEM,
605 .start = AU1300_SD0_INT,
606 .end = AU1300_SD0_INT,
607 .flags = IORESOURCE_IRQ,
610 .start = AU1300_DSCR_CMD0_SDMS_TX0,
611 .end = AU1300_DSCR_CMD0_SDMS_TX0,
612 .flags = IORESOURCE_DMA,
615 .start = AU1300_DSCR_CMD0_SDMS_RX0,
616 .end = AU1300_DSCR_CMD0_SDMS_RX0,
617 .flags = IORESOURCE_DMA,
621 static struct platform_device db1300_sd0_dev = {
623 .platform_data = &db1300_sd0_platdata,
625 .name = "au1xxx-mmc",
627 .resource = au1300_sd0_res,
628 .num_resources = ARRAY_SIZE(au1300_sd0_res),
631 /**********************************************************************/
633 static struct platform_device db1300_wm9715_dev = {
634 .name = "wm9712-codec",
635 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
638 static struct platform_device db1300_ac97dma_dev = {
639 .name = "au1xpsc-pcm",
640 .id = 1, /* PSC ID */
643 static struct platform_device db1300_i2sdma_dev = {
644 .name = "au1xpsc-pcm",
645 .id = 2, /* PSC ID */
648 static struct platform_device db1300_sndac97_dev = {
649 .name = "db1300-ac97",
652 static struct platform_device db1300_sndi2s_dev = {
653 .name = "db1300-i2s",
656 /**********************************************************************/
658 static int db1300fb_panel_index(void)
660 return 9; /* DB1300_800x480 */
663 static int db1300fb_panel_init(void)
665 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
666 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
671 static int db1300fb_panel_shutdown(void)
673 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
674 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
675 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
679 static struct au1200fb_platdata db1300fb_pd = {
680 .panel_index = db1300fb_panel_index,
681 .panel_init = db1300fb_panel_init,
682 .panel_shutdown = db1300fb_panel_shutdown,
685 static struct resource au1300_lcd_res[] = {
687 .start = AU1200_LCD_PHYS_ADDR,
688 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
689 .flags = IORESOURCE_MEM,
692 .start = AU1300_LCD_INT,
693 .end = AU1300_LCD_INT,
694 .flags = IORESOURCE_IRQ,
698 static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
700 static struct platform_device db1300_lcd_dev = {
701 .name = "au1200-lcd",
704 .dma_mask = &au1300_lcd_dmamask,
705 .coherent_dma_mask = DMA_BIT_MASK(32),
706 .platform_data = &db1300fb_pd,
708 .num_resources = ARRAY_SIZE(au1300_lcd_res),
709 .resource = au1300_lcd_res,
712 /**********************************************************************/
714 static struct platform_device *db1300_dev[] __initdata = {
732 int __init db1300_dev_setup(void)
734 int swapped, cpldirq;
737 /* setup CPLD IRQ muxer */
738 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
739 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
740 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
742 /* insert/eject IRQs: one always triggers so don't enable them
743 * when doing request_irq() on them. DB1200 has this bug too.
745 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
746 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
747 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
748 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
753 prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
755 i2c_register_board_info(0, db1300_i2c_devs,
756 ARRAY_SIZE(db1300_i2c_devs));
758 /* Audio PSC clock is supplied by codecs (PSC1, 2) */
759 __raw_writel(PSC_SEL_CLK_SERCLK,
760 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
762 __raw_writel(PSC_SEL_CLK_SERCLK,
763 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
765 /* I2C uses internal 48MHz EXTCLK1 */
766 c = clk_get(NULL, "psc3_intclk");
768 clk_prepare_enable(c);
771 __raw_writel(PSC_SEL_CLK_INTCLK,
772 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
775 /* enable power to USB ports */
776 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
778 /* although it is socket #0, it uses the CPLD bits which previous boards
779 * have used for socket #1.
781 db1x_register_pcmcia_socket(
782 AU1000_PCMCIA_ATTR_PHYS_ADDR,
783 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
784 AU1000_PCMCIA_MEM_PHYS_ADDR,
785 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
786 AU1000_PCMCIA_IO_PHYS_ADDR,
787 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
788 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
790 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
791 db1x_register_norflash(64 << 20, 2, swapped);
793 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
797 int __init db1300_board_setup(void)
799 unsigned short whoami;
801 bcsr_init(DB1300_BCSR_PHYS_ADDR,
802 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
804 whoami = bcsr_read(BCSR_WHOAMI);
805 if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300)
808 db1300_gpio_config();
810 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
811 "BoardID %d CPLD Rev %d DaughtercardID %d\n",
812 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
813 BCSR_WHOAMI_DCID(whoami));
815 /* enable UARTs, YAMON only enables #2 */
816 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
817 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
818 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);