arch/mips/boot/dts/brcm/bcm7360.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7360";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <375000000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips3300";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17         };
  18
  19         aliases {
  20                 uart0 = &uart0;
  21                 uart1 = &uart1;
  22                 uart2 = &uart2;
  23         };
  24
  25         cpu_intc: cpu_intc {
  26                 #address-cells = <0>;
  27                 compatible = "mti,cpu-interrupt-controller";
  28
  29                 interrupt-controller;
  30                 #interrupt-cells = <1>;
  31         };
  32
  33         clocks {
  34                 uart_clk: uart_clk {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <81000000>;
  38                 };
  39         };
  40
  41         rdb {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44
  45                 compatible = "simple-bus";
  46                 ranges = <0 0x10000000 0x01000000>;
  47
  48                 periph_intc: periph_intc@411400 {
  49                         compatible = "brcm,bcm7038-l1-intc";
  50                         reg = <0x411400 0x30>;
  51
  52                         interrupt-controller;
  53                         #interrupt-cells = <1>;
  54
  55                         interrupt-parent = <&cpu_intc>;
  56                         interrupts = <2>;
  57                 };
  58
  59                 sun_l2_intc: sun_l2_intc@403000 {
  60                         compatible = "brcm,l2-intc";
  61                         reg = <0x403000 0x30>;
  62                         interrupt-controller;
  63                         #interrupt-cells = <1>;
  64                         interrupt-parent = <&periph_intc>;
  65                         interrupts = <48>;
  66                 };
  67
  68                 gisb-arb@400000 {
  69                         compatible = "brcm,bcm7400-gisb-arb";
  70                         reg = <0x400000 0xdc>;
  71                         native-endian;
  72                         interrupt-parent = <&sun_l2_intc>;
  73                         interrupts = <0>, <2>;
  74                         brcm,gisb-arb-master-mask = <0x2f3>;
  75                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  76                                                      "rdc_0", "raaga_0",
  77                                                      "avd_0", "jtag_0";
  78                 };
  79
  80                 upg_irq0_intc: upg_irq0_intc@406600 {
  81                         compatible = "brcm,bcm7120-l2-intc";
  82                         reg = <0x406600 0x8>;
  83
  84                         brcm,int-map-mask = <0x44>, <0x7000000>;
  85                         brcm,int-fwd-mask = <0x70000>;
  86
  87                         interrupt-controller;
  88                         #interrupt-cells = <1>;
  89
  90                         interrupt-parent = <&periph_intc>;
  91                         interrupts = <56>, <54>;
  92                         interrupt-names = "upg_main", "upg_bsc";
  93                 };
  94
  95                 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
  96                         compatible = "brcm,bcm7120-l2-intc";
  97                         reg = <0x408b80 0x8>;
  98
  99                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
 100                         brcm,int-fwd-mask = <0>;
 101                         brcm,irq-can-wake;
 102
 103                         interrupt-controller;
 104                         #interrupt-cells = <1>;
 105
 106                         interrupt-parent = <&periph_intc>;
 107                         interrupts = <57>, <55>, <59>;
 108                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
 109                                           "upg_spi";
 110                 };
 111
 112                 sun_top_ctrl: syscon@404000 {
 113                         compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
 114                         reg = <0x404000 0x51c>;
 115                 };
 116
 117                 reboot {
 118                         compatible = "brcm,brcmstb-reboot";
 119                         syscon = <&sun_top_ctrl 0x304 0x308>;
 120                 };
 121
 122                 uart0: serial@406800 {
 123                         compatible = "ns16550a";
 124                         reg = <0x406800 0x20>;
 125                         reg-io-width = <0x4>;
 126                         reg-shift = <0x2>;
 127                         native-endian;
 128                         interrupt-parent = <&periph_intc>;
 129                         interrupts = <61>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart1: serial@406840 {
 135                         compatible = "ns16550a";
 136                         reg = <0x406840 0x20>;
 137                         reg-io-width = <0x4>;
 138                         reg-shift = <0x2>;
 139                         native-endian;
 140                         interrupt-parent = <&periph_intc>;
 141                         interrupts = <62>;
 142                         clocks = <&uart_clk>;
 143                         status = "disabled";
 144                 };
 145
 146                 uart2: serial@406880 {
 147                         compatible = "ns16550a";
 148                         reg = <0x406880 0x20>;
 149                         reg-io-width = <0x4>;
 150                         reg-shift = <0x2>;
 151                         native-endian;
 152                         interrupt-parent = <&periph_intc>;
 153                         interrupts = <63>;
 154                         clocks = <&uart_clk>;
 155                         status = "disabled";
 156                 };
 157
 158                 bsca: i2c@406200 {
 159                       clock-frequency = <390000>;
 160                       compatible = "brcm,brcmstb-i2c";
 161                       interrupt-parent = <&upg_irq0_intc>;
 162                       reg = <0x406200 0x58>;
 163                       interrupts = <24>;
 164                       interrupt-names = "upg_bsca";
 165                       status = "disabled";
 166                 };
 167
 168                 bscb: i2c@406280 {
 169                       clock-frequency = <390000>;
 170                       compatible = "brcm,brcmstb-i2c";
 171                       interrupt-parent = <&upg_irq0_intc>;
 172                       reg = <0x406280 0x58>;
 173                       interrupts = <25>;
 174                       interrupt-names = "upg_bscb";
 175                       status = "disabled";
 176                 };
 177
 178                 bscc: i2c@406300 {
 179                       clock-frequency = <390000>;
 180                       compatible = "brcm,brcmstb-i2c";
 181                       interrupt-parent = <&upg_irq0_intc>;
 182                       reg = <0x406300 0x58>;
 183                       interrupts = <26>;
 184                       interrupt-names = "upg_bscc";
 185                       status = "disabled";
 186                 };
 187
 188                 bscd: i2c@408980 {
 189                       clock-frequency = <390000>;
 190                       compatible = "brcm,brcmstb-i2c";
 191                       interrupt-parent = <&upg_aon_irq0_intc>;
 192                       reg = <0x408980 0x58>;
 193                       interrupts = <27>;
 194                       interrupt-names = "upg_bscd";
 195                       status = "disabled";
 196                 };
 197
 198                 enet0: ethernet@430000 {
 199                         phy-mode = "internal";
 200                         phy-handle = <&phy1>;
 201                         mac-address = [ 00 10 18 36 23 1a ];
 202                         compatible = "brcm,genet-v2";
 203                         #address-cells = <0x1>;
 204                         #size-cells = <0x1>;
 205                         reg = <0x430000 0x4c8c>;
 206                         interrupts = <24>, <25>;
 207                         interrupt-parent = <&periph_intc>;
 208                         status = "disabled";
 209
 210                         mdio@e14 {
 211                                 compatible = "brcm,genet-mdio-v2";
 212                                 #address-cells = <0x1>;
 213                                 #size-cells = <0x0>;
 214                                 reg = <0xe14 0x8>;
 215
 216                                 phy1: ethernet-phy@1 {
 217                                         max-speed = <100>;
 218                                         reg = <0x1>;
 219                                         compatible = "brcm,40nm-ephy",
 220                                                 "ethernet-phy-ieee802.3-c22";
 221                                 };
 222                         };
 223                 };
 224
 225                 ehci0: usb@480300 {
 226                         compatible = "brcm,bcm7360-ehci", "generic-ehci";
 227                         reg = <0x480300 0x100>;
 228                         native-endian;
 229                         interrupt-parent = <&periph_intc>;
 230                         interrupts = <65>;
 231                         status = "disabled";
 232                 };
 233
 234                 ohci0: usb@480400 {
 235                         compatible = "brcm,bcm7360-ohci", "generic-ohci";
 236                         reg = <0x480400 0x100>;
 237                         native-endian;
 238                         no-big-frame-no;
 239                         interrupt-parent = <&periph_intc>;
 240                         interrupts = <66>;
 241                         status = "disabled";
 242                 };
 243         };
 244 };