2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/compiler.h>
11 #include <linux/vmalloc.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/console.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/interrupt.h>
19 #include <linux/serial.h>
20 #include <linux/smp.h>
21 #include <linux/types.h>
22 #include <linux/string.h> /* for memset */
23 #include <linux/tty.h>
24 #include <linux/time.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/of_fdt.h>
29 #include <linux/libfdt.h>
30 #include <linux/kexec.h>
32 #include <asm/processor.h>
33 #include <asm/reboot.h>
34 #include <asm/smp-ops.h>
35 #include <asm/irq_cpu.h>
36 #include <asm/mipsregs.h>
37 #include <asm/bootinfo.h>
38 #include <asm/sections.h>
41 #include <asm/octeon/octeon.h>
42 #include <asm/octeon/pci-octeon.h>
43 #include <asm/octeon/cvmx-rst-defs.h>
46 * TRUE for devices having registers with little-endian byte
47 * order, FALSE for registers with native-endian byte order.
48 * PCI mandates little-endian, USB and SATA are configuraable,
49 * but we chose little-endian for these.
51 const bool octeon_should_swizzle_table[256] = {
52 [0x00] = true, /* bootbus/CF */
53 [0x1b] = true, /* PCI mmio window */
54 [0x1c] = true, /* PCI mmio window */
55 [0x1d] = true, /* PCI mmio window */
56 [0x1e] = true, /* PCI mmio window */
57 [0x68] = true, /* OCTEON III USB */
58 [0x69] = true, /* OCTEON III USB */
59 [0x6c] = true, /* OCTEON III SATA */
60 [0x6f] = true, /* OCTEON II USB */
62 EXPORT_SYMBOL(octeon_should_swizzle_table);
65 extern void pci_console_init(const char *arg);
68 static unsigned long long MAX_MEMORY = 512ull << 20;
70 DEFINE_SEMAPHORE(octeon_bootbus_sem);
71 EXPORT_SYMBOL(octeon_bootbus_sem);
73 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
75 struct cvmx_bootinfo *octeon_bootinfo;
76 EXPORT_SYMBOL(octeon_bootinfo);
78 static unsigned long long RESERVE_LOW_MEM = 0ull;
82 * Wait for relocation code is prepared and send
83 * secondary CPUs to spin until kernel is relocated.
85 static void octeon_kexec_smp_down(void *ignored)
87 int cpu = smp_processor_id();
90 set_cpu_online(cpu, false);
91 while (!atomic_read(&kexec_ready_to_reboot))
98 relocated_kexec_smp_wait(NULL);
102 #define OCTEON_DDR0_BASE (0x0ULL)
103 #define OCTEON_DDR0_SIZE (0x010000000ULL)
104 #define OCTEON_DDR1_BASE (0x410000000ULL)
105 #define OCTEON_DDR1_SIZE (0x010000000ULL)
106 #define OCTEON_DDR2_BASE (0x020000000ULL)
107 #define OCTEON_DDR2_SIZE (0x3e0000000ULL)
108 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
110 static struct kimage *kimage_ptr;
112 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
115 struct cvmx_bootmem_desc *bootmem_desc;
117 bootmem_desc = cvmx_bootmem_get_desc();
119 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
120 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
121 pr_err("Error: requested memory too large,"
122 "truncating to maximum size\n");
125 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
126 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
128 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
129 bootmem_desc->head_addr = 0;
131 if (mem_size <= OCTEON_DDR0_SIZE) {
132 __cvmx_bootmem_phy_free(addr,
133 mem_size - RESERVE_LOW_MEM -
134 low_reserved_bytes, 0);
138 __cvmx_bootmem_phy_free(addr,
139 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
140 low_reserved_bytes, 0);
142 mem_size -= OCTEON_DDR0_SIZE;
144 if (mem_size > OCTEON_DDR1_SIZE) {
145 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
146 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
147 mem_size - OCTEON_DDR1_SIZE, 0);
149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
152 static int octeon_kexec_prepare(struct kimage *image)
155 char *bootloader = "kexec";
157 octeon_boot_desc_ptr->argc = 0;
158 for (i = 0; i < image->nr_segments; i++) {
159 if (!strncmp(bootloader, (char *)image->segment[i].buf,
160 strlen(bootloader))) {
162 * convert command line string to array
163 * of parameters (as bootloader does).
166 char *str = (char *)image->segment[i].buf;
167 char *ptr = strchr(str, ' ');
168 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
171 offt = (int)(ptr - str + 1);
172 octeon_boot_desc_ptr->argv[argc] =
173 image->segment[i].mem + offt;
176 ptr = strchr(ptr + 1, ' ');
178 octeon_boot_desc_ptr->argc = argc;
184 * Information about segments will be needed during pre-boot memory
191 static void octeon_generic_shutdown(void)
197 struct cvmx_bootmem_desc *bootmem_desc;
198 void *named_block_array_ptr;
200 bootmem_desc = cvmx_bootmem_get_desc();
201 named_block_array_ptr =
202 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
205 /* disable watchdogs */
206 for_each_online_cpu(cpu)
207 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
209 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
211 if (kimage_ptr != kexec_crash_image) {
212 memset(named_block_array_ptr,
214 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
215 sizeof(struct cvmx_bootmem_named_block_desc));
217 * Mark all memory (except low 0x100000 bytes) as free.
218 * It is the same thing that bootloader does.
220 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
223 * Allocate all segments to avoid their corruption during boot.
225 for (i = 0; i < kimage_ptr->nr_segments; i++)
226 cvmx_bootmem_alloc_address(
227 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
228 kimage_ptr->segment[i].mem - PAGE_SIZE,
232 * Do not mark all memory as free. Free only named sections
233 * leaving the rest of memory unchanged.
235 struct cvmx_bootmem_named_block_desc *ptr =
236 (struct cvmx_bootmem_named_block_desc *)
237 named_block_array_ptr;
239 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
241 cvmx_bootmem_free_named(ptr[i].name);
243 kexec_args[2] = 1UL; /* running on octeon_main_processor */
244 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
246 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
247 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
251 static void octeon_shutdown(void)
253 octeon_generic_shutdown();
255 smp_call_function(octeon_kexec_smp_down, NULL, 0);
257 while (num_online_cpus() > 1) {
264 static void octeon_crash_shutdown(struct pt_regs *regs)
266 octeon_generic_shutdown();
267 default_machine_crash_shutdown(regs);
270 #endif /* CONFIG_KEXEC */
272 #ifdef CONFIG_CAVIUM_RESERVE32
273 uint64_t octeon_reserve32_memory;
274 EXPORT_SYMBOL(octeon_reserve32_memory);
278 /* crashkernel cmdline parameter is parsed _after_ memory setup
279 * we also parse it here (workaround for EHB5200) */
280 static uint64_t crashk_size, crashk_base;
283 static int octeon_uart;
285 extern asmlinkage void handle_int(void);
288 * Return non zero if we are currently running in the Octeon simulator
292 int octeon_is_simulation(void)
294 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
296 EXPORT_SYMBOL(octeon_is_simulation);
299 * Return true if Octeon is in PCI Host mode. This means
300 * Linux can control the PCI bus.
302 * Returns Non zero if Octeon in host mode.
304 int octeon_is_pci_host(void)
307 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
314 * Get the clock rate of Octeon
316 * Returns Clock rate in HZ
318 uint64_t octeon_get_clock_rate(void)
320 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
322 return sysinfo->cpu_clock_hz;
324 EXPORT_SYMBOL(octeon_get_clock_rate);
326 static u64 octeon_io_clock_rate;
328 u64 octeon_get_io_clock_rate(void)
330 return octeon_io_clock_rate;
332 EXPORT_SYMBOL(octeon_get_io_clock_rate);
336 * Write to the LCD display connected to the bootbus. This display
337 * exists on most Cavium evaluation boards. If it doesn't exist, then
338 * this function doesn't do anything.
340 * @s: String to write
342 void octeon_write_lcd(const char *s)
344 if (octeon_bootinfo->led_display_base_addr) {
345 void __iomem *lcd_address =
346 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
349 for (i = 0; i < 8; i++, s++) {
351 iowrite8(*s, lcd_address + i);
353 iowrite8(' ', lcd_address + i);
355 iounmap(lcd_address);
360 * Return the console uart passed by the bootloader
362 * Returns uart (0 or 1)
364 int octeon_get_boot_uart(void)
367 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
370 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
377 * Get the coremask Linux was booted on.
381 int octeon_get_boot_coremask(void)
383 return octeon_boot_desc_ptr->core_mask;
387 * Check the hardware BIST results for a CPU
389 void octeon_check_cpu_bist(void)
391 const int coreid = cvmx_get_core_num();
392 unsigned long long mask;
393 unsigned long long bist_val;
395 /* Check BIST results for COP0 registers */
396 mask = 0x1f00000000ull;
397 bist_val = read_octeon_c0_icacheerr();
399 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
402 bist_val = read_octeon_c0_dcacheerr();
404 pr_err("Core%d L1 Dcache parity error: "
405 "CacheErr(dcache) = 0x%llx\n",
408 mask = 0xfc00000000000000ull;
409 bist_val = read_c0_cvmmemctl();
411 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
414 write_octeon_c0_dcacheerr(0);
420 * @command: Command to pass to the bootloader. Currently ignored.
422 static void octeon_restart(char *command)
424 /* Disable all watchdogs before soft reset. They don't get cleared */
427 for_each_online_cpu(cpu)
428 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
430 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
435 if (OCTEON_IS_OCTEON3())
436 cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
438 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
443 * Permanently stop a core.
447 static void octeon_kill_core(void *arg)
449 if (octeon_is_simulation())
450 /* A break instruction causes the simulator stop a core */
451 asm volatile ("break" ::: "memory");
454 /* Disable watchdog on this core. */
455 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
456 /* Spin in a low power mode. */
458 asm volatile ("wait" ::: "memory");
465 static void octeon_halt(void)
467 smp_call_function(octeon_kill_core, NULL, 0);
469 switch (octeon_bootinfo->board_type) {
470 case CVMX_BOARD_TYPE_NAO38:
471 /* Driving a 1 to GPIO 12 shuts off this board */
472 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
473 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
476 octeon_write_lcd("PowerOff");
480 octeon_kill_core(NULL);
483 static char __read_mostly octeon_system_type[80];
485 static void __init init_octeon_system_type(void)
487 char const *board_type;
489 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type);
490 if (board_type == NULL) {
491 struct device_node *root;
494 root = of_find_node_by_path("/");
495 ret = of_property_read_string(root, "model", &board_type);
498 board_type = "Unsupported Board";
501 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
502 board_type, octeon_model_get_string(read_c0_prid()));
506 * Return a string representing the system type
510 const char *octeon_board_type_string(void)
512 return octeon_system_type;
515 const char *get_system_type(void)
516 __attribute__ ((alias("octeon_board_type_string")));
518 void octeon_user_io_init(void)
520 union octeon_cvmemctl cvmmemctl;
522 /* Get the current settings for CP0_CVMMEMCTL_REG */
523 cvmmemctl.u64 = read_c0_cvmmemctl();
524 /* R/W If set, marked write-buffer entries time out the same
525 * as as other entries; if clear, marked write-buffer entries
526 * use the maximum timeout. */
527 cvmmemctl.s.dismarkwblongto = 1;
528 /* R/W If set, a merged store does not clear the write-buffer
529 * entry timeout state. */
530 cvmmemctl.s.dismrgclrwbto = 0;
531 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
532 * word location for an IOBDMA. The other 8 bits come from the
533 * SCRADDR field of the IOBDMA. */
534 cvmmemctl.s.iobdmascrmsb = 0;
535 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
536 * clear, SYNCWS and SYNCS only order unmarked
537 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
539 cvmmemctl.s.syncwsmarked = 0;
540 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
541 cvmmemctl.s.dissyncws = 0;
542 /* R/W If set, no stall happens on write buffer full. */
543 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
544 cvmmemctl.s.diswbfst = 1;
546 cvmmemctl.s.diswbfst = 0;
547 /* R/W If set (and SX set), supervisor-level loads/stores can
548 * use XKPHYS addresses with <48>==0 */
549 cvmmemctl.s.xkmemenas = 0;
551 /* R/W If set (and UX set), user-level loads/stores can use
552 * XKPHYS addresses with VA<48>==0 */
553 cvmmemctl.s.xkmemenau = 0;
555 /* R/W If set (and SX set), supervisor-level loads/stores can
556 * use XKPHYS addresses with VA<48>==1 */
557 cvmmemctl.s.xkioenas = 0;
559 /* R/W If set (and UX set), user-level loads/stores can use
560 * XKPHYS addresses with VA<48>==1 */
561 cvmmemctl.s.xkioenau = 0;
563 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
564 * when this is set) RW, reset to 0. */
565 cvmmemctl.s.allsyncw = 0;
567 /* R/W If set, no stores merge, and all stores reach the
568 * coherent bus in order. */
569 cvmmemctl.s.nomerge = 0;
570 /* R/W Selects the bit in the counter used for DID time-outs 0
571 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
572 * between 1x and 2x this interval. For example, with
573 * DIDTTO=3, expiration interval is between 16K and 32K. */
574 cvmmemctl.s.didtto = 0;
575 /* R/W If set, the (mem) CSR clock never turns off. */
576 cvmmemctl.s.csrckalwys = 0;
577 /* R/W If set, mclk never turns off. */
578 cvmmemctl.s.mclkalwys = 0;
579 /* R/W Selects the bit in the counter used for write buffer
580 * flush time-outs (WBFLT+11) is the bit position in an
581 * internal counter used to determine expiration. The write
582 * buffer expires between 1x and 2x this interval. For
583 * example, with WBFLT = 0, a write buffer expires between 2K
584 * and 4K cycles after the write buffer entry is allocated. */
585 cvmmemctl.s.wbfltime = 0;
586 /* R/W If set, do not put Istream in the L2 cache. */
587 cvmmemctl.s.istrnol2 = 0;
590 * R/W The write buffer threshold. As per erratum Core-14752
591 * for CN63XX, a sc/scd might fail if the write buffer is
592 * full. Lowering WBTHRESH greatly lowers the chances of the
593 * write buffer ever being full and triggering the erratum.
595 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
596 cvmmemctl.s.wbthresh = 4;
598 cvmmemctl.s.wbthresh = 10;
600 /* R/W If set, CVMSEG is available for loads/stores in
601 * kernel/debug mode. */
602 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
603 cvmmemctl.s.cvmsegenak = 1;
605 cvmmemctl.s.cvmsegenak = 0;
607 /* R/W If set, CVMSEG is available for loads/stores in
608 * supervisor mode. */
609 cvmmemctl.s.cvmsegenas = 0;
610 /* R/W If set, CVMSEG is available for loads/stores in user
612 cvmmemctl.s.cvmsegenau = 0;
614 write_c0_cvmmemctl(cvmmemctl.u64);
616 /* Setup of CVMSEG is done in kernel-entry-init.h */
617 if (smp_processor_id() == 0)
618 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
619 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
620 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
622 if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
623 union cvmx_iob_fau_timeout fau_timeout;
625 /* Set a default for the hardware timeouts */
627 fau_timeout.s.tout_val = 0xfff;
628 /* Disable tagwait FAU timeout */
629 fau_timeout.s.tout_enb = 0;
630 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
633 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
634 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) ||
635 OCTEON_IS_MODEL(OCTEON_CN70XX)) {
636 union cvmx_pow_nw_tim nm_tim;
641 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
644 write_octeon_c0_icacheerr(0);
645 write_c0_derraddr1(0);
649 * Early entry point for arch setup
651 void __init prom_init(void)
653 struct cvmx_sysinfo *sysinfo;
659 #ifdef CONFIG_CAVIUM_RESERVE32
663 * The bootloader passes a pointer to the boot descriptor in
664 * $a3, this is available as fw_arg3.
666 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
668 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
669 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
671 sysinfo = cvmx_sysinfo_get();
672 memset(sysinfo, 0, sizeof(*sysinfo));
673 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
674 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr);
676 if ((octeon_bootinfo->major_version > 1) ||
677 (octeon_bootinfo->major_version == 1 &&
678 octeon_bootinfo->minor_version >= 4))
679 cvmx_coremask_copy(&sysinfo->core_mask,
680 &octeon_bootinfo->ext_core_mask);
682 cvmx_coremask_set64(&sysinfo->core_mask,
683 octeon_bootinfo->core_mask);
685 /* Some broken u-boot pass garbage in upper bits, clear them out */
686 if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
687 for (i = 512; i < 1024; i++)
688 cvmx_coremask_clear_core(&sysinfo->core_mask, i);
690 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
691 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
692 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
693 sysinfo->board_type = octeon_bootinfo->board_type;
694 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
695 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
696 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
697 sizeof(sysinfo->mac_addr_base));
698 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
699 memcpy(sysinfo->board_serial_number,
700 octeon_bootinfo->board_serial_number,
701 sizeof(sysinfo->board_serial_number));
702 sysinfo->compact_flash_common_base_addr =
703 octeon_bootinfo->compact_flash_common_base_addr;
704 sysinfo->compact_flash_attribute_base_addr =
705 octeon_bootinfo->compact_flash_attribute_base_addr;
706 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
707 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
708 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
710 if (OCTEON_IS_OCTEON2()) {
711 /* I/O clock runs at a different rate than the CPU. */
712 union cvmx_mio_rst_boot rst_boot;
713 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
714 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
715 } else if (OCTEON_IS_OCTEON3()) {
716 /* I/O clock runs at a different rate than the CPU. */
717 union cvmx_rst_boot rst_boot;
718 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
719 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
721 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
724 t = read_c0_cvmctl();
725 if ((t & (1ull << 27)) == 0) {
727 * Setup the multiplier save/restore code if
728 * CvmCtl[NOMUL] clear.
736 int save_max = (char *)octeon_mult_save_end -
737 (char *)octeon_mult_save;
738 int restore_max = (char *)octeon_mult_restore_end -
739 (char *)octeon_mult_restore;
740 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
741 save = octeon_mult_save3;
742 save_end = octeon_mult_save3_end;
743 restore = octeon_mult_restore3;
744 restore_end = octeon_mult_restore3_end;
746 save = octeon_mult_save2;
747 save_end = octeon_mult_save2_end;
748 restore = octeon_mult_restore2;
749 restore_end = octeon_mult_restore2_end;
751 save_len = (char *)save_end - (char *)save;
752 restore_len = (char *)restore_end - (char *)restore;
753 if (!WARN_ON(save_len > save_max ||
754 restore_len > restore_max)) {
755 memcpy(octeon_mult_save, save, save_len);
756 memcpy(octeon_mult_restore, restore, restore_len);
761 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
762 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
764 if (!octeon_is_simulation() &&
765 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
766 cvmx_write_csr(CVMX_LED_EN, 0);
767 cvmx_write_csr(CVMX_LED_PRT, 0);
768 cvmx_write_csr(CVMX_LED_DBG, 0);
769 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
770 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
771 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
772 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
773 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
774 cvmx_write_csr(CVMX_LED_EN, 1);
776 #ifdef CONFIG_CAVIUM_RESERVE32
778 * We need to temporarily allocate all memory in the reserve32
779 * region. This makes sure the kernel doesn't allocate this
780 * memory when it is getting memory from the
781 * bootloader. Later, after the memory allocations are
782 * complete, the reserve32 will be freed.
784 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
785 * is in case we later use hugetlb entries with it.
787 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
789 "CAVIUM_RESERVE32", 0);
791 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
793 octeon_reserve32_memory = addr;
796 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
797 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
798 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
800 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
801 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
803 cvmx_l2c_lock_mem_region(ebase, 0x100);
805 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
806 /* General exception */
807 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
809 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
810 /* Interrupt handler */
811 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
813 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
814 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
815 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
817 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
818 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
823 octeon_check_cpu_bist();
825 octeon_uart = octeon_get_boot_uart();
828 octeon_write_lcd("LinuxSMP");
830 octeon_write_lcd("Linux");
833 octeon_setup_delays();
836 * BIST should always be enabled when doing a soft reset. L2
837 * Cache locking for instance is not cleared unless BIST is
838 * enabled. Unfortunately due to a chip errata G-200 for
839 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
841 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
842 OCTEON_IS_MODEL(OCTEON_CN31XX))
843 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
845 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
847 /* Default to 64MB in the simulator to speed things up */
848 if (octeon_is_simulation())
849 MAX_MEMORY = 64ull << 20;
851 arg = strstr(arcs_cmdline, "mem=");
853 MAX_MEMORY = memparse(arg + 4, &p);
855 MAX_MEMORY = 32ull << 30;
857 RESERVE_LOW_MEM = memparse(p + 1, &p);
861 argc = octeon_boot_desc_ptr->argc;
862 for (i = 0; i < argc; i++) {
864 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
865 if ((strncmp(arg, "MEM=", 4) == 0) ||
866 (strncmp(arg, "mem=", 4) == 0)) {
867 MAX_MEMORY = memparse(arg + 4, &p);
869 MAX_MEMORY = 32ull << 30;
871 RESERVE_LOW_MEM = memparse(p + 1, &p);
873 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
874 crashk_size = memparse(arg+12, &p);
876 crashk_base = memparse(p+1, &p);
877 strcat(arcs_cmdline, " ");
878 strcat(arcs_cmdline, arg);
880 * To do: switch parsing to new style, something like:
881 * parse_crashkernel(arg, sysinfo->system_dram_size,
882 * &crashk_size, &crashk_base);
885 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
886 sizeof(arcs_cmdline) - 1) {
887 strcat(arcs_cmdline, " ");
888 strcat(arcs_cmdline, arg);
892 if (strstr(arcs_cmdline, "console=") == NULL) {
893 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
894 strcat(arcs_cmdline, " console=ttyS0,115200");
896 if (octeon_uart == 1)
897 strcat(arcs_cmdline, " console=ttyS1,115200");
899 strcat(arcs_cmdline, " console=ttyS0,115200");
903 mips_hpt_frequency = octeon_get_clock_rate();
905 octeon_init_cvmcount();
907 _machine_restart = octeon_restart;
908 _machine_halt = octeon_halt;
911 _machine_kexec_shutdown = octeon_shutdown;
912 _machine_crash_shutdown = octeon_crash_shutdown;
913 _machine_kexec_prepare = octeon_kexec_prepare;
916 octeon_user_io_init();
920 /* Exclude a single page from the regions obtained in plat_mem_setup. */
921 #ifndef CONFIG_CRASH_DUMP
922 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
924 if (addr > *mem && addr < *mem + *size) {
925 u64 inc = addr - *mem;
926 add_memory_region(*mem, inc, BOOT_MEM_RAM);
931 if (addr == *mem && *size > PAGE_SIZE) {
936 #endif /* CONFIG_CRASH_DUMP */
938 void __init plat_mem_setup(void)
940 uint64_t mem_alloc_size;
943 #ifndef CONFIG_CRASH_DUMP
945 uint64_t kernel_start;
946 uint64_t kernel_size;
953 * The Mips memory init uses the first memory location for
954 * some memory vectors. When SPARSEMEM is in use, it doesn't
955 * verify that the size is big enough for the final
956 * vectors. Making the smallest chuck 4MB seems to be enough
957 * to consistently work.
959 mem_alloc_size = 4 << 20;
960 if (mem_alloc_size > MAX_MEMORY)
961 mem_alloc_size = MAX_MEMORY;
963 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
964 #ifdef CONFIG_CRASH_DUMP
965 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
969 if (crashk_size > 0) {
970 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
971 crashk_end = crashk_base + crashk_size;
975 * When allocating memory, we want incrementing addresses from
976 * bootmem_alloc so the code in add_memory_region can merge
977 * regions next to each other.
980 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
981 && (total < MAX_MEMORY)) {
982 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
983 __pa_symbol(&_end), -1,
985 CVMX_BOOTMEM_FLAG_NO_LOCKING);
987 u64 size = mem_alloc_size;
993 * exclude a page at the beginning and end of
994 * the 256MB PCIe 'hole' so the kernel will not
995 * try to allocate multi-page buffers that
996 * span the discontinuity.
998 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
1000 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
1001 CVMX_PCIE_BAR1_PHYS_SIZE,
1004 end = memory + mem_alloc_size;
1007 * This function automatically merges address regions
1008 * next to each other if they are received in
1009 * incrementing order
1011 if (memory < crashk_base && end > crashk_end) {
1012 /* region is fully in */
1013 add_memory_region(memory,
1014 crashk_base - memory,
1016 total += crashk_base - memory;
1017 add_memory_region(crashk_end,
1020 total += end - crashk_end;
1024 if (memory >= crashk_base && end <= crashk_end)
1026 * Entire memory region is within the new
1027 * kernel's memory, ignore it.
1031 if (memory > crashk_base && memory < crashk_end &&
1034 * Overlap with the beginning of the region,
1035 * reserve the beginning.
1037 mem_alloc_size -= crashk_end - memory;
1038 memory = crashk_end;
1039 } else if (memory < crashk_base && end > crashk_base &&
1042 * Overlap with the beginning of the region,
1045 mem_alloc_size -= end - crashk_base;
1047 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
1048 total += mem_alloc_size;
1049 /* Recovering mem_alloc_size */
1050 mem_alloc_size = 4 << 20;
1055 cvmx_bootmem_unlock();
1056 /* Add the memory region for the kernel. */
1057 kernel_start = (unsigned long) _text;
1058 kernel_size = _end - _text;
1060 /* Adjust for physical offset. */
1061 kernel_start &= ~0xffffffff80000000ULL;
1062 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
1063 #endif /* CONFIG_CRASH_DUMP */
1065 #ifdef CONFIG_CAVIUM_RESERVE32
1067 * Now that we've allocated the kernel memory it is safe to
1068 * free the reserved region. We free it here so that builtin
1069 * drivers can use the memory.
1071 if (octeon_reserve32_memory)
1072 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
1073 #endif /* CONFIG_CAVIUM_RESERVE32 */
1076 panic("Unable to allocate memory from "
1077 "cvmx_bootmem_phy_alloc");
1081 * Emit one character to the boot UART. Exported for use by the
1084 int prom_putchar(char c)
1088 /* Spin until there is room */
1090 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1091 } while ((lsrval & 0x20) == 0);
1093 /* Write the byte */
1094 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1097 EXPORT_SYMBOL(prom_putchar);
1099 void __init prom_free_prom_memory(void)
1101 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
1102 /* Check for presence of Core-14449 fix. */
1108 asm volatile("# before" : : : "memory");
1112 ".set noreorder\n\t"
1115 "1:\tlw %0,-12($31)\n\t"
1117 : "=r" (insn) : : "$31", "memory");
1119 if ((insn >> 26) != 0x33)
1120 panic("No PREF instruction at Core-14449 probe point.");
1122 if (((insn >> 16) & 0x1f) != 28)
1123 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1124 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1129 void __init octeon_fill_mac_addresses(void);
1130 int octeon_prune_device_tree(void);
1132 extern const char __appended_dtb;
1133 extern const char __dtb_octeon_3xxx_begin;
1134 extern const char __dtb_octeon_68xx_begin;
1135 void __init device_tree_init(void)
1141 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
1142 if (!fdt_check_header(&__appended_dtb)) {
1143 fdt = &__appended_dtb;
1146 pr_info("Using appended Device Tree.\n");
1149 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1150 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1151 if (fdt_check_header(fdt))
1152 panic("Corrupt Device Tree passed to kernel.");
1155 pr_info("Using passed Device Tree.\n");
1156 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1157 fdt = &__dtb_octeon_68xx_begin;
1161 fdt = &__dtb_octeon_3xxx_begin;
1166 initial_boot_params = (void *)fdt;
1169 octeon_prune_device_tree();
1170 pr_info("Using internal Device Tree.\n");
1173 octeon_fill_mac_addresses();
1174 unflatten_and_copy_device_tree();
1175 init_octeon_system_type();
1178 static int __initdata disable_octeon_edac_p;
1180 static int __init disable_octeon_edac(char *str)
1182 disable_octeon_edac_p = 1;
1185 early_param("disable_octeon_edac", disable_octeon_edac);
1187 static char *edac_device_names[] = {
1192 static int __init edac_devinit(void)
1194 struct platform_device *dev;
1199 if (disable_octeon_edac_p)
1202 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1203 name = edac_device_names[i];
1204 dev = platform_device_register_simple(name, -1, NULL, 0);
1206 pr_err("Registration of %s failed!\n", name);
1211 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1212 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1213 for (i = 0; i < num_lmc; i++) {
1214 dev = platform_device_register_simple("octeon_lmc_edac",
1217 pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
1224 device_initcall(edac_devinit);
1226 static void __initdata *octeon_dummy_iospace;
1228 static int __init octeon_no_pci_init(void)
1231 * Initially assume there is no PCI. The PCI/PCIe platform code will
1232 * later re-initialize these to correct values if they are present.
1234 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1235 set_io_port_base((unsigned long)octeon_dummy_iospace);
1236 ioport_resource.start = MAX_RESOURCE;
1237 ioport_resource.end = 0;
1240 core_initcall(octeon_no_pci_init);
1242 static int __init octeon_no_pci_release(void)
1245 * Release the allocated memory if a real IO space is there.
1247 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1248 vfree(octeon_dummy_iospace);
1251 late_initcall(octeon_no_pci_release);