arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_SEGCTL0 $5, 2
  52 #define CP0_SEGCTL1 $5, 3
  53 #define CP0_SEGCTL2 $5, 4
  54 #define CP0_WIRED $6
  55 #define CP0_INFO $7
  56 #define CP0_HWRENA $7
  57 #define CP0_BADVADDR $8
  58 #define CP0_BADINSTR $8, 1
  59 #define CP0_COUNT $9
  60 #define CP0_ENTRYHI $10
  61 #define CP0_GUESTCTL1 $10, 4
  62 #define CP0_GUESTCTL2 $10, 5
  63 #define CP0_GUESTCTL3 $10, 6
  64 #define CP0_COMPARE $11
  65 #define CP0_GUESTCTL0EXT $11, 4
  66 #define CP0_STATUS $12
  67 #define CP0_GUESTCTL0 $12, 6
  68 #define CP0_GTOFFSET $12, 7
  69 #define CP0_CAUSE $13
  70 #define CP0_EPC $14
  71 #define CP0_PRID $15
  72 #define CP0_EBASE $15, 1
  73 #define CP0_CMGCRBASE $15, 3
  74 #define CP0_CONFIG $16
  75 #define CP0_CONFIG3 $16, 3
  76 #define CP0_CONFIG5 $16, 5
  77 #define CP0_LLADDR $17
  78 #define CP0_WATCHLO $18
  79 #define CP0_WATCHHI $19
  80 #define CP0_XCONTEXT $20
  81 #define CP0_FRAMEMASK $21
  82 #define CP0_DIAGNOSTIC $22
  83 #define CP0_DEBUG $23
  84 #define CP0_DEPC $24
  85 #define CP0_PERFORMANCE $25
  86 #define CP0_ECC $26
  87 #define CP0_CACHEERR $27
  88 #define CP0_TAGLO $28
  89 #define CP0_TAGHI $29
  90 #define CP0_ERROREPC $30
  91 #define CP0_DESAVE $31
  92
  93 /*
  94  * R4640/R4650 cp0 register names.  These registers are listed
  95  * here only for completeness; without MMU these CPUs are not useable
  96  * by Linux.  A future ELKS port might take make Linux run on them
  97  * though ...
  98  */
  99 #define CP0_IBASE $0
 100 #define CP0_IBOUND $1
 101 #define CP0_DBASE $2
 102 #define CP0_DBOUND $3
 103 #define CP0_CALG $17
 104 #define CP0_IWATCH $18
 105 #define CP0_DWATCH $19
 106
 107 /*
 108  * Coprocessor 0 Set 1 register names
 109  */
 110 #define CP0_S1_DERRADDR0  $26
 111 #define CP0_S1_DERRADDR1  $27
 112 #define CP0_S1_INTCONTROL $20
 113
 114 /*
 115  * Coprocessor 0 Set 2 register names
 116  */
 117 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 118
 119 /*
 120  * Coprocessor 0 Set 3 register names
 121  */
 122 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 123
 124 /*
 125  *  TX39 Series
 126  */
 127 #define CP0_TX39_CACHE  $7
 128
 129
 130 /* Generic EntryLo bit definitions */
 131 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 132 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 133 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 134 #define ENTRYLO_C_SHIFT         3
 135 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 136
 137 /* R3000 EntryLo bit definitions */
 138 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 139 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 140 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 141 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 142
 143 /* MIPS32/64 EntryLo bit definitions */
 144 #define MIPS_ENTRYLO_PFN_SHIFT  6
 145 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 146 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 147
 148 /*
 149  * Values for PageMask register
 150  */
 151 #ifdef CONFIG_CPU_VR41XX
 152
 153 /* Why doesn't stupidity hurt ... */
 154
 155 #define PM_1K           0x00000000
 156 #define PM_4K           0x00001800
 157 #define PM_16K          0x00007800
 158 #define PM_64K          0x0001f800
 159 #define PM_256K         0x0007f800
 160
 161 #else
 162
 163 #define PM_4K           0x00000000
 164 #define PM_8K           0x00002000
 165 #define PM_16K          0x00006000
 166 #define PM_32K          0x0000e000
 167 #define PM_64K          0x0001e000
 168 #define PM_128K         0x0003e000
 169 #define PM_256K         0x0007e000
 170 #define PM_512K         0x000fe000
 171 #define PM_1M           0x001fe000
 172 #define PM_2M           0x003fe000
 173 #define PM_4M           0x007fe000
 174 #define PM_8M           0x00ffe000
 175 #define PM_16M          0x01ffe000
 176 #define PM_32M          0x03ffe000
 177 #define PM_64M          0x07ffe000
 178 #define PM_256M         0x1fffe000
 179 #define PM_1G           0x7fffe000
 180
 181 #endif
 182
 183 /*
 184  * Default page size for a given kernel configuration
 185  */
 186 #ifdef CONFIG_PAGE_SIZE_4KB
 187 #define PM_DEFAULT_MASK PM_4K
 188 #elif defined(CONFIG_PAGE_SIZE_8KB)
 189 #define PM_DEFAULT_MASK PM_8K
 190 #elif defined(CONFIG_PAGE_SIZE_16KB)
 191 #define PM_DEFAULT_MASK PM_16K
 192 #elif defined(CONFIG_PAGE_SIZE_32KB)
 193 #define PM_DEFAULT_MASK PM_32K
 194 #elif defined(CONFIG_PAGE_SIZE_64KB)
 195 #define PM_DEFAULT_MASK PM_64K
 196 #else
 197 #error Bad page size configuration!
 198 #endif
 199
 200 /*
 201  * Default huge tlb size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_HUGE_MASK    PM_1M
 205 #elif defined(CONFIG_PAGE_SIZE_8KB)
 206 #define PM_HUGE_MASK    PM_4M
 207 #elif defined(CONFIG_PAGE_SIZE_16KB)
 208 #define PM_HUGE_MASK    PM_16M
 209 #elif defined(CONFIG_PAGE_SIZE_32KB)
 210 #define PM_HUGE_MASK    PM_64M
 211 #elif defined(CONFIG_PAGE_SIZE_64KB)
 212 #define PM_HUGE_MASK    PM_256M
 213 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 214 #error Bad page size configuration for hugetlbfs!
 215 #endif
 216
 217 /*
 218  * Values used for computation of new tlb entries
 219  */
 220 #define PL_4K           12
 221 #define PL_16K          14
 222 #define PL_64K          16
 223 #define PL_256K         18
 224 #define PL_1M           20
 225 #define PL_4M           22
 226 #define PL_16M          24
 227 #define PL_64M          26
 228 #define PL_256M         28
 229
 230 /*
 231  * PageGrain bits
 232  */
 233 #define PG_RIE          (_ULCAST_(1) <<  31)
 234 #define PG_XIE          (_ULCAST_(1) <<  30)
 235 #define PG_ELPA         (_ULCAST_(1) <<  29)
 236 #define PG_ESP          (_ULCAST_(1) <<  28)
 237 #define PG_IEC          (_ULCAST_(1) <<  27)
 238
 239 /* MIPS32/64 EntryHI bit definitions */
 240 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 241 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 242 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 243
 244 /*
 245  * R4x00 interrupt enable / cause bits
 246  */
 247 #define IE_SW0          (_ULCAST_(1) <<  8)
 248 #define IE_SW1          (_ULCAST_(1) <<  9)
 249 #define IE_IRQ0         (_ULCAST_(1) << 10)
 250 #define IE_IRQ1         (_ULCAST_(1) << 11)
 251 #define IE_IRQ2         (_ULCAST_(1) << 12)
 252 #define IE_IRQ3         (_ULCAST_(1) << 13)
 253 #define IE_IRQ4         (_ULCAST_(1) << 14)
 254 #define IE_IRQ5         (_ULCAST_(1) << 15)
 255
 256 /*
 257  * R4x00 interrupt cause bits
 258  */
 259 #define C_SW0           (_ULCAST_(1) <<  8)
 260 #define C_SW1           (_ULCAST_(1) <<  9)
 261 #define C_IRQ0          (_ULCAST_(1) << 10)
 262 #define C_IRQ1          (_ULCAST_(1) << 11)
 263 #define C_IRQ2          (_ULCAST_(1) << 12)
 264 #define C_IRQ3          (_ULCAST_(1) << 13)
 265 #define C_IRQ4          (_ULCAST_(1) << 14)
 266 #define C_IRQ5          (_ULCAST_(1) << 15)
 267
 268 /*
 269  * Bitfields in the R4xx0 cp0 status register
 270  */
 271 #define ST0_IE                  0x00000001
 272 #define ST0_EXL                 0x00000002
 273 #define ST0_ERL                 0x00000004
 274 #define ST0_KSU                 0x00000018
 275 #  define KSU_USER              0x00000010
 276 #  define KSU_SUPERVISOR        0x00000008
 277 #  define KSU_KERNEL            0x00000000
 278 #define ST0_UX                  0x00000020
 279 #define ST0_SX                  0x00000040
 280 #define ST0_KX                  0x00000080
 281 #define ST0_DE                  0x00010000
 282 #define ST0_CE                  0x00020000
 283
 284 /*
 285  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 286  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 287  * processors.
 288  */
 289 #define ST0_CO                  0x08000000
 290
 291 /*
 292  * Bitfields in the R[23]000 cp0 status register.
 293  */
 294 #define ST0_IEC                 0x00000001
 295 #define ST0_KUC                 0x00000002
 296 #define ST0_IEP                 0x00000004
 297 #define ST0_KUP                 0x00000008
 298 #define ST0_IEO                 0x00000010
 299 #define ST0_KUO                 0x00000020
 300 /* bits 6 & 7 are reserved on R[23]000 */
 301 #define ST0_ISC                 0x00010000
 302 #define ST0_SWC                 0x00020000
 303 #define ST0_CM                  0x00080000
 304
 305 /*
 306  * Bits specific to the R4640/R4650
 307  */
 308 #define ST0_UM                  (_ULCAST_(1) <<  4)
 309 #define ST0_IL                  (_ULCAST_(1) << 23)
 310 #define ST0_DL                  (_ULCAST_(1) << 24)
 311
 312 /*
 313  * Enable the MIPS MDMX and DSP ASEs
 314  */
 315 #define ST0_MX                  0x01000000
 316
 317 /*
 318  * Status register bits available in all MIPS CPUs.
 319  */
 320 #define ST0_IM                  0x0000ff00
 321 #define  STATUSB_IP0            8
 322 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 323 #define  STATUSB_IP1            9
 324 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 325 #define  STATUSB_IP2            10
 326 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 327 #define  STATUSB_IP3            11
 328 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 329 #define  STATUSB_IP4            12
 330 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 331 #define  STATUSB_IP5            13
 332 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 333 #define  STATUSB_IP6            14
 334 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 335 #define  STATUSB_IP7            15
 336 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 337 #define  STATUSB_IP8            0
 338 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 339 #define  STATUSB_IP9            1
 340 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 341 #define  STATUSB_IP10           2
 342 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 343 #define  STATUSB_IP11           3
 344 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 345 #define  STATUSB_IP12           4
 346 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 347 #define  STATUSB_IP13           5
 348 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 349 #define  STATUSB_IP14           6
 350 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 351 #define  STATUSB_IP15           7
 352 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 353 #define ST0_CH                  0x00040000
 354 #define ST0_NMI                 0x00080000
 355 #define ST0_SR                  0x00100000
 356 #define ST0_TS                  0x00200000
 357 #define ST0_BEV                 0x00400000
 358 #define ST0_RE                  0x02000000
 359 #define ST0_FR                  0x04000000
 360 #define ST0_CU                  0xf0000000
 361 #define ST0_CU0                 0x10000000
 362 #define ST0_CU1                 0x20000000
 363 #define ST0_CU2                 0x40000000
 364 #define ST0_CU3                 0x80000000
 365 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 366
 367 /*
 368  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 369  */
 370 #define INTCTLB_IPFDC           23
 371 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 372 #define INTCTLB_IPPCI           26
 373 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 374 #define INTCTLB_IPTI            29
 375 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 376
 377 /*
 378  * Bitfields and bit numbers in the coprocessor 0 cause register.
 379  *
 380  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 381  */
 382 #define CAUSEB_EXCCODE          2
 383 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 384 #define CAUSEB_IP               8
 385 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 386 #define  CAUSEB_IP0             8
 387 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 388 #define  CAUSEB_IP1             9
 389 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 390 #define  CAUSEB_IP2             10
 391 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 392 #define  CAUSEB_IP3             11
 393 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 394 #define  CAUSEB_IP4             12
 395 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 396 #define  CAUSEB_IP5             13
 397 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 398 #define  CAUSEB_IP6             14
 399 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 400 #define  CAUSEB_IP7             15
 401 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 402 #define CAUSEB_FDCI             21
 403 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 404 #define CAUSEB_WP               22
 405 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 406 #define CAUSEB_IV               23
 407 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 408 #define CAUSEB_PCI              26
 409 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 410 #define CAUSEB_DC               27
 411 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 412 #define CAUSEB_CE               28
 413 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 414 #define CAUSEB_TI               30
 415 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 416 #define CAUSEB_BD               31
 417 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 418
 419 /*
 420  * Cause.ExcCode trap codes.
 421  */
 422 #define EXCCODE_INT             0       /* Interrupt pending */
 423 #define EXCCODE_MOD             1       /* TLB modified fault */
 424 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 425 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 426 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 427 #define EXCCODE_ADES            5       /* Address error on a store */
 428 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 429 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 430 #define EXCCODE_SYS             8       /* System call */
 431 #define EXCCODE_BP              9       /* Breakpoint */
 432 #define EXCCODE_RI              10      /* Reserved instruction exception */
 433 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 434 #define EXCCODE_OV              12      /* Arithmetic overflow */
 435 #define EXCCODE_TR              13      /* Trap instruction */
 436 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 437 #define EXCCODE_FPE             15      /* Floating point exception */
 438 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 439 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 440 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 441 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 442 #define EXCCODE_WATCH           23      /* Watch address reference */
 443 #define EXCCODE_MCHECK          24      /* Machine check */
 444 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 445 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 446 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 447
 448 /* Implementation specific trap codes used by MIPS cores */
 449 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 450
 451 /*
 452  * Bits in the coprocessor 0 config register.
 453  */
 454 /* Generic bits.  */
 455 #define CONF_CM_CACHABLE_NO_WA          0
 456 #define CONF_CM_CACHABLE_WA             1
 457 #define CONF_CM_UNCACHED                2
 458 #define CONF_CM_CACHABLE_NONCOHERENT    3
 459 #define CONF_CM_CACHABLE_CE             4
 460 #define CONF_CM_CACHABLE_COW            5
 461 #define CONF_CM_CACHABLE_CUW            6
 462 #define CONF_CM_CACHABLE_ACCELERATED    7
 463 #define CONF_CM_CMASK                   7
 464 #define CONF_BE                 (_ULCAST_(1) << 15)
 465
 466 /* Bits common to various processors.  */
 467 #define CONF_CU                 (_ULCAST_(1) <<  3)
 468 #define CONF_DB                 (_ULCAST_(1) <<  4)
 469 #define CONF_IB                 (_ULCAST_(1) <<  5)
 470 #define CONF_DC                 (_ULCAST_(7) <<  6)
 471 #define CONF_IC                 (_ULCAST_(7) <<  9)
 472 #define CONF_EB                 (_ULCAST_(1) << 13)
 473 #define CONF_EM                 (_ULCAST_(1) << 14)
 474 #define CONF_SM                 (_ULCAST_(1) << 16)
 475 #define CONF_SC                 (_ULCAST_(1) << 17)
 476 #define CONF_EW                 (_ULCAST_(3) << 18)
 477 #define CONF_EP                 (_ULCAST_(15)<< 24)
 478 #define CONF_EC                 (_ULCAST_(7) << 28)
 479 #define CONF_CM                 (_ULCAST_(1) << 31)
 480
 481 /* Bits specific to the R4xx0.  */
 482 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 483 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 484 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 485
 486 /* Bits specific to the R5000.  */
 487 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 488 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 489
 490 /* Bits specific to the RM7000.  */
 491 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 492 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 493 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 494 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 495 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 496 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 497
 498 /* Bits specific to the R10000.  */
 499 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 500 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 501 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 502 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 503 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 504 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 505 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 506 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 507 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 508 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 509 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 510
 511 /* Bits specific to the VR41xx.  */
 512 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 513 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 514 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 515 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 516 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 517
 518 /* Bits specific to the R30xx.  */
 519 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 520 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 521 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 522 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 523 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 524 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 525 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 526 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 527 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 528
 529 /* Bits specific to the TX49.  */
 530 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 531 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 532 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 533 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 534
 535 /* Bits specific to the MIPS32/64 PRA.  */
 536 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 537 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 538 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 539 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 540 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 541 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 542 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 543
 544 /*
 545  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 546  */
 547 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 548 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 549 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 550 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 551 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 552 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 553 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 554 #define MIPS_CONF1_DA_SHF       7
 555 #define MIPS_CONF1_DA_SZ        3
 556 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 557 #define MIPS_CONF1_DL_SHF       10
 558 #define MIPS_CONF1_DL_SZ        3
 559 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 560 #define MIPS_CONF1_DS_SHF       13
 561 #define MIPS_CONF1_DS_SZ        3
 562 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 563 #define MIPS_CONF1_IA_SHF       16
 564 #define MIPS_CONF1_IA_SZ        3
 565 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 566 #define MIPS_CONF1_IL_SHF       19
 567 #define MIPS_CONF1_IL_SZ        3
 568 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 569 #define MIPS_CONF1_IS_SHF       22
 570 #define MIPS_CONF1_IS_SZ        3
 571 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 572 #define MIPS_CONF1_TLBS_SHIFT   (25)
 573 #define MIPS_CONF1_TLBS_SIZE    (6)
 574 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 575
 576 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 577 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 578 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 579 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 580 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 581 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 582 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 583 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 584
 585 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 586 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 587 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 588 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 589 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 590 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 591 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 592 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 593 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 594 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 595 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 596 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 597 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 598 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 599 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 600 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 601 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 602 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 603 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 604 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 605 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 606 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 607 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 608 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 609 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 610 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 611 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 612
 613 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 614 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 615 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 616 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 617 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 618 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 619 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 620 /* bits 10:8 in FTLB-only configurations */
 621 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 622 /* bits 12:8 in VTLB-FTLB only configurations */
 623 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 624 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 625 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 626 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 627 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 628 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 629 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 630 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 631 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 632 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 633 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 634 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 635
 636 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 637 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 638 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 639 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 640 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 641 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 642 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 643 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 644 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 645 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 646 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 647 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 648
 649 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 650 /* proAptiv FTLB on/off bit */
 651 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 652 /* Loongson-3 FTLB on/off bit */
 653 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 654 /* FTLB probability bits */
 655 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 656
 657 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 658
 659 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 660
 661 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 662 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 663 /* FTLB probability bits for R6 */
 664 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 665
 666 /* WatchLo* register definitions */
 667 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 668
 669 /* WatchHi* register definitions */
 670 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 671 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 672 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 673 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 674 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 675 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 676 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 677 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 678 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 679 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 680 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 681 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 682 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 683
 684 /* MAAR bit definitions */
 685 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 686 #define MIPS_MAAR_ADDR_SHIFT    12
 687 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 688 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 689
 690 /* EBase bit definitions */
 691 #define MIPS_EBASE_CPUNUM_SHIFT 0
 692 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 693 #define MIPS_EBASE_WG_SHIFT     11
 694 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 695 #define MIPS_EBASE_BASE_SHIFT   12
 696 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 697
 698 /* CMGCRBase bit definitions */
 699 #define MIPS_CMGCRB_BASE        11
 700 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 701
 702 /*
 703  * Bits in the MIPS32 Memory Segmentation registers.
 704  */
 705 #define MIPS_SEGCFG_PA_SHIFT    9
 706 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 707 #define MIPS_SEGCFG_AM_SHIFT    4
 708 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 709 #define MIPS_SEGCFG_EU_SHIFT    3
 710 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 711 #define MIPS_SEGCFG_C_SHIFT     0
 712 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 713
 714 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 715 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 716 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 717 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 718 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 719 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 720 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 721
 722 #define MIPS_PWFIELD_GDI_SHIFT  24
 723 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 724 #define MIPS_PWFIELD_UDI_SHIFT  18
 725 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 726 #define MIPS_PWFIELD_MDI_SHIFT  12
 727 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 728 #define MIPS_PWFIELD_PTI_SHIFT  6
 729 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 730 #define MIPS_PWFIELD_PTEI_SHIFT 0
 731 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 732
 733 #define MIPS_PWSIZE_PS_SHIFT    30
 734 #define MIPS_PWSIZE_PS_MASK     0x40000000
 735 #define MIPS_PWSIZE_GDW_SHIFT   24
 736 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 737 #define MIPS_PWSIZE_UDW_SHIFT   18
 738 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 739 #define MIPS_PWSIZE_MDW_SHIFT   12
 740 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 741 #define MIPS_PWSIZE_PTW_SHIFT   6
 742 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 743 #define MIPS_PWSIZE_PTEW_SHIFT  0
 744 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 745
 746 #define MIPS_PWCTL_PWEN_SHIFT   31
 747 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 748 #define MIPS_PWCTL_XK_SHIFT     28
 749 #define MIPS_PWCTL_XK_MASK      0x10000000
 750 #define MIPS_PWCTL_XS_SHIFT     27
 751 #define MIPS_PWCTL_XS_MASK      0x08000000
 752 #define MIPS_PWCTL_XU_SHIFT     26
 753 #define MIPS_PWCTL_XU_MASK      0x04000000
 754 #define MIPS_PWCTL_DPH_SHIFT    7
 755 #define MIPS_PWCTL_DPH_MASK     0x00000080
 756 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 757 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 758 #define MIPS_PWCTL_PSN_SHIFT    0
 759 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 760
 761 /* GuestCtl0 fields */
 762 #define MIPS_GCTL0_GM_SHIFT     31
 763 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 764 #define MIPS_GCTL0_RI_SHIFT     30
 765 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 766 #define MIPS_GCTL0_MC_SHIFT     29
 767 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 768 #define MIPS_GCTL0_CP0_SHIFT    28
 769 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 770 #define MIPS_GCTL0_AT_SHIFT     26
 771 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 772 #define MIPS_GCTL0_GT_SHIFT     25
 773 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 774 #define MIPS_GCTL0_CG_SHIFT     24
 775 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 776 #define MIPS_GCTL0_CF_SHIFT     23
 777 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 778 #define MIPS_GCTL0_G1_SHIFT     22
 779 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 780 #define MIPS_GCTL0_G0E_SHIFT    19
 781 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 782 #define MIPS_GCTL0_PT_SHIFT     18
 783 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 784 #define MIPS_GCTL0_RAD_SHIFT    9
 785 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 786 #define MIPS_GCTL0_DRG_SHIFT    8
 787 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 788 #define MIPS_GCTL0_G2_SHIFT     7
 789 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 790 #define MIPS_GCTL0_GEXC_SHIFT   2
 791 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 792 #define MIPS_GCTL0_SFC2_SHIFT   1
 793 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 794 #define MIPS_GCTL0_SFC1_SHIFT   0
 795 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 796
 797 /* GuestCtl0.AT Guest address translation control */
 798 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 799 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 800
 801 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 802 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 803 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 804 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 805 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 806 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 807 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 808 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 809
 810 /* GuestCtl0Ext fields */
 811 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 812 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 813 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 814 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 815 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 816 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 817 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 818 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 819 #define MIPS_GCTL0EXT_OG_SHIFT  2
 820 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 821 #define MIPS_GCTL0EXT_BG_SHIFT  1
 822 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 823 #define MIPS_GCTL0EXT_MG_SHIFT  0
 824 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 825
 826 /* GuestCtl0Ext.RPW Root page walk configuration */
 827 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 828 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 829 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 830
 831 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 832 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 833 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 834
 835 /* GuestCtl1 fields */
 836 #define MIPS_GCTL1_ID_SHIFT     0
 837 #define MIPS_GCTL1_ID_WIDTH     8
 838 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 839 #define MIPS_GCTL1_RID_SHIFT    16
 840 #define MIPS_GCTL1_RID_WIDTH    8
 841 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 842 #define MIPS_GCTL1_EID_SHIFT    24
 843 #define MIPS_GCTL1_EID_WIDTH    8
 844 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 845
 846 /* GuestID reserved for root context */
 847 #define MIPS_GCTL1_ROOT_GUESTID 0
 848
 849 /* CDMMBase register bit definitions */
 850 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 851 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 852 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 853 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 854 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 855 #define MIPS_CDMMBASE_ADDR_START 15
 856
 857 /* RDHWR register numbers */
 858 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 859 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 860 #define MIPS_HWR_CC             2       /* Cycle counter */
 861 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 862 #define MIPS_HWR_ULR            29      /* UserLocal */
 863 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 864 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 865
 866 /* Bits in HWREna register */
 867 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 868 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 869 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 870 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 871 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 872 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 873 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 874
 875 /*
 876  * Bitfields in the TX39 family CP0 Configuration Register 3
 877  */
 878 #define TX39_CONF_ICS_SHIFT     19
 879 #define TX39_CONF_ICS_MASK      0x00380000
 880 #define TX39_CONF_ICS_1KB       0x00000000
 881 #define TX39_CONF_ICS_2KB       0x00080000
 882 #define TX39_CONF_ICS_4KB       0x00100000
 883 #define TX39_CONF_ICS_8KB       0x00180000
 884 #define TX39_CONF_ICS_16KB      0x00200000
 885
 886 #define TX39_CONF_DCS_SHIFT     16
 887 #define TX39_CONF_DCS_MASK      0x00070000
 888 #define TX39_CONF_DCS_1KB       0x00000000
 889 #define TX39_CONF_DCS_2KB       0x00010000
 890 #define TX39_CONF_DCS_4KB       0x00020000
 891 #define TX39_CONF_DCS_8KB       0x00030000
 892 #define TX39_CONF_DCS_16KB      0x00040000
 893
 894 #define TX39_CONF_CWFON         0x00004000
 895 #define TX39_CONF_WBON          0x00002000
 896 #define TX39_CONF_RF_SHIFT      10
 897 #define TX39_CONF_RF_MASK       0x00000c00
 898 #define TX39_CONF_DOZE          0x00000200
 899 #define TX39_CONF_HALT          0x00000100
 900 #define TX39_CONF_LOCK          0x00000080
 901 #define TX39_CONF_ICE           0x00000020
 902 #define TX39_CONF_DCE           0x00000010
 903 #define TX39_CONF_IRSIZE_SHIFT  2
 904 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 905 #define TX39_CONF_DRSIZE_SHIFT  0
 906 #define TX39_CONF_DRSIZE_MASK   0x00000003
 907
 908 /*
 909  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 910  */
 911 /* Disable Branch Target Address Cache */
 912 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 913 /* Enable Branch Prediction Global History */
 914 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 915 /* Disable Branch Return Cache */
 916 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 917
 918 /* Flush ITLB */
 919 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 920 /* Flush DTLB */
 921 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 922 /* Flush VTLB */
 923 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 924 /* Flush FTLB */
 925 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 926
 927 /*
 928  * Coprocessor 1 (FPU) register names
 929  */
 930 #define CP1_REVISION    $0
 931 #define CP1_UFR         $1
 932 #define CP1_UNFR        $4
 933 #define CP1_FCCR        $25
 934 #define CP1_FEXR        $26
 935 #define CP1_FENR        $28
 936 #define CP1_STATUS      $31
 937
 938
 939 /*
 940  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 941  */
 942 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 943 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 944 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 945 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 946 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 947 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 948 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 949 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 950 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 951 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 952
 953 /*
 954  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 955  */
 956 #define MIPS_FCCR_CONDX_S       0
 957 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 958 #define MIPS_FCCR_COND0_S       0
 959 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 960 #define MIPS_FCCR_COND1_S       1
 961 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 962 #define MIPS_FCCR_COND2_S       2
 963 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 964 #define MIPS_FCCR_COND3_S       3
 965 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 966 #define MIPS_FCCR_COND4_S       4
 967 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 968 #define MIPS_FCCR_COND5_S       5
 969 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 970 #define MIPS_FCCR_COND6_S       6
 971 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 972 #define MIPS_FCCR_COND7_S       7
 973 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 974
 975 /*
 976  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 977  */
 978 #define MIPS_FENR_FS_S          2
 979 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 980
 981 /*
 982  * FPU Status Register Values
 983  */
 984 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 985 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 986
 987 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 988 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 989
 990 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 991 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 992 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 993 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 994 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 995 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 996 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 997 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 998 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 999 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1000 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1001 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1002 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1003 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1004 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1005 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1006
1007 /*
1008  * Bits 22:20 of the FPU Status Register will be read as 0,
1009  * and should be written as zero.
1010  */
1011 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1012
1013 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1014 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1015
1016 /*
1017  * X the exception cause indicator
1018  * E the exception enable
1019  * S the sticky/flag bit
1020 */
1021 #define FPU_CSR_ALL_X   0x0003f000
1022 #define FPU_CSR_UNI_X   0x00020000
1023 #define FPU_CSR_INV_X   0x00010000
1024 #define FPU_CSR_DIV_X   0x00008000
1025 #define FPU_CSR_OVF_X   0x00004000
1026 #define FPU_CSR_UDF_X   0x00002000
1027 #define FPU_CSR_INE_X   0x00001000
1028
1029 #define FPU_CSR_ALL_E   0x00000f80
1030 #define FPU_CSR_INV_E   0x00000800
1031 #define FPU_CSR_DIV_E   0x00000400
1032 #define FPU_CSR_OVF_E   0x00000200
1033 #define FPU_CSR_UDF_E   0x00000100
1034 #define FPU_CSR_INE_E   0x00000080
1035
1036 #define FPU_CSR_ALL_S   0x0000007c
1037 #define FPU_CSR_INV_S   0x00000040
1038 #define FPU_CSR_DIV_S   0x00000020
1039 #define FPU_CSR_OVF_S   0x00000010
1040 #define FPU_CSR_UDF_S   0x00000008
1041 #define FPU_CSR_INE_S   0x00000004
1042
1043 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1044 #define FPU_CSR_RM      0x00000003
1045 #define FPU_CSR_RN      0x0     /* nearest */
1046 #define FPU_CSR_RZ      0x1     /* towards zero */
1047 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1048 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1049
1050
1051 #ifndef __ASSEMBLY__
1052
1053 /*
1054  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1055  */
1056 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1057     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1058 #define get_isa16_mode(x)               ((x) & 0x1)
1059 #define msk_isa16_mode(x)               ((x) & ~0x1)
1060 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1061 #else
1062 #define get_isa16_mode(x)               0
1063 #define msk_isa16_mode(x)               (x)
1064 #define set_isa16_mode(x)               do { } while(0)
1065 #endif
1066
1067 /*
1068  * microMIPS instructions can be 16-bit or 32-bit in length. This
1069  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1070  */
1071 static inline int mm_insn_16bit(u16 insn)
1072 {
1073         u16 opcode = (insn >> 10) & 0x7;
1074
1075         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1076 }
1077
1078 /*
1079  * Helper macros for generating raw instruction encodings in inline asm.
1080  */
1081 #ifdef CONFIG_CPU_MICROMIPS
1082 #define _ASM_INSN16_IF_MM(_enc)                 \
1083         ".insn\n\t"                             \
1084         ".hword (" #_enc ")\n\t"
1085 #define _ASM_INSN32_IF_MM(_enc)                 \
1086         ".insn\n\t"                             \
1087         ".hword ((" #_enc ") >> 16)\n\t"        \
1088         ".hword ((" #_enc ") & 0xffff)\n\t"
1089 #else
1090 #define _ASM_INSN_IF_MIPS(_enc)                 \
1091         ".insn\n\t"                             \
1092         ".word (" #_enc ")\n\t"
1093 #endif
1094
1095 #ifndef _ASM_INSN16_IF_MM
1096 #define _ASM_INSN16_IF_MM(_enc)
1097 #endif
1098 #ifndef _ASM_INSN32_IF_MM
1099 #define _ASM_INSN32_IF_MM(_enc)
1100 #endif
1101 #ifndef _ASM_INSN_IF_MIPS
1102 #define _ASM_INSN_IF_MIPS(_enc)
1103 #endif
1104
1105 /*
1106  * TLB Invalidate Flush
1107  */
1108 static inline void tlbinvf(void)
1109 {
1110         __asm__ __volatile__(
1111                 ".set push\n\t"
1112                 ".set noreorder\n\t"
1113                 "# tlbinvf\n\t"
1114                 _ASM_INSN_IF_MIPS(0x42000004)
1115                 _ASM_INSN32_IF_MM(0x0000537c)
1116                 ".set pop");
1117 }
1118
1119
1120 /*
1121  * Functions to access the R10000 performance counters.  These are basically
1122  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1123  * performance counter number encoded into bits 1 ... 5 of the instruction.
1124  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1125  * disassembler these will look like an access to sel 0 or 1.
1126  */
1127 #define read_r10k_perf_cntr(counter)                            \
1128 ({                                                              \
1129         unsigned int __res;                                     \
1130         __asm__ __volatile__(                                   \
1131         "mfpc\t%0, %1"                                          \
1132         : "=r" (__res)                                          \
1133         : "i" (counter));                                       \
1134                                                                 \
1135         __res;                                                  \
1136 })
1137
1138 #define write_r10k_perf_cntr(counter,val)                       \
1139 do {                                                            \
1140         __asm__ __volatile__(                                   \
1141         "mtpc\t%0, %1"                                          \
1142         :                                                       \
1143         : "r" (val), "i" (counter));                            \
1144 } while (0)
1145
1146 #define read_r10k_perf_event(counter)                           \
1147 ({                                                              \
1148         unsigned int __res;                                     \
1149         __asm__ __volatile__(                                   \
1150         "mfps\t%0, %1"                                          \
1151         : "=r" (__res)                                          \
1152         : "i" (counter));                                       \
1153                                                                 \
1154         __res;                                                  \
1155 })
1156
1157 #define write_r10k_perf_cntl(counter,val)                       \
1158 do {                                                            \
1159         __asm__ __volatile__(                                   \
1160         "mtps\t%0, %1"                                          \
1161         :                                                       \
1162         : "r" (val), "i" (counter));                            \
1163 } while (0)
1164
1165
1166 /*
1167  * Macros to access the system control coprocessor
1168  */
1169
1170 #define __read_32bit_c0_register(source, sel)                           \
1171 ({ unsigned int __res;                                                  \
1172         if (sel == 0)                                                   \
1173                 __asm__ __volatile__(                                   \
1174                         "mfc0\t%0, " #source "\n\t"                     \
1175                         : "=r" (__res));                                \
1176         else                                                            \
1177                 __asm__ __volatile__(                                   \
1178                         ".set\tmips32\n\t"                              \
1179                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1180                         ".set\tmips0\n\t"                               \
1181                         : "=r" (__res));                                \
1182         __res;                                                          \
1183 })
1184
1185 #define __read_64bit_c0_register(source, sel)                           \
1186 ({ unsigned long long __res;                                            \
1187         if (sizeof(unsigned long) == 4)                                 \
1188                 __res = __read_64bit_c0_split(source, sel);             \
1189         else if (sel == 0)                                              \
1190                 __asm__ __volatile__(                                   \
1191                         ".set\tmips3\n\t"                               \
1192                         "dmfc0\t%0, " #source "\n\t"                    \
1193                         ".set\tmips0"                                   \
1194                         : "=r" (__res));                                \
1195         else                                                            \
1196                 __asm__ __volatile__(                                   \
1197                         ".set\tmips64\n\t"                              \
1198                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1199                         ".set\tmips0"                                   \
1200                         : "=r" (__res));                                \
1201         __res;                                                          \
1202 })
1203
1204 #define __write_32bit_c0_register(register, sel, value)                 \
1205 do {                                                                    \
1206         if (sel == 0)                                                   \
1207                 __asm__ __volatile__(                                   \
1208                         "mtc0\t%z0, " #register "\n\t"                  \
1209                         : : "Jr" ((unsigned int)(value)));              \
1210         else                                                            \
1211                 __asm__ __volatile__(                                   \
1212                         ".set\tmips32\n\t"                              \
1213                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1214                         ".set\tmips0"                                   \
1215                         : : "Jr" ((unsigned int)(value)));              \
1216 } while (0)
1217
1218 #define __write_64bit_c0_register(register, sel, value)                 \
1219 do {                                                                    \
1220         if (sizeof(unsigned long) == 4)                                 \
1221                 __write_64bit_c0_split(register, sel, value);           \
1222         else if (sel == 0)                                              \
1223                 __asm__ __volatile__(                                   \
1224                         ".set\tmips3\n\t"                               \
1225                         "dmtc0\t%z0, " #register "\n\t"                 \
1226                         ".set\tmips0"                                   \
1227                         : : "Jr" (value));                              \
1228         else                                                            \
1229                 __asm__ __volatile__(                                   \
1230                         ".set\tmips64\n\t"                              \
1231                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1232                         ".set\tmips0"                                   \
1233                         : : "Jr" (value));                              \
1234 } while (0)
1235
1236 #define __read_ulong_c0_register(reg, sel)                              \
1237         ((sizeof(unsigned long) == 4) ?                                 \
1238         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1239         (unsigned long) __read_64bit_c0_register(reg, sel))
1240
1241 #define __write_ulong_c0_register(reg, sel, val)                        \
1242 do {                                                                    \
1243         if (sizeof(unsigned long) == 4)                                 \
1244                 __write_32bit_c0_register(reg, sel, val);               \
1245         else                                                            \
1246                 __write_64bit_c0_register(reg, sel, val);               \
1247 } while (0)
1248
1249 /*
1250  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1251  */
1252 #define __read_32bit_c0_ctrl_register(source)                           \
1253 ({ unsigned int __res;                                                  \
1254         __asm__ __volatile__(                                           \
1255                 "cfc0\t%0, " #source "\n\t"                             \
1256                 : "=r" (__res));                                        \
1257         __res;                                                          \
1258 })
1259
1260 #define __write_32bit_c0_ctrl_register(register, value)                 \
1261 do {                                                                    \
1262         __asm__ __volatile__(                                           \
1263                 "ctc0\t%z0, " #register "\n\t"                          \
1264                 : : "Jr" ((unsigned int)(value)));                      \
1265 } while (0)
1266
1267 /*
1268  * These versions are only needed for systems with more than 38 bits of
1269  * physical address space running the 32-bit kernel.  That's none atm :-)
1270  */
1271 #define __read_64bit_c0_split(source, sel)                              \
1272 ({                                                                      \
1273         unsigned long long __val;                                       \
1274         unsigned long __flags;                                          \
1275                                                                         \
1276         local_irq_save(__flags);                                        \
1277         if (sel == 0)                                                   \
1278                 __asm__ __volatile__(                                   \
1279                         ".set\tmips64\n\t"                              \
1280                         "dmfc0\t%M0, " #source "\n\t"                   \
1281                         "dsll\t%L0, %M0, 32\n\t"                        \
1282                         "dsra\t%M0, %M0, 32\n\t"                        \
1283                         "dsra\t%L0, %L0, 32\n\t"                        \
1284                         ".set\tmips0"                                   \
1285                         : "=r" (__val));                                \
1286         else                                                            \
1287                 __asm__ __volatile__(                                   \
1288                         ".set\tmips64\n\t"                              \
1289                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1290                         "dsll\t%L0, %M0, 32\n\t"                        \
1291                         "dsra\t%M0, %M0, 32\n\t"                        \
1292                         "dsra\t%L0, %L0, 32\n\t"                        \
1293                         ".set\tmips0"                                   \
1294                         : "=r" (__val));                                \
1295         local_irq_restore(__flags);                                     \
1296                                                                         \
1297         __val;                                                          \
1298 })
1299
1300 #define __write_64bit_c0_split(source, sel, val)                        \
1301 do {                                                                    \
1302         unsigned long __flags;                                          \
1303                                                                         \
1304         local_irq_save(__flags);                                        \
1305         if (sel == 0)                                                   \
1306                 __asm__ __volatile__(                                   \
1307                         ".set\tmips64\n\t"                              \
1308                         "dsll\t%L0, %L0, 32\n\t"                        \
1309                         "dsrl\t%L0, %L0, 32\n\t"                        \
1310                         "dsll\t%M0, %M0, 32\n\t"                        \
1311                         "or\t%L0, %L0, %M0\n\t"                         \
1312                         "dmtc0\t%L0, " #source "\n\t"                   \
1313                         ".set\tmips0"                                   \
1314                         : : "r" (val));                                 \
1315         else                                                            \
1316                 __asm__ __volatile__(                                   \
1317                         ".set\tmips64\n\t"                              \
1318                         "dsll\t%L0, %L0, 32\n\t"                        \
1319                         "dsrl\t%L0, %L0, 32\n\t"                        \
1320                         "dsll\t%M0, %M0, 32\n\t"                        \
1321                         "or\t%L0, %L0, %M0\n\t"                         \
1322                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1323                         ".set\tmips0"                                   \
1324                         : : "r" (val));                                 \
1325         local_irq_restore(__flags);                                     \
1326 } while (0)
1327
1328 #define __readx_32bit_c0_register(source)                               \
1329 ({                                                                      \
1330         unsigned int __res;                                             \
1331                                                                         \
1332         __asm__ __volatile__(                                           \
1333         "       .set    push                                    \n"     \
1334         "       .set    noat                                    \n"     \
1335         "       .set    mips32r2                                \n"     \
1336         "       # mfhc0 $1, %1                                  \n"     \
1337         _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
1338         _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
1339         "       move    %0, $1                                  \n"     \
1340         "       .set    pop                                     \n"     \
1341         : "=r" (__res)                                                  \
1342         : "i" (source));                                                \
1343         __res;                                                          \
1344 })
1345
1346 #define __writex_32bit_c0_register(register, value)                     \
1347 do {                                                                    \
1348         __asm__ __volatile__(                                           \
1349         "       .set    push                                    \n"     \
1350         "       .set    noat                                    \n"     \
1351         "       .set    mips32r2                                \n"     \
1352         "       move    $1, %0                                  \n"     \
1353         "       # mthc0 $1, %1                                  \n"     \
1354         _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
1355         _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
1356         "       .set    pop                                     \n"     \
1357         :                                                               \
1358         : "r" (value), "i" (register));                                 \
1359 } while (0)
1360
1361 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1362 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1363
1364 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1365 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1366
1367 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1368 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1369
1370 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1371 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1372
1373 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1374 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1375
1376 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1377 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1378
1379 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1380 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1381
1382 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1383 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1384
1385 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1386 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1387
1388 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1389 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1390
1391 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1392 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1393
1394 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1395 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1396
1397 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1398 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1399
1400 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1401 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1402
1403 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1404
1405 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1406 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1407
1408 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1409 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1410
1411 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1412 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1413
1414 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1415 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1416
1417 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1418 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1419
1420 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1421 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1422
1423 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1424 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1425
1426 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1427 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1428
1429 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1430 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1431
1432 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1433 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1434
1435 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1436 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1437
1438 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1439 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1440
1441 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1442 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1443
1444 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1445 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1446
1447 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1448
1449 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1450
1451 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1452 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1453
1454 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1455 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1456
1457 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1458 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1459
1460 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1461 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1462
1463 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1464
1465 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1466
1467 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1468 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1469 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1470 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1471 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1472 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1473 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1474 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1475 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1476 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1477 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1478 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1479 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1480 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1481 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1482 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1483
1484 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1485 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1486 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1487 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1488 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1489 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1490
1491 /*
1492  * The WatchLo register.  There may be up to 8 of them.
1493  */
1494 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1495 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1496 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1497 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1498 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1499 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1500 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1501 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1502 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1503 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1504 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1505 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1506 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1507 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1508 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1509 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1510
1511 /*
1512  * The WatchHi register.  There may be up to 8 of them.
1513  */
1514 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1515 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1516 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1517 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1518 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1519 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1520 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1521 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1522
1523 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1524 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1525 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1526 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1527 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1528 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1529 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1530 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1531
1532 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1533 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1534
1535 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1536 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1537
1538 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1539 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1540
1541 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1542 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1543
1544 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1545 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1546 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1547
1548 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1549 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1550
1551 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1552 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1553
1554 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1555 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1556
1557 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1558 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1559
1560 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1561 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1562
1563 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1564 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1565
1566 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1567 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1568
1569 /*
1570  * MIPS32 / MIPS64 performance counters
1571  */
1572 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1573 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1574 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1575 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1576 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1577 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1578 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1579 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1580 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1581 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1582 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1583 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1584 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1585 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1586 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1587 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1588 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1589 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1590 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1591 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1592 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1593 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1594 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1595 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1596
1597 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1598 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1599
1600 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1601 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1602
1603 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1604
1605 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1606 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1607
1608 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1609 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1610
1611 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1612 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1613
1614 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1615 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1616
1617 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1618 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1619
1620 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1621 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1622
1623 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1624 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1625
1626 /* MIPSR2 */
1627 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1628 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1629
1630 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1631 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1632
1633 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1634 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1635
1636 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1637 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1638
1639 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1640 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1641
1642 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1643 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1644
1645 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1646 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1647
1648 /* MIPSR3 */
1649 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1650 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1651
1652 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1653 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1654
1655 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1656 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1657
1658 /* Hardware Page Table Walker */
1659 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1660 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1661
1662 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1663 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1664
1665 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1666 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1667
1668 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1669 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1670
1671 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1672 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1673
1674 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1675 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1676
1677 /* Cavium OCTEON (cnMIPS) */
1678 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1679 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1680
1681 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1682 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1683
1684 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1685 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1686 /*
1687  * The cacheerr registers are not standardized.  On OCTEON, they are
1688  * 64 bits wide.
1689  */
1690 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1691 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1692
1693 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1694 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1695
1696 /* BMIPS3300 */
1697 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1698 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1699
1700 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1701 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1702
1703 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1704 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1705
1706 /* BMIPS43xx */
1707 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1708 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1709
1710 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1711 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1712
1713 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1714 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1715
1716 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1717 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1718
1719 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1720 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1721
1722 /* BMIPS5000 */
1723 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1724 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1725
1726 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1727 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1728
1729 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1730 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1731
1732 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1733 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1734
1735 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1736 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1737
1738 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1739 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1740
1741 /*
1742  * Macros to access the guest system control coprocessor
1743  */
1744
1745 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1746
1747 #define __read_32bit_gc0_register(source, sel)                          \
1748 ({ int __res;                                                           \
1749         __asm__ __volatile__(                                           \
1750                 ".set\tpush\n\t"                                        \
1751                 ".set\tmips32r2\n\t"                                    \
1752                 ".set\tvirt\n\t"                                        \
1753                 "mfgc0\t%0, $%1, %2\n\t"                                \
1754                 ".set\tpop"                                             \
1755                 : "=r" (__res)                                          \
1756                 : "i" (source), "i" (sel));                             \
1757         __res;                                                          \
1758 })
1759
1760 #define __read_64bit_gc0_register(source, sel)                          \
1761 ({ unsigned long long __res;                                            \
1762         __asm__ __volatile__(                                           \
1763                 ".set\tpush\n\t"                                        \
1764                 ".set\tmips64r2\n\t"                                    \
1765                 ".set\tvirt\n\t"                                        \
1766                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1767                 ".set\tpop"                                             \
1768                 : "=r" (__res)                                          \
1769                 : "i" (source), "i" (sel));                             \
1770         __res;                                                          \
1771 })
1772
1773 #define __write_32bit_gc0_register(register, sel, value)                \
1774 do {                                                                    \
1775         __asm__ __volatile__(                                           \
1776                 ".set\tpush\n\t"                                        \
1777                 ".set\tmips32r2\n\t"                                    \
1778                 ".set\tvirt\n\t"                                        \
1779                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1780                 ".set\tpop"                                             \
1781                 : : "Jr" ((unsigned int)(value)),                       \
1782                     "i" (register), "i" (sel));                         \
1783 } while (0)
1784
1785 #define __write_64bit_gc0_register(register, sel, value)                \
1786 do {                                                                    \
1787         __asm__ __volatile__(                                           \
1788                 ".set\tpush\n\t"                                        \
1789                 ".set\tmips64r2\n\t"                                    \
1790                 ".set\tvirt\n\t"                                        \
1791                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1792                 ".set\tpop"                                             \
1793                 : : "Jr" (value),                                       \
1794                     "i" (register), "i" (sel));                         \
1795 } while (0)
1796
1797 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1798
1799 #define __read_32bit_gc0_register(source, sel)                          \
1800 ({ int __res;                                                           \
1801         __asm__ __volatile__(                                           \
1802                 ".set\tpush\n\t"                                        \
1803                 ".set\tnoat\n\t"                                        \
1804                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1805                 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
1806                 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
1807                 "move\t%0, $1\n\t"                                      \
1808                 ".set\tpop"                                             \
1809                 : "=r" (__res)                                          \
1810                 : "i" (source), "i" (sel));                             \
1811         __res;                                                          \
1812 })
1813
1814 #define __read_64bit_gc0_register(source, sel)                          \
1815 ({ unsigned long long __res;                                            \
1816         __asm__ __volatile__(                                           \
1817                 ".set\tpush\n\t"                                        \
1818                 ".set\tnoat\n\t"                                        \
1819                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1820                 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
1821                 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
1822                 "move\t%0, $1\n\t"                                      \
1823                 ".set\tpop"                                             \
1824                 : "=r" (__res)                                          \
1825                 : "i" (source), "i" (sel));                             \
1826         __res;                                                          \
1827 })
1828
1829 #define __write_32bit_gc0_register(register, sel, value)                \
1830 do {                                                                    \
1831         __asm__ __volatile__(                                           \
1832                 ".set\tpush\n\t"                                        \
1833                 ".set\tnoat\n\t"                                        \
1834                 "move\t$1, %z0\n\t"                                     \
1835                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1836                 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
1837                 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
1838                 ".set\tpop"                                             \
1839                 : : "Jr" ((unsigned int)(value)),                       \
1840                     "i" (register), "i" (sel));                         \
1841 } while (0)
1842
1843 #define __write_64bit_gc0_register(register, sel, value)                \
1844 do {                                                                    \
1845         __asm__ __volatile__(                                           \
1846                 ".set\tpush\n\t"                                        \
1847                 ".set\tnoat\n\t"                                        \
1848                 "move\t$1, %z0\n\t"                                     \
1849                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1850                 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
1851                 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
1852                 ".set\tpop"                                             \
1853                 : : "Jr" (value),                                       \
1854                     "i" (register), "i" (sel));                         \
1855 } while (0)
1856
1857 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1858
1859 #define __read_ulong_gc0_register(reg, sel)                             \
1860         ((sizeof(unsigned long) == 4) ?                                 \
1861         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1862         (unsigned long) __read_64bit_gc0_register(reg, sel))
1863
1864 #define __write_ulong_gc0_register(reg, sel, val)                       \
1865 do {                                                                    \
1866         if (sizeof(unsigned long) == 4)                                 \
1867                 __write_32bit_gc0_register(reg, sel, val);              \
1868         else                                                            \
1869                 __write_64bit_gc0_register(reg, sel, val);              \
1870 } while (0)
1871
1872 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1873 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1874
1875 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1876 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1877
1878 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1879 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1880
1881 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1882 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1883
1884 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1885 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1886
1887 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1888 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1889
1890 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1891 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1892
1893 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1894 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1895
1896 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1897 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1898
1899 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1900 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1901
1902 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1903 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1904
1905 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1906 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1907
1908 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1909 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
1910
1911 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
1912 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
1913
1914 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
1915 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
1916
1917 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
1918 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
1919
1920 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
1921 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
1922
1923 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
1924 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
1925
1926 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
1927 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
1928
1929 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
1930 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
1931
1932 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
1933 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
1934
1935 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
1936
1937 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
1938 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
1939
1940 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
1941 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
1942
1943 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
1944 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
1945
1946 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
1947 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
1948
1949 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
1950 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
1951
1952 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
1953 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
1954
1955 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
1956 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
1957
1958 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
1959 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
1960
1961 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
1962 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
1963 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
1964 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
1965 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
1966 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
1967 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
1968 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
1969 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
1970 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
1971 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
1972 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
1973 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
1974 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
1975 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
1976 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
1977
1978 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
1979 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
1980 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
1981 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
1982 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
1983 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
1984 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
1985 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
1986 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
1987 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
1988 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
1989 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
1990 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
1991 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
1992 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
1993 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
1994
1995 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
1996 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
1997 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
1998 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
1999 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
2000 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
2001 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
2002 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
2003 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
2004 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
2005 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
2006 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
2007 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
2008 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
2009 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
2010 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
2011
2012 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
2013 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
2014
2015 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
2016 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
2017 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
2018 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
2019 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
2020 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
2021 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
2022 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
2023 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
2024 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
2025 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
2026 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
2027 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
2028 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
2029 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
2030 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
2031 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
2032 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
2033 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
2034 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
2035 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
2036 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
2037 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
2038 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
2039
2040 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
2041 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
2042
2043 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
2044 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
2045 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
2046 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
2047 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
2048 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
2049 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
2050 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
2051 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
2052 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
2053 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
2054 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
2055
2056 /*
2057  * Macros to access the floating point coprocessor control registers
2058  */
2059 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2060 ({                                                                      \
2061         unsigned int __res;                                             \
2062                                                                         \
2063         __asm__ __volatile__(                                           \
2064         "       .set    push                                    \n"     \
2065         "       .set    reorder                                 \n"     \
2066         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2067         "       # like Octeon.                                  \n"     \
2068         "       .set    mips1                                   \n"     \
2069         "       "STR(gas_hardfloat)"                            \n"     \
2070         "       cfc1    %0,"STR(source)"                        \n"     \
2071         "       .set    pop                                     \n"     \
2072         : "=r" (__res));                                                \
2073         __res;                                                          \
2074 })
2075
2076 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2077 do {                                                                    \
2078         __asm__ __volatile__(                                           \
2079         "       .set    push                                    \n"     \
2080         "       .set    reorder                                 \n"     \
2081         "       "STR(gas_hardfloat)"                            \n"     \
2082         "       ctc1    %0,"STR(dest)"                          \n"     \
2083         "       .set    pop                                     \n"     \
2084         : : "r" (val));                                                 \
2085 } while (0)
2086
2087 #ifdef GAS_HAS_SET_HARDFLOAT
2088 #define read_32bit_cp1_register(source)                                 \
2089         _read_32bit_cp1_register(source, .set hardfloat)
2090 #define write_32bit_cp1_register(dest, val)                             \
2091         _write_32bit_cp1_register(dest, val, .set hardfloat)
2092 #else
2093 #define read_32bit_cp1_register(source)                                 \
2094         _read_32bit_cp1_register(source, )
2095 #define write_32bit_cp1_register(dest, val)                             \
2096         _write_32bit_cp1_register(dest, val, )
2097 #endif
2098
2099 #ifdef HAVE_AS_DSP
2100 #define rddsp(mask)                                                     \
2101 ({                                                                      \
2102         unsigned int __dspctl;                                          \
2103                                                                         \
2104         __asm__ __volatile__(                                           \
2105         "       .set push                                       \n"     \
2106         "       .set dsp                                        \n"     \
2107         "       rddsp   %0, %x1                                 \n"     \
2108         "       .set pop                                        \n"     \
2109         : "=r" (__dspctl)                                               \
2110         : "i" (mask));                                                  \
2111         __dspctl;                                                       \
2112 })
2113
2114 #define wrdsp(val, mask)                                                \
2115 do {                                                                    \
2116         __asm__ __volatile__(                                           \
2117         "       .set push                                       \n"     \
2118         "       .set dsp                                        \n"     \
2119         "       wrdsp   %0, %x1                                 \n"     \
2120         "       .set pop                                        \n"     \
2121         :                                                               \
2122         : "r" (val), "i" (mask));                                       \
2123 } while (0)
2124
2125 #define mflo0()                                                         \
2126 ({                                                                      \
2127         long mflo0;                                                     \
2128         __asm__(                                                        \
2129         "       .set push                                       \n"     \
2130         "       .set dsp                                        \n"     \
2131         "       mflo %0, $ac0                                   \n"     \
2132         "       .set pop                                        \n"     \
2133         : "=r" (mflo0));                                                \
2134         mflo0;                                                          \
2135 })
2136
2137 #define mflo1()                                                         \
2138 ({                                                                      \
2139         long mflo1;                                                     \
2140         __asm__(                                                        \
2141         "       .set push                                       \n"     \
2142         "       .set dsp                                        \n"     \
2143         "       mflo %0, $ac1                                   \n"     \
2144         "       .set pop                                        \n"     \
2145         : "=r" (mflo1));                                                \
2146         mflo1;                                                          \
2147 })
2148
2149 #define mflo2()                                                         \
2150 ({                                                                      \
2151         long mflo2;                                                     \
2152         __asm__(                                                        \
2153         "       .set push                                       \n"     \
2154         "       .set dsp                                        \n"     \
2155         "       mflo %0, $ac2                                   \n"     \
2156         "       .set pop                                        \n"     \
2157         : "=r" (mflo2));                                                \
2158         mflo2;                                                          \
2159 })
2160
2161 #define mflo3()                                                         \
2162 ({                                                                      \
2163         long mflo3;                                                     \
2164         __asm__(                                                        \
2165         "       .set push                                       \n"     \
2166         "       .set dsp                                        \n"     \
2167         "       mflo %0, $ac3                                   \n"     \
2168         "       .set pop                                        \n"     \
2169         : "=r" (mflo3));                                                \
2170         mflo3;                                                          \
2171 })
2172
2173 #define mfhi0()                                                         \
2174 ({                                                                      \
2175         long mfhi0;                                                     \
2176         __asm__(                                                        \
2177         "       .set push                                       \n"     \
2178         "       .set dsp                                        \n"     \
2179         "       mfhi %0, $ac0                                   \n"     \
2180         "       .set pop                                        \n"     \
2181         : "=r" (mfhi0));                                                \
2182         mfhi0;                                                          \
2183 })
2184
2185 #define mfhi1()                                                         \
2186 ({                                                                      \
2187         long mfhi1;                                                     \
2188         __asm__(                                                        \
2189         "       .set push                                       \n"     \
2190         "       .set dsp                                        \n"     \
2191         "       mfhi %0, $ac1                                   \n"     \
2192         "       .set pop                                        \n"     \
2193         : "=r" (mfhi1));                                                \
2194         mfhi1;                                                          \
2195 })
2196
2197 #define mfhi2()                                                         \
2198 ({                                                                      \
2199         long mfhi2;                                                     \
2200         __asm__(                                                        \
2201         "       .set push                                       \n"     \
2202         "       .set dsp                                        \n"     \
2203         "       mfhi %0, $ac2                                   \n"     \
2204         "       .set pop                                        \n"     \
2205         : "=r" (mfhi2));                                                \
2206         mfhi2;                                                          \
2207 })
2208
2209 #define mfhi3()                                                         \
2210 ({                                                                      \
2211         long mfhi3;                                                     \
2212         __asm__(                                                        \
2213         "       .set push                                       \n"     \
2214         "       .set dsp                                        \n"     \
2215         "       mfhi %0, $ac3                                   \n"     \
2216         "       .set pop                                        \n"     \
2217         : "=r" (mfhi3));                                                \
2218         mfhi3;                                                          \
2219 })
2220
2221
2222 #define mtlo0(x)                                                        \
2223 ({                                                                      \
2224         __asm__(                                                        \
2225         "       .set push                                       \n"     \
2226         "       .set dsp                                        \n"     \
2227         "       mtlo %0, $ac0                                   \n"     \
2228         "       .set pop                                        \n"     \
2229         :                                                               \
2230         : "r" (x));                                                     \
2231 })
2232
2233 #define mtlo1(x)                                                        \
2234 ({                                                                      \
2235         __asm__(                                                        \
2236         "       .set push                                       \n"     \
2237         "       .set dsp                                        \n"     \
2238         "       mtlo %0, $ac1                                   \n"     \
2239         "       .set pop                                        \n"     \
2240         :                                                               \
2241         : "r" (x));                                                     \
2242 })
2243
2244 #define mtlo2(x)                                                        \
2245 ({                                                                      \
2246         __asm__(                                                        \
2247         "       .set push                                       \n"     \
2248         "       .set dsp                                        \n"     \
2249         "       mtlo %0, $ac2                                   \n"     \
2250         "       .set pop                                        \n"     \
2251         :                                                               \
2252         : "r" (x));                                                     \
2253 })
2254
2255 #define mtlo3(x)                                                        \
2256 ({                                                                      \
2257         __asm__(                                                        \
2258         "       .set push                                       \n"     \
2259         "       .set dsp                                        \n"     \
2260         "       mtlo %0, $ac3                                   \n"     \
2261         "       .set pop                                        \n"     \
2262         :                                                               \
2263         : "r" (x));                                                     \
2264 })
2265
2266 #define mthi0(x)                                                        \
2267 ({                                                                      \
2268         __asm__(                                                        \
2269         "       .set push                                       \n"     \
2270         "       .set dsp                                        \n"     \
2271         "       mthi %0, $ac0                                   \n"     \
2272         "       .set pop                                        \n"     \
2273         :                                                               \
2274         : "r" (x));                                                     \
2275 })
2276
2277 #define mthi1(x)                                                        \
2278 ({                                                                      \
2279         __asm__(                                                        \
2280         "       .set push                                       \n"     \
2281         "       .set dsp                                        \n"     \
2282         "       mthi %0, $ac1                                   \n"     \
2283         "       .set pop                                        \n"     \
2284         :                                                               \
2285         : "r" (x));                                                     \
2286 })
2287
2288 #define mthi2(x)                                                        \
2289 ({                                                                      \
2290         __asm__(                                                        \
2291         "       .set push                                       \n"     \
2292         "       .set dsp                                        \n"     \
2293         "       mthi %0, $ac2                                   \n"     \
2294         "       .set pop                                        \n"     \
2295         :                                                               \
2296         : "r" (x));                                                     \
2297 })
2298
2299 #define mthi3(x)                                                        \
2300 ({                                                                      \
2301         __asm__(                                                        \
2302         "       .set push                                       \n"     \
2303         "       .set dsp                                        \n"     \
2304         "       mthi %0, $ac3                                   \n"     \
2305         "       .set pop                                        \n"     \
2306         :                                                               \
2307         : "r" (x));                                                     \
2308 })
2309
2310 #else
2311
2312 #define rddsp(mask)                                                     \
2313 ({                                                                      \
2314         unsigned int __res;                                             \
2315                                                                         \
2316         __asm__ __volatile__(                                           \
2317         "       .set    push                                    \n"     \
2318         "       .set    noat                                    \n"     \
2319         "       # rddsp $1, %x1                                 \n"     \
2320         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2321         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2322         "       move    %0, $1                                  \n"     \
2323         "       .set    pop                                     \n"     \
2324         : "=r" (__res)                                                  \
2325         : "i" (mask));                                                  \
2326         __res;                                                          \
2327 })
2328
2329 #define wrdsp(val, mask)                                                \
2330 do {                                                                    \
2331         __asm__ __volatile__(                                           \
2332         "       .set    push                                    \n"     \
2333         "       .set    noat                                    \n"     \
2334         "       move    $1, %0                                  \n"     \
2335         "       # wrdsp $1, %x1                                 \n"     \
2336         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2337         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2338         "       .set    pop                                     \n"     \
2339         :                                                               \
2340         : "r" (val), "i" (mask));                                       \
2341 } while (0)
2342
2343 #define _dsp_mfxxx(ins)                                                 \
2344 ({                                                                      \
2345         unsigned long __treg;                                           \
2346                                                                         \
2347         __asm__ __volatile__(                                           \
2348         "       .set    push                                    \n"     \
2349         "       .set    noat                                    \n"     \
2350         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2351         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2352         "       move    %0, $1                                  \n"     \
2353         "       .set    pop                                     \n"     \
2354         : "=r" (__treg)                                                 \
2355         : "i" (ins));                                                   \
2356         __treg;                                                         \
2357 })
2358
2359 #define _dsp_mtxxx(val, ins)                                            \
2360 do {                                                                    \
2361         __asm__ __volatile__(                                           \
2362         "       .set    push                                    \n"     \
2363         "       .set    noat                                    \n"     \
2364         "       move    $1, %0                                  \n"     \
2365         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2366         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2367         "       .set    pop                                     \n"     \
2368         :                                                               \
2369         : "r" (val), "i" (ins));                                        \
2370 } while (0)
2371
2372 #ifdef CONFIG_CPU_MICROMIPS
2373
2374 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2375 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2376
2377 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2378 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2379
2380 #else  /* !CONFIG_CPU_MICROMIPS */
2381
2382 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2383 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2384
2385 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2386 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2387
2388 #endif /* CONFIG_CPU_MICROMIPS */
2389
2390 #define mflo0() _dsp_mflo(0)
2391 #define mflo1() _dsp_mflo(1)
2392 #define mflo2() _dsp_mflo(2)
2393 #define mflo3() _dsp_mflo(3)
2394
2395 #define mfhi0() _dsp_mfhi(0)
2396 #define mfhi1() _dsp_mfhi(1)
2397 #define mfhi2() _dsp_mfhi(2)
2398 #define mfhi3() _dsp_mfhi(3)
2399
2400 #define mtlo0(x) _dsp_mtlo(x, 0)
2401 #define mtlo1(x) _dsp_mtlo(x, 1)
2402 #define mtlo2(x) _dsp_mtlo(x, 2)
2403 #define mtlo3(x) _dsp_mtlo(x, 3)
2404
2405 #define mthi0(x) _dsp_mthi(x, 0)
2406 #define mthi1(x) _dsp_mthi(x, 1)
2407 #define mthi2(x) _dsp_mthi(x, 2)
2408 #define mthi3(x) _dsp_mthi(x, 3)
2409
2410 #endif
2411
2412 /*
2413  * TLB operations.
2414  *
2415  * It is responsibility of the caller to take care of any TLB hazards.
2416  */
2417 static inline void tlb_probe(void)
2418 {
2419         __asm__ __volatile__(
2420                 ".set noreorder\n\t"
2421                 "tlbp\n\t"
2422                 ".set reorder");
2423 }
2424
2425 static inline void tlb_read(void)
2426 {
2427 #if MIPS34K_MISSED_ITLB_WAR
2428         int res = 0;
2429
2430         __asm__ __volatile__(
2431         "       .set    push                                    \n"
2432         "       .set    noreorder                               \n"
2433         "       .set    noat                                    \n"
2434         "       .set    mips32r2                                \n"
2435         "       .word   0x41610001              # dvpe $1       \n"
2436         "       move    %0, $1                                  \n"
2437         "       ehb                                             \n"
2438         "       .set    pop                                     \n"
2439         : "=r" (res));
2440
2441         instruction_hazard();
2442 #endif
2443
2444         __asm__ __volatile__(
2445                 ".set noreorder\n\t"
2446                 "tlbr\n\t"
2447                 ".set reorder");
2448
2449 #if MIPS34K_MISSED_ITLB_WAR
2450         if ((res & _ULCAST_(1)))
2451                 __asm__ __volatile__(
2452                 "       .set    push                            \n"
2453                 "       .set    noreorder                       \n"
2454                 "       .set    noat                            \n"
2455                 "       .set    mips32r2                        \n"
2456                 "       .word   0x41600021      # evpe          \n"
2457                 "       ehb                                     \n"
2458                 "       .set    pop                             \n");
2459 #endif
2460 }
2461
2462 static inline void tlb_write_indexed(void)
2463 {
2464         __asm__ __volatile__(
2465                 ".set noreorder\n\t"
2466                 "tlbwi\n\t"
2467                 ".set reorder");
2468 }
2469
2470 static inline void tlb_write_random(void)
2471 {
2472         __asm__ __volatile__(
2473                 ".set noreorder\n\t"
2474                 "tlbwr\n\t"
2475                 ".set reorder");
2476 }
2477
2478 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2479
2480 /*
2481  * Guest TLB operations.
2482  *
2483  * It is responsibility of the caller to take care of any TLB hazards.
2484  */
2485 static inline void guest_tlb_probe(void)
2486 {
2487         __asm__ __volatile__(
2488                 ".set push\n\t"
2489                 ".set noreorder\n\t"
2490                 ".set virt\n\t"
2491                 "tlbgp\n\t"
2492                 ".set pop");
2493 }
2494
2495 static inline void guest_tlb_read(void)
2496 {
2497         __asm__ __volatile__(
2498                 ".set push\n\t"
2499                 ".set noreorder\n\t"
2500                 ".set virt\n\t"
2501                 "tlbgr\n\t"
2502                 ".set pop");
2503 }
2504
2505 static inline void guest_tlb_write_indexed(void)
2506 {
2507         __asm__ __volatile__(
2508                 ".set push\n\t"
2509                 ".set noreorder\n\t"
2510                 ".set virt\n\t"
2511                 "tlbgwi\n\t"
2512                 ".set pop");
2513 }
2514
2515 static inline void guest_tlb_write_random(void)
2516 {
2517         __asm__ __volatile__(
2518                 ".set push\n\t"
2519                 ".set noreorder\n\t"
2520                 ".set virt\n\t"
2521                 "tlbgwr\n\t"
2522                 ".set pop");
2523 }
2524
2525 /*
2526  * Guest TLB Invalidate Flush
2527  */
2528 static inline void guest_tlbinvf(void)
2529 {
2530         __asm__ __volatile__(
2531                 ".set push\n\t"
2532                 ".set noreorder\n\t"
2533                 ".set virt\n\t"
2534                 "tlbginvf\n\t"
2535                 ".set pop");
2536 }
2537
2538 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2539
2540 /*
2541  * Guest TLB operations.
2542  *
2543  * It is responsibility of the caller to take care of any TLB hazards.
2544  */
2545 static inline void guest_tlb_probe(void)
2546 {
2547         __asm__ __volatile__(
2548                 "# tlbgp\n\t"
2549                 _ASM_INSN_IF_MIPS(0x42000010)
2550                 _ASM_INSN32_IF_MM(0x0000017c));
2551 }
2552
2553 static inline void guest_tlb_read(void)
2554 {
2555         __asm__ __volatile__(
2556                 "# tlbgr\n\t"
2557                 _ASM_INSN_IF_MIPS(0x42000009)
2558                 _ASM_INSN32_IF_MM(0x0000117c));
2559 }
2560
2561 static inline void guest_tlb_write_indexed(void)
2562 {
2563         __asm__ __volatile__(
2564                 "# tlbgwi\n\t"
2565                 _ASM_INSN_IF_MIPS(0x4200000a)
2566                 _ASM_INSN32_IF_MM(0x0000217c));
2567 }
2568
2569 static inline void guest_tlb_write_random(void)
2570 {
2571         __asm__ __volatile__(
2572                 "# tlbgwr\n\t"
2573                 _ASM_INSN_IF_MIPS(0x4200000e)
2574                 _ASM_INSN32_IF_MM(0x0000317c));
2575 }
2576
2577 /*
2578  * Guest TLB Invalidate Flush
2579  */
2580 static inline void guest_tlbinvf(void)
2581 {
2582         __asm__ __volatile__(
2583                 "# tlbginvf\n\t"
2584                 _ASM_INSN_IF_MIPS(0x4200000c)
2585                 _ASM_INSN32_IF_MM(0x0000517c));
2586 }
2587
2588 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2589
2590 /*
2591  * Manipulate bits in a register.
2592  */
2593 #define __BUILD_SET_COMMON(name)                                \
2594 static inline unsigned int                                      \
2595 set_##name(unsigned int set)                                    \
2596 {                                                               \
2597         unsigned int res, new;                                  \
2598                                                                 \
2599         res = read_##name();                                    \
2600         new = res | set;                                        \
2601         write_##name(new);                                      \
2602                                                                 \
2603         return res;                                             \
2604 }                                                               \
2605                                                                 \
2606 static inline unsigned int                                      \
2607 clear_##name(unsigned int clear)                                \
2608 {                                                               \
2609         unsigned int res, new;                                  \
2610                                                                 \
2611         res = read_##name();                                    \
2612         new = res & ~clear;                                     \
2613         write_##name(new);                                      \
2614                                                                 \
2615         return res;                                             \
2616 }                                                               \
2617                                                                 \
2618 static inline unsigned int                                      \
2619 change_##name(unsigned int change, unsigned int val)            \
2620 {                                                               \
2621         unsigned int res, new;                                  \
2622                                                                 \
2623         res = read_##name();                                    \
2624         new = res & ~change;                                    \
2625         new |= (val & change);                                  \
2626         write_##name(new);                                      \
2627                                                                 \
2628         return res;                                             \
2629 }
2630
2631 /*
2632  * Manipulate bits in a c0 register.
2633  */
2634 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2635
2636 __BUILD_SET_C0(status)
2637 __BUILD_SET_C0(cause)
2638 __BUILD_SET_C0(config)
2639 __BUILD_SET_C0(config5)
2640 __BUILD_SET_C0(intcontrol)
2641 __BUILD_SET_C0(intctl)
2642 __BUILD_SET_C0(srsmap)
2643 __BUILD_SET_C0(pagegrain)
2644 __BUILD_SET_C0(guestctl0)
2645 __BUILD_SET_C0(guestctl0ext)
2646 __BUILD_SET_C0(guestctl1)
2647 __BUILD_SET_C0(guestctl2)
2648 __BUILD_SET_C0(guestctl3)
2649 __BUILD_SET_C0(brcm_config_0)
2650 __BUILD_SET_C0(brcm_bus_pll)
2651 __BUILD_SET_C0(brcm_reset)
2652 __BUILD_SET_C0(brcm_cmt_intr)
2653 __BUILD_SET_C0(brcm_cmt_ctrl)
2654 __BUILD_SET_C0(brcm_config)
2655 __BUILD_SET_C0(brcm_mode)
2656
2657 /*
2658  * Manipulate bits in a guest c0 register.
2659  */
2660 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2661
2662 __BUILD_SET_GC0(status)
2663 __BUILD_SET_GC0(cause)
2664 __BUILD_SET_GC0(ebase)
2665
2666 /*
2667  * Return low 10 bits of ebase.
2668  * Note that under KVM (MIPSVZ) this returns vcpu id.
2669  */
2670 static inline unsigned int get_ebase_cpunum(void)
2671 {
2672         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2673 }
2674
2675 #endif /* !__ASSEMBLY__ */
2676
2677 #endif /* _ASM_MIPSREGS_H */