2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
28 #include <asm/watch.h>
30 #include <asm/spram.h>
31 #include <asm/uaccess.h>
33 static int mips_fpu_disabled;
35 static int __init fpu_disable(char *s)
37 cpu_data[0].options &= ~MIPS_CPU_FPU;
38 mips_fpu_disabled = 1;
43 __setup("nofpu", fpu_disable);
45 int mips_dsp_disabled;
47 static int __init dsp_disable(char *s)
49 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
50 mips_dsp_disabled = 1;
55 __setup("nodsp", dsp_disable);
57 static inline void check_errata(void)
59 struct cpuinfo_mips *c = ¤t_cpu_data;
61 switch (current_cpu_type()) {
64 * Erratum "RPS May Cause Incorrect Instruction Execution"
65 * This code only handles VPE0, any SMP/RTOS code
66 * making use of VPE1 will be responsable for that VPE.
68 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
69 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
76 void __init check_bugs32(void)
82 * Probe whether cpu has config register by trying to play with
83 * alternate cache bit and see whether it matters.
84 * It's used by cpu_probe to distinguish between R3000A and R3081.
86 static inline int cpu_has_confreg(void)
88 #ifdef CONFIG_CPU_R3000
89 extern unsigned long r3k_cache_size(unsigned long);
90 unsigned long size1, size2;
91 unsigned long cfg = read_c0_conf();
93 size1 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg ^ R30XX_CONF_AC);
95 size2 = r3k_cache_size(ST0_ISC);
97 return size1 != size2;
103 static inline void set_elf_platform(int cpu, const char *plat)
106 __elf_platform = plat;
110 * Get the FPU Implementation/Revision.
112 static inline unsigned long cpu_get_fpu_id(void)
114 unsigned long tmp, fpu_id;
116 tmp = read_c0_status();
117 __enable_fpu(FPU_AS_IS);
118 fpu_id = read_32bit_cp1_register(CP1_REVISION);
119 write_c0_status(tmp);
124 * Check the CPU has an FPU the official way.
126 static inline int __cpu_has_fpu(void)
128 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
131 static inline unsigned long cpu_get_msa_id(void)
133 unsigned long status, conf5, msa_id;
135 status = read_c0_status();
136 __enable_fpu(FPU_64BIT);
137 conf5 = read_c0_config5();
139 msa_id = read_msa_ir();
140 write_c0_config5(conf5);
141 write_c0_status(status);
145 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
147 #ifdef __NEED_VMBITS_PROBE
148 write_c0_entryhi(0x3fffffffffffe000ULL);
149 back_to_back_c0_hazard();
150 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
154 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
157 case MIPS_CPU_ISA_M64R2:
158 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
159 case MIPS_CPU_ISA_M64R1:
160 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
162 c->isa_level |= MIPS_CPU_ISA_V;
163 case MIPS_CPU_ISA_IV:
164 c->isa_level |= MIPS_CPU_ISA_IV;
165 case MIPS_CPU_ISA_III:
166 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
169 case MIPS_CPU_ISA_M32R2:
170 c->isa_level |= MIPS_CPU_ISA_M32R2;
171 case MIPS_CPU_ISA_M32R1:
172 c->isa_level |= MIPS_CPU_ISA_M32R1;
173 case MIPS_CPU_ISA_II:
174 c->isa_level |= MIPS_CPU_ISA_II;
179 static char unknown_isa[] = KERN_ERR \
180 "Unsupported ISA type, c0.config0: %d.";
182 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
184 unsigned int config6;
186 /* It's implementation dependent how the FTLB can be enabled */
187 switch (c->cputype) {
190 /* proAptiv & related cores use Config6 to enable the FTLB */
191 config6 = read_c0_config6();
194 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
197 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
198 back_to_back_c0_hazard();
203 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
205 unsigned int config0;
208 config0 = read_c0_config();
211 * Look for Standard TLB or Dual VTLB and FTLB
213 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
214 (((config0 & MIPS_CONF_MT) >> 7) == 4))
215 c->options |= MIPS_CPU_TLB;
217 isa = (config0 & MIPS_CONF_AT) >> 13;
220 switch ((config0 & MIPS_CONF_AR) >> 10) {
222 set_isa(c, MIPS_CPU_ISA_M32R1);
225 set_isa(c, MIPS_CPU_ISA_M32R2);
232 switch ((config0 & MIPS_CONF_AR) >> 10) {
234 set_isa(c, MIPS_CPU_ISA_M64R1);
237 set_isa(c, MIPS_CPU_ISA_M64R2);
247 return config0 & MIPS_CONF_M;
250 panic(unknown_isa, config0);
253 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
255 unsigned int config1;
257 config1 = read_c0_config1();
259 if (config1 & MIPS_CONF1_MD)
260 c->ases |= MIPS_ASE_MDMX;
261 if (config1 & MIPS_CONF1_WR)
262 c->options |= MIPS_CPU_WATCH;
263 if (config1 & MIPS_CONF1_CA)
264 c->ases |= MIPS_ASE_MIPS16;
265 if (config1 & MIPS_CONF1_EP)
266 c->options |= MIPS_CPU_EJTAG;
267 if (config1 & MIPS_CONF1_FP) {
268 c->options |= MIPS_CPU_FPU;
269 c->options |= MIPS_CPU_32FPR;
272 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
273 c->tlbsizevtlb = c->tlbsize;
274 c->tlbsizeftlbsets = 0;
277 return config1 & MIPS_CONF_M;
280 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
282 unsigned int config2;
284 config2 = read_c0_config2();
286 if (config2 & MIPS_CONF2_SL)
287 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
289 return config2 & MIPS_CONF_M;
292 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
294 unsigned int config3;
296 config3 = read_c0_config3();
298 if (config3 & MIPS_CONF3_SM) {
299 c->ases |= MIPS_ASE_SMARTMIPS;
300 c->options |= MIPS_CPU_RIXI;
302 if (config3 & MIPS_CONF3_RXI)
303 c->options |= MIPS_CPU_RIXI;
304 if (config3 & MIPS_CONF3_DSP)
305 c->ases |= MIPS_ASE_DSP;
306 if (config3 & MIPS_CONF3_DSP2P)
307 c->ases |= MIPS_ASE_DSP2P;
308 if (config3 & MIPS_CONF3_VINT)
309 c->options |= MIPS_CPU_VINT;
310 if (config3 & MIPS_CONF3_VEIC)
311 c->options |= MIPS_CPU_VEIC;
312 if (config3 & MIPS_CONF3_MT)
313 c->ases |= MIPS_ASE_MIPSMT;
314 if (config3 & MIPS_CONF3_ULRI)
315 c->options |= MIPS_CPU_ULRI;
316 if (config3 & MIPS_CONF3_ISA)
317 c->options |= MIPS_CPU_MICROMIPS;
318 if (config3 & MIPS_CONF3_VZ)
319 c->ases |= MIPS_ASE_VZ;
320 if (config3 & MIPS_CONF3_SC)
321 c->options |= MIPS_CPU_SEGMENTS;
322 if (config3 & MIPS_CONF3_MSA)
323 c->ases |= MIPS_ASE_MSA;
325 return config3 & MIPS_CONF_M;
328 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
330 unsigned int config4;
332 unsigned int mmuextdef;
333 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
335 config4 = read_c0_config4();
338 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
339 c->options |= MIPS_CPU_TLBINV;
340 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
342 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
343 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
344 c->tlbsizevtlb = c->tlbsize;
346 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
348 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
349 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
350 c->tlbsize = c->tlbsizevtlb;
351 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
353 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
354 newcf4 = (config4 & ~ftlb_page) |
355 (page_size_ftlb(mmuextdef) <<
356 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
357 write_c0_config4(newcf4);
358 back_to_back_c0_hazard();
359 config4 = read_c0_config4();
360 if (config4 != newcf4) {
361 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
363 /* Switch FTLB off */
364 set_ftlb_enable(c, 0);
367 c->tlbsizeftlbsets = 1 <<
368 ((config4 & MIPS_CONF4_FTLBSETS) >>
369 MIPS_CONF4_FTLBSETS_SHIFT);
370 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
371 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
372 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
377 c->kscratch_mask = (config4 >> 16) & 0xff;
379 return config4 & MIPS_CONF_M;
382 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
384 unsigned int config5;
386 config5 = read_c0_config5();
387 config5 &= ~MIPS_CONF5_UFR;
388 write_c0_config5(config5);
390 if (config5 & MIPS_CONF5_EVA)
391 c->options |= MIPS_CPU_EVA;
393 return config5 & MIPS_CONF_M;
396 static void decode_configs(struct cpuinfo_mips *c)
400 /* MIPS32 or MIPS64 compliant CPU. */
401 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
402 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
404 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
406 /* Enable FTLB if present */
407 set_ftlb_enable(c, 1);
409 ok = decode_config0(c); /* Read Config registers. */
410 BUG_ON(!ok); /* Arch spec violation! */
412 ok = decode_config1(c);
414 ok = decode_config2(c);
416 ok = decode_config3(c);
418 ok = decode_config4(c);
420 ok = decode_config5(c);
422 mips_probe_watch_registers(c);
424 #ifndef CONFIG_MIPS_CPS
425 if (cpu_has_mips_r2) {
426 c->core = get_ebase_cpunum();
428 c->core >>= fls(core_nvpes()) - 1;
433 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
436 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
438 switch (c->processor_id & PRID_IMP_MASK) {
440 c->cputype = CPU_R2000;
441 __cpu_name[cpu] = "R2000";
442 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
445 c->options |= MIPS_CPU_FPU;
449 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
450 if (cpu_has_confreg()) {
451 c->cputype = CPU_R3081E;
452 __cpu_name[cpu] = "R3081";
454 c->cputype = CPU_R3000A;
455 __cpu_name[cpu] = "R3000A";
458 c->cputype = CPU_R3000;
459 __cpu_name[cpu] = "R3000";
461 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
464 c->options |= MIPS_CPU_FPU;
468 if (read_c0_config() & CONF_SC) {
469 if ((c->processor_id & PRID_REV_MASK) >=
471 c->cputype = CPU_R4400PC;
472 __cpu_name[cpu] = "R4400PC";
474 c->cputype = CPU_R4000PC;
475 __cpu_name[cpu] = "R4000PC";
478 int cca = read_c0_config() & CONF_CM_CMASK;
482 * SC and MC versions can't be reliably told apart,
483 * but only the latter support coherent caching
484 * modes so assume the firmware has set the KSEG0
485 * coherency attribute reasonably (if uncached, we
489 case CONF_CM_CACHABLE_CE:
490 case CONF_CM_CACHABLE_COW:
491 case CONF_CM_CACHABLE_CUW:
498 if ((c->processor_id & PRID_REV_MASK) >=
500 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
501 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
503 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
504 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
508 set_isa(c, MIPS_CPU_ISA_III);
509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
510 MIPS_CPU_WATCH | MIPS_CPU_VCE |
514 case PRID_IMP_VR41XX:
515 set_isa(c, MIPS_CPU_ISA_III);
516 c->options = R4K_OPTS;
518 switch (c->processor_id & 0xf0) {
519 case PRID_REV_VR4111:
520 c->cputype = CPU_VR4111;
521 __cpu_name[cpu] = "NEC VR4111";
523 case PRID_REV_VR4121:
524 c->cputype = CPU_VR4121;
525 __cpu_name[cpu] = "NEC VR4121";
527 case PRID_REV_VR4122:
528 if ((c->processor_id & 0xf) < 0x3) {
529 c->cputype = CPU_VR4122;
530 __cpu_name[cpu] = "NEC VR4122";
532 c->cputype = CPU_VR4181A;
533 __cpu_name[cpu] = "NEC VR4181A";
536 case PRID_REV_VR4130:
537 if ((c->processor_id & 0xf) < 0x4) {
538 c->cputype = CPU_VR4131;
539 __cpu_name[cpu] = "NEC VR4131";
541 c->cputype = CPU_VR4133;
542 c->options |= MIPS_CPU_LLSC;
543 __cpu_name[cpu] = "NEC VR4133";
547 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
548 c->cputype = CPU_VR41XX;
549 __cpu_name[cpu] = "NEC Vr41xx";
554 c->cputype = CPU_R4300;
555 __cpu_name[cpu] = "R4300";
556 set_isa(c, MIPS_CPU_ISA_III);
557 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 c->cputype = CPU_R4600;
563 __cpu_name[cpu] = "R4600";
564 set_isa(c, MIPS_CPU_ISA_III);
565 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
572 * This processor doesn't have an MMU, so it's not
573 * "real easy" to run Linux on it. It is left purely
574 * for documentation. Commented out because it shares
575 * it's c0_prid id number with the TX3900.
577 c->cputype = CPU_R4650;
578 __cpu_name[cpu] = "R4650";
579 set_isa(c, MIPS_CPU_ISA_III);
580 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
585 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
587 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
588 c->cputype = CPU_TX3927;
589 __cpu_name[cpu] = "TX3927";
592 switch (c->processor_id & PRID_REV_MASK) {
593 case PRID_REV_TX3912:
594 c->cputype = CPU_TX3912;
595 __cpu_name[cpu] = "TX3912";
598 case PRID_REV_TX3922:
599 c->cputype = CPU_TX3922;
600 __cpu_name[cpu] = "TX3922";
607 c->cputype = CPU_R4700;
608 __cpu_name[cpu] = "R4700";
609 set_isa(c, MIPS_CPU_ISA_III);
610 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
615 c->cputype = CPU_TX49XX;
616 __cpu_name[cpu] = "R49XX";
617 set_isa(c, MIPS_CPU_ISA_III);
618 c->options = R4K_OPTS | MIPS_CPU_LLSC;
619 if (!(c->processor_id & 0x08))
620 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
624 c->cputype = CPU_R5000;
625 __cpu_name[cpu] = "R5000";
626 set_isa(c, MIPS_CPU_ISA_IV);
627 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
632 c->cputype = CPU_R5432;
633 __cpu_name[cpu] = "R5432";
634 set_isa(c, MIPS_CPU_ISA_IV);
635 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
636 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
640 c->cputype = CPU_R5500;
641 __cpu_name[cpu] = "R5500";
642 set_isa(c, MIPS_CPU_ISA_IV);
643 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
644 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
647 case PRID_IMP_NEVADA:
648 c->cputype = CPU_NEVADA;
649 __cpu_name[cpu] = "Nevada";
650 set_isa(c, MIPS_CPU_ISA_IV);
651 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
656 c->cputype = CPU_R6000;
657 __cpu_name[cpu] = "R6000";
658 set_isa(c, MIPS_CPU_ISA_II);
659 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
663 case PRID_IMP_R6000A:
664 c->cputype = CPU_R6000A;
665 __cpu_name[cpu] = "R6000A";
666 set_isa(c, MIPS_CPU_ISA_II);
667 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
671 case PRID_IMP_RM7000:
672 c->cputype = CPU_RM7000;
673 __cpu_name[cpu] = "RM7000";
674 set_isa(c, MIPS_CPU_ISA_IV);
675 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
678 * Undocumented RM7000: Bit 29 in the info register of
679 * the RM7000 v2.0 indicates if the TLB has 48 or 64
682 * 29 1 => 64 entry JTLB
685 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
688 c->cputype = CPU_R8000;
689 __cpu_name[cpu] = "RM8000";
690 set_isa(c, MIPS_CPU_ISA_IV);
691 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
692 MIPS_CPU_FPU | MIPS_CPU_32FPR |
694 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
696 case PRID_IMP_R10000:
697 c->cputype = CPU_R10000;
698 __cpu_name[cpu] = "R10000";
699 set_isa(c, MIPS_CPU_ISA_IV);
700 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
701 MIPS_CPU_FPU | MIPS_CPU_32FPR |
702 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
706 case PRID_IMP_R12000:
707 c->cputype = CPU_R12000;
708 __cpu_name[cpu] = "R12000";
709 set_isa(c, MIPS_CPU_ISA_IV);
710 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
711 MIPS_CPU_FPU | MIPS_CPU_32FPR |
712 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
716 case PRID_IMP_R14000:
717 c->cputype = CPU_R14000;
718 __cpu_name[cpu] = "R14000";
719 set_isa(c, MIPS_CPU_ISA_IV);
720 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
721 MIPS_CPU_FPU | MIPS_CPU_32FPR |
722 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
726 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
727 switch (c->processor_id & PRID_REV_MASK) {
728 case PRID_REV_LOONGSON2E:
729 c->cputype = CPU_LOONGSON2;
730 __cpu_name[cpu] = "ICT Loongson-2";
731 set_elf_platform(cpu, "loongson2e");
733 case PRID_REV_LOONGSON2F:
734 c->cputype = CPU_LOONGSON2;
735 __cpu_name[cpu] = "ICT Loongson-2";
736 set_elf_platform(cpu, "loongson2f");
738 case PRID_REV_LOONGSON3A:
739 c->cputype = CPU_LOONGSON3;
740 __cpu_name[cpu] = "ICT Loongson-3";
741 set_elf_platform(cpu, "loongson3a");
745 set_isa(c, MIPS_CPU_ISA_III);
746 c->options = R4K_OPTS |
747 MIPS_CPU_FPU | MIPS_CPU_LLSC |
751 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
754 c->cputype = CPU_LOONGSON1;
756 switch (c->processor_id & PRID_REV_MASK) {
757 case PRID_REV_LOONGSON1B:
758 __cpu_name[cpu] = "Loongson 1B";
766 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
768 switch (c->processor_id & PRID_IMP_MASK) {
770 c->cputype = CPU_4KC;
771 __cpu_name[cpu] = "MIPS 4Kc";
774 case PRID_IMP_4KECR2:
775 c->cputype = CPU_4KEC;
776 __cpu_name[cpu] = "MIPS 4KEc";
780 c->cputype = CPU_4KSC;
781 __cpu_name[cpu] = "MIPS 4KSc";
784 c->cputype = CPU_5KC;
785 __cpu_name[cpu] = "MIPS 5Kc";
788 c->cputype = CPU_5KE;
789 __cpu_name[cpu] = "MIPS 5KE";
792 c->cputype = CPU_20KC;
793 __cpu_name[cpu] = "MIPS 20Kc";
796 c->cputype = CPU_24K;
797 __cpu_name[cpu] = "MIPS 24Kc";
800 c->cputype = CPU_24K;
801 __cpu_name[cpu] = "MIPS 24KEc";
804 c->cputype = CPU_25KF;
805 __cpu_name[cpu] = "MIPS 25Kc";
808 c->cputype = CPU_34K;
809 __cpu_name[cpu] = "MIPS 34Kc";
812 c->cputype = CPU_74K;
813 __cpu_name[cpu] = "MIPS 74Kc";
816 c->cputype = CPU_M14KC;
817 __cpu_name[cpu] = "MIPS M14Kc";
819 case PRID_IMP_M14KEC:
820 c->cputype = CPU_M14KEC;
821 __cpu_name[cpu] = "MIPS M14KEc";
824 c->cputype = CPU_1004K;
825 __cpu_name[cpu] = "MIPS 1004Kc";
828 c->cputype = CPU_1074K;
829 __cpu_name[cpu] = "MIPS 1074Kc";
831 case PRID_IMP_INTERAPTIV_UP:
832 c->cputype = CPU_INTERAPTIV;
833 __cpu_name[cpu] = "MIPS interAptiv";
835 case PRID_IMP_INTERAPTIV_MP:
836 c->cputype = CPU_INTERAPTIV;
837 __cpu_name[cpu] = "MIPS interAptiv (multi)";
839 case PRID_IMP_PROAPTIV_UP:
840 c->cputype = CPU_PROAPTIV;
841 __cpu_name[cpu] = "MIPS proAptiv";
843 case PRID_IMP_PROAPTIV_MP:
844 c->cputype = CPU_PROAPTIV;
845 __cpu_name[cpu] = "MIPS proAptiv (multi)";
848 c->cputype = CPU_P5600;
849 __cpu_name[cpu] = "MIPS P5600";
852 c->cputype = CPU_M5150;
853 __cpu_name[cpu] = "MIPS M5150";
862 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
865 switch (c->processor_id & PRID_IMP_MASK) {
866 case PRID_IMP_AU1_REV1:
867 case PRID_IMP_AU1_REV2:
868 c->cputype = CPU_ALCHEMY;
869 switch ((c->processor_id >> 24) & 0xff) {
871 __cpu_name[cpu] = "Au1000";
874 __cpu_name[cpu] = "Au1500";
877 __cpu_name[cpu] = "Au1100";
880 __cpu_name[cpu] = "Au1550";
883 __cpu_name[cpu] = "Au1200";
884 if ((c->processor_id & PRID_REV_MASK) == 2)
885 __cpu_name[cpu] = "Au1250";
888 __cpu_name[cpu] = "Au1210";
891 __cpu_name[cpu] = "Au1xxx";
898 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
902 switch (c->processor_id & PRID_IMP_MASK) {
904 c->cputype = CPU_SB1;
905 __cpu_name[cpu] = "SiByte SB1";
906 /* FPU in pass1 is known to have issues. */
907 if ((c->processor_id & PRID_REV_MASK) < 0x02)
908 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
911 c->cputype = CPU_SB1A;
912 __cpu_name[cpu] = "SiByte SB1A";
917 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
920 switch (c->processor_id & PRID_IMP_MASK) {
921 case PRID_IMP_SR71000:
922 c->cputype = CPU_SR71000;
923 __cpu_name[cpu] = "Sandcraft SR71000";
930 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
933 switch (c->processor_id & PRID_IMP_MASK) {
934 case PRID_IMP_PR4450:
935 c->cputype = CPU_PR4450;
936 __cpu_name[cpu] = "Philips PR4450";
937 set_isa(c, MIPS_CPU_ISA_M32R1);
942 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
945 switch (c->processor_id & PRID_IMP_MASK) {
946 case PRID_IMP_BMIPS32_REV4:
947 case PRID_IMP_BMIPS32_REV8:
948 c->cputype = CPU_BMIPS32;
949 __cpu_name[cpu] = "Broadcom BMIPS32";
950 set_elf_platform(cpu, "bmips32");
952 case PRID_IMP_BMIPS3300:
953 case PRID_IMP_BMIPS3300_ALT:
954 case PRID_IMP_BMIPS3300_BUG:
955 c->cputype = CPU_BMIPS3300;
956 __cpu_name[cpu] = "Broadcom BMIPS3300";
957 set_elf_platform(cpu, "bmips3300");
959 case PRID_IMP_BMIPS43XX: {
960 int rev = c->processor_id & PRID_REV_MASK;
962 if (rev >= PRID_REV_BMIPS4380_LO &&
963 rev <= PRID_REV_BMIPS4380_HI) {
964 c->cputype = CPU_BMIPS4380;
965 __cpu_name[cpu] = "Broadcom BMIPS4380";
966 set_elf_platform(cpu, "bmips4380");
968 c->cputype = CPU_BMIPS4350;
969 __cpu_name[cpu] = "Broadcom BMIPS4350";
970 set_elf_platform(cpu, "bmips4350");
974 case PRID_IMP_BMIPS5000:
975 c->cputype = CPU_BMIPS5000;
976 __cpu_name[cpu] = "Broadcom BMIPS5000";
977 set_elf_platform(cpu, "bmips5000");
978 c->options |= MIPS_CPU_ULRI;
983 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
986 switch (c->processor_id & PRID_IMP_MASK) {
987 case PRID_IMP_CAVIUM_CN38XX:
988 case PRID_IMP_CAVIUM_CN31XX:
989 case PRID_IMP_CAVIUM_CN30XX:
990 c->cputype = CPU_CAVIUM_OCTEON;
991 __cpu_name[cpu] = "Cavium Octeon";
993 case PRID_IMP_CAVIUM_CN58XX:
994 case PRID_IMP_CAVIUM_CN56XX:
995 case PRID_IMP_CAVIUM_CN50XX:
996 case PRID_IMP_CAVIUM_CN52XX:
997 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
998 __cpu_name[cpu] = "Cavium Octeon+";
1000 set_elf_platform(cpu, "octeon");
1002 case PRID_IMP_CAVIUM_CN61XX:
1003 case PRID_IMP_CAVIUM_CN63XX:
1004 case PRID_IMP_CAVIUM_CN66XX:
1005 case PRID_IMP_CAVIUM_CN68XX:
1006 case PRID_IMP_CAVIUM_CNF71XX:
1007 c->cputype = CPU_CAVIUM_OCTEON2;
1008 __cpu_name[cpu] = "Cavium Octeon II";
1009 set_elf_platform(cpu, "octeon2");
1011 case PRID_IMP_CAVIUM_CN70XX:
1012 case PRID_IMP_CAVIUM_CN78XX:
1013 c->cputype = CPU_CAVIUM_OCTEON3;
1014 __cpu_name[cpu] = "Cavium Octeon III";
1015 set_elf_platform(cpu, "octeon3");
1018 printk(KERN_INFO "Unknown Octeon chip!\n");
1019 c->cputype = CPU_UNKNOWN;
1024 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1027 /* JZRISC does not implement the CP0 counter. */
1028 c->options &= ~MIPS_CPU_COUNTER;
1029 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1030 switch (c->processor_id & PRID_IMP_MASK) {
1031 case PRID_IMP_JZRISC:
1032 c->cputype = CPU_JZRISC;
1033 __cpu_name[cpu] = "Ingenic JZRISC";
1036 panic("Unknown Ingenic Processor ID!");
1041 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1045 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1046 c->cputype = CPU_ALCHEMY;
1047 __cpu_name[cpu] = "Au1300";
1048 /* following stuff is not for Alchemy */
1052 c->options = (MIPS_CPU_TLB |
1060 switch (c->processor_id & PRID_IMP_MASK) {
1061 case PRID_IMP_NETLOGIC_XLP2XX:
1062 case PRID_IMP_NETLOGIC_XLP9XX:
1063 case PRID_IMP_NETLOGIC_XLP5XX:
1064 c->cputype = CPU_XLP;
1065 __cpu_name[cpu] = "Broadcom XLPII";
1068 case PRID_IMP_NETLOGIC_XLP8XX:
1069 case PRID_IMP_NETLOGIC_XLP3XX:
1070 c->cputype = CPU_XLP;
1071 __cpu_name[cpu] = "Netlogic XLP";
1074 case PRID_IMP_NETLOGIC_XLR732:
1075 case PRID_IMP_NETLOGIC_XLR716:
1076 case PRID_IMP_NETLOGIC_XLR532:
1077 case PRID_IMP_NETLOGIC_XLR308:
1078 case PRID_IMP_NETLOGIC_XLR532C:
1079 case PRID_IMP_NETLOGIC_XLR516C:
1080 case PRID_IMP_NETLOGIC_XLR508C:
1081 case PRID_IMP_NETLOGIC_XLR308C:
1082 c->cputype = CPU_XLR;
1083 __cpu_name[cpu] = "Netlogic XLR";
1086 case PRID_IMP_NETLOGIC_XLS608:
1087 case PRID_IMP_NETLOGIC_XLS408:
1088 case PRID_IMP_NETLOGIC_XLS404:
1089 case PRID_IMP_NETLOGIC_XLS208:
1090 case PRID_IMP_NETLOGIC_XLS204:
1091 case PRID_IMP_NETLOGIC_XLS108:
1092 case PRID_IMP_NETLOGIC_XLS104:
1093 case PRID_IMP_NETLOGIC_XLS616B:
1094 case PRID_IMP_NETLOGIC_XLS608B:
1095 case PRID_IMP_NETLOGIC_XLS416B:
1096 case PRID_IMP_NETLOGIC_XLS412B:
1097 case PRID_IMP_NETLOGIC_XLS408B:
1098 case PRID_IMP_NETLOGIC_XLS404B:
1099 c->cputype = CPU_XLR;
1100 __cpu_name[cpu] = "Netlogic XLS";
1104 pr_info("Unknown Netlogic chip id [%02x]!\n",
1106 c->cputype = CPU_XLR;
1110 if (c->cputype == CPU_XLP) {
1111 set_isa(c, MIPS_CPU_ISA_M64R2);
1112 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1113 /* This will be updated again after all threads are woken up */
1114 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1116 set_isa(c, MIPS_CPU_ISA_M64R1);
1117 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1119 c->kscratch_mask = 0xf;
1123 /* For use by uaccess.h */
1125 EXPORT_SYMBOL(__ua_limit);
1128 const char *__cpu_name[NR_CPUS];
1129 const char *__elf_platform;
1131 void cpu_probe(void)
1133 struct cpuinfo_mips *c = ¤t_cpu_data;
1134 unsigned int cpu = smp_processor_id();
1136 c->processor_id = PRID_IMP_UNKNOWN;
1137 c->fpu_id = FPIR_IMP_NONE;
1138 c->cputype = CPU_UNKNOWN;
1140 c->processor_id = read_c0_prid();
1141 switch (c->processor_id & PRID_COMP_MASK) {
1142 case PRID_COMP_LEGACY:
1143 cpu_probe_legacy(c, cpu);
1145 case PRID_COMP_MIPS:
1146 cpu_probe_mips(c, cpu);
1148 case PRID_COMP_ALCHEMY:
1149 cpu_probe_alchemy(c, cpu);
1151 case PRID_COMP_SIBYTE:
1152 cpu_probe_sibyte(c, cpu);
1154 case PRID_COMP_BROADCOM:
1155 cpu_probe_broadcom(c, cpu);
1157 case PRID_COMP_SANDCRAFT:
1158 cpu_probe_sandcraft(c, cpu);
1161 cpu_probe_nxp(c, cpu);
1163 case PRID_COMP_CAVIUM:
1164 cpu_probe_cavium(c, cpu);
1166 case PRID_COMP_INGENIC:
1167 cpu_probe_ingenic(c, cpu);
1169 case PRID_COMP_NETLOGIC:
1170 cpu_probe_netlogic(c, cpu);
1174 BUG_ON(!__cpu_name[cpu]);
1175 BUG_ON(c->cputype == CPU_UNKNOWN);
1178 * Platform code can force the cpu type to optimize code
1179 * generation. In that case be sure the cpu type is correctly
1180 * manually setup otherwise it could trigger some nasty bugs.
1182 BUG_ON(current_cpu_type() != c->cputype);
1184 if (mips_fpu_disabled)
1185 c->options &= ~MIPS_CPU_FPU;
1187 if (mips_dsp_disabled)
1188 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1190 if (c->options & MIPS_CPU_FPU) {
1191 c->fpu_id = cpu_get_fpu_id();
1193 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1194 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1195 if (c->fpu_id & MIPS_FPIR_3D)
1196 c->ases |= MIPS_ASE_MIPS3D;
1200 if (cpu_has_mips_r2) {
1201 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1202 /* R2 has Performance Counter Interrupt indicator */
1203 c->options |= MIPS_CPU_PCI;
1209 c->msa_id = cpu_get_msa_id();
1210 WARN(c->msa_id & MSA_IR_WRPF,
1211 "Vector register partitioning unimplemented!");
1214 cpu_probe_vmbits(c);
1218 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1222 void cpu_report(void)
1224 struct cpuinfo_mips *c = ¤t_cpu_data;
1226 pr_info("CPU%d revision is: %08x (%s)\n",
1227 smp_processor_id(), c->processor_id, cpu_name_string());
1228 if (c->options & MIPS_CPU_FPU)
1229 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1231 pr_info("MSA revision is: %08x\n", c->msa_id);