arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13 #include <linux/clocksource.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/gic.h>
  17 #include <asm/setup.h>
  18 #include <asm/traps.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned int gic_frequency;
  23 unsigned int gic_present;
  24 unsigned long _gic_base;
  25 unsigned int gic_irq_base;
  26 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  27
  28 /* The index into this array is the vector # of the interrupt. */
  29 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  30
  31 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  32 static struct gic_pending_regs pending_regs[NR_CPUS];
  33 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  34
  35 #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
  36 cycle_t gic_read_count(void)
  37 {
  38         unsigned int hi, hi2, lo;
  39
  40         do {
  41                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
  42                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
  43                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
  44         } while (hi2 != hi);
  45
  46         return (((cycle_t) hi) << 32) + lo;
  47 }
  48
  49 void gic_write_compare(cycle_t cnt)
  50 {
  51         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
  52                                 (int)(cnt >> 32));
  53         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
  54                                 (int)(cnt & 0xffffffff));
  55 }
  56
  57 void gic_write_cpu_compare(cycle_t cnt, int cpu)
  58 {
  59         unsigned long flags;
  60
  61         local_irq_save(flags);
  62
  63         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
  64         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
  65                                 (int)(cnt >> 32));
  66         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
  67                                 (int)(cnt & 0xffffffff));
  68
  69         local_irq_restore(flags);
  70 }
  71
  72 cycle_t gic_read_compare(void)
  73 {
  74         unsigned int hi, lo;
  75
  76         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
  77         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
  78
  79         return (((cycle_t) hi) << 32) + lo;
  80 }
  81 #endif
  82
  83 unsigned int gic_get_timer_pending(void)
  84 {
  85         unsigned int vpe_pending;
  86
  87         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  88         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  89         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  90 }
  91
  92 void gic_bind_eic_interrupt(int irq, int set)
  93 {
  94         /* Convert irq vector # to hw int # */
  95         irq -= GIC_PIN_TO_VEC_OFFSET;
  96
  97         /* Set irq to use shadow set */
  98         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  99 }
 100
 101 void gic_send_ipi(unsigned int intr)
 102 {
 103         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 104 }
 105
 106 static void gic_eic_irq_dispatch(void)
 107 {
 108         unsigned int cause = read_c0_cause();
 109         int irq;
 110
 111         irq = (cause & ST0_IM) >> STATUSB_IP2;
 112         if (irq == 0)
 113                 irq = -1;
 114
 115         if (irq >= 0)
 116                 do_IRQ(gic_irq_base + irq);
 117         else
 118                 spurious_interrupt();
 119 }
 120
 121 static void __init vpe_local_setup(unsigned int numvpes)
 122 {
 123         unsigned long timer_intr = GIC_INT_TMR;
 124         unsigned long perf_intr = GIC_INT_PERFCTR;
 125         unsigned int vpe_ctl;
 126         int i;
 127
 128         if (cpu_has_veic) {
 129                 /*
 130                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
 131                  * map to pin X+2-1 (since GIC adds 1)
 132                  */
 133                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 134                 /*
 135                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
 136                  * map to pin X+2-1 (since GIC adds 1)
 137                  */
 138                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 139         }
 140
 141         /*
 142          * Setup the default performance counter timer interrupts
 143          * for all VPEs
 144          */
 145         for (i = 0; i < numvpes; i++) {
 146                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 147
 148                 /* Are Interrupts locally routable? */
 149                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 150                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 151                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 152                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 153                 if (cpu_has_veic) {
 154                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 155                                 gic_eic_irq_dispatch);
 156                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 157                 }
 158
 159                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 160                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 161                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 162                 if (cpu_has_veic) {
 163                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 164                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 165                 }
 166         }
 167 }
 168
 169 unsigned int gic_compare_int(void)
 170 {
 171         unsigned int pending;
 172
 173         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
 174         if (pending & GIC_VPE_PEND_CMP_MSK)
 175                 return 1;
 176         else
 177                 return 0;
 178 }
 179
 180 unsigned int gic_get_int(void)
 181 {
 182         unsigned int i;
 183         unsigned long *pending, *intrmask, *pcpu_mask;
 184         unsigned long *pending_abs, *intrmask_abs;
 185
 186         /* Get per-cpu bitmaps */
 187         pending = pending_regs[smp_processor_id()].pending;
 188         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 189         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 190
 191         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 192                                                          GIC_SH_PEND_31_0_OFS);
 193         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 194                                                           GIC_SH_MASK_31_0_OFS);
 195
 196         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 197                 GICREAD(*pending_abs, pending[i]);
 198                 GICREAD(*intrmask_abs, intrmask[i]);
 199                 pending_abs++;
 200                 intrmask_abs++;
 201         }
 202
 203         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 204         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 205
 206         return find_first_bit(pending, GIC_NUM_INTRS);
 207 }
 208
 209 static void gic_mask_irq(struct irq_data *d)
 210 {
 211         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 212 }
 213
 214 static void gic_unmask_irq(struct irq_data *d)
 215 {
 216         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 217 }
 218
 219 #ifdef CONFIG_SMP
 220 static DEFINE_SPINLOCK(gic_lock);
 221
 222 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 223                             bool force)
 224 {
 225         unsigned int irq = (d->irq - gic_irq_base);
 226         cpumask_t       tmp = CPU_MASK_NONE;
 227         unsigned long   flags;
 228         int             i;
 229
 230         cpumask_and(&tmp, cpumask, cpu_online_mask);
 231         if (cpus_empty(tmp))
 232                 return -1;
 233
 234         /* Assumption : cpumask refers to a single CPU */
 235         spin_lock_irqsave(&gic_lock, flags);
 236
 237         /* Re-route this IRQ */
 238         GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 239
 240         /* Update the pcpu_masks */
 241         for (i = 0; i < NR_CPUS; i++)
 242                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 243         set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 244
 245         cpumask_copy(d->affinity, cpumask);
 246         spin_unlock_irqrestore(&gic_lock, flags);
 247
 248         return IRQ_SET_MASK_OK_NOCOPY;
 249 }
 250 #endif
 251
 252 static struct irq_chip gic_irq_controller = {
 253         .name                   =       "MIPS GIC",
 254         .irq_ack                =       gic_irq_ack,
 255         .irq_mask               =       gic_mask_irq,
 256         .irq_mask_ack           =       gic_mask_irq,
 257         .irq_unmask             =       gic_unmask_irq,
 258         .irq_eoi                =       gic_finish_irq,
 259 #ifdef CONFIG_SMP
 260         .irq_set_affinity       =       gic_set_affinity,
 261 #endif
 262 };
 263
 264 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 265         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 266         unsigned int flags)
 267 {
 268         struct gic_shared_intr_map *map_ptr;
 269
 270         /* Setup Intr to Pin mapping */
 271         if (pin & GIC_MAP_TO_NMI_MSK) {
 272                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 273                 /* FIXME: hack to route NMI to all cpu's */
 274                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 275                         GICWRITE(GIC_REG_ADDR(SHARED,
 276                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 277                                  0xffffffff);
 278                 }
 279         } else {
 280                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 281                          GIC_MAP_TO_PIN_MSK | pin);
 282                 /* Setup Intr to CPU mapping */
 283                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 284                 if (cpu_has_veic) {
 285                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 286                                 gic_eic_irq_dispatch);
 287                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 288                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 289                                 BUG();
 290                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 291                 }
 292         }
 293
 294         /* Setup Intr Polarity */
 295         GIC_SET_POLARITY(intr, polarity);
 296
 297         /* Setup Intr Trigger Type */
 298         GIC_SET_TRIGGER(intr, trigtype);
 299
 300         /* Init Intr Masks */
 301         GIC_CLR_INTR_MASK(intr);
 302         /* Initialise per-cpu Interrupt software masks */
 303         if (flags & GIC_FLAG_IPI)
 304                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 305         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 306                 GIC_SET_INTR_MASK(intr);
 307         if (trigtype == GIC_TRIG_EDGE)
 308                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 309 }
 310
 311 static void __init gic_basic_init(int numintrs, int numvpes,
 312                         struct gic_intr_map *intrmap, int mapsize)
 313 {
 314         unsigned int i, cpu;
 315         unsigned int pin_offset = 0;
 316
 317         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 318
 319         /* Setup defaults */
 320         for (i = 0; i < numintrs; i++) {
 321                 GIC_SET_POLARITY(i, GIC_POL_POS);
 322                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 323                 GIC_CLR_INTR_MASK(i);
 324                 if (i < GIC_NUM_INTRS) {
 325                         gic_irq_flags[i] = 0;
 326                         gic_shared_intr_map[i].num_shared_intr = 0;
 327                         gic_shared_intr_map[i].local_intr_mask = 0;
 328                 }
 329         }
 330
 331         /*
 332          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 333          * one because the GIC will add one (since 0=no intr).
 334          */
 335         if (cpu_has_veic)
 336                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 337
 338         /* Setup specifics */
 339         for (i = 0; i < mapsize; i++) {
 340                 cpu = intrmap[i].cpunum;
 341                 if (cpu == GIC_UNUSED)
 342                         continue;
 343                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 344                         continue;
 345                 gic_setup_intr(i,
 346                         intrmap[i].cpunum,
 347                         intrmap[i].pin + pin_offset,
 348                         intrmap[i].polarity,
 349                         intrmap[i].trigtype,
 350                         intrmap[i].flags);
 351         }
 352
 353         vpe_local_setup(numvpes);
 354 }
 355
 356 void __init gic_init(unsigned long gic_base_addr,
 357                      unsigned long gic_addrspace_size,
 358                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 359                      unsigned int irqbase)
 360 {
 361         unsigned int gicconfig;
 362         int numvpes, numintrs;
 363
 364         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 365                                                     gic_addrspace_size);
 366         gic_irq_base = irqbase;
 367
 368         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 369         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 370                    GIC_SH_CONFIG_NUMINTRS_SHF;
 371         numintrs = ((numintrs + 1) * 8);
 372
 373         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 374                   GIC_SH_CONFIG_NUMVPES_SHF;
 375         numvpes = numvpes + 1;
 376
 377         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 378
 379         gic_platform_init(numintrs, &gic_irq_controller);
 380 }