arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13 #include <linux/clocksource.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/gic.h>
  17 #include <asm/setup.h>
  18 #include <asm/traps.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned int gic_frequency;
  23 unsigned int gic_present;
  24 unsigned long _gic_base;
  25 unsigned int gic_irq_base;
  26 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  27
  28 /* The index into this array is the vector # of the interrupt. */
  29 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  30
  31 struct gic_pcpu_mask {
  32         DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
  33 };
  34
  35 struct gic_pending_regs {
  36         DECLARE_BITMAP(pending, GIC_NUM_INTRS);
  37 };
  38
  39 struct gic_intrmask_regs {
  40         DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
  41 };
  42
  43 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  44 static struct gic_pending_regs pending_regs[NR_CPUS];
  45 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  46
  47 #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
  48 cycle_t gic_read_count(void)
  49 {
  50         unsigned int hi, hi2, lo;
  51
  52         do {
  53                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
  54                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
  55                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
  56         } while (hi2 != hi);
  57
  58         return (((cycle_t) hi) << 32) + lo;
  59 }
  60
  61 void gic_write_compare(cycle_t cnt)
  62 {
  63         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
  64                                 (int)(cnt >> 32));
  65         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
  66                                 (int)(cnt & 0xffffffff));
  67 }
  68
  69 void gic_write_cpu_compare(cycle_t cnt, int cpu)
  70 {
  71         unsigned long flags;
  72
  73         local_irq_save(flags);
  74
  75         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
  76         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
  77                                 (int)(cnt >> 32));
  78         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
  79                                 (int)(cnt & 0xffffffff));
  80
  81         local_irq_restore(flags);
  82 }
  83
  84 cycle_t gic_read_compare(void)
  85 {
  86         unsigned int hi, lo;
  87
  88         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
  89         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
  90
  91         return (((cycle_t) hi) << 32) + lo;
  92 }
  93 #endif
  94
  95 unsigned int gic_get_timer_pending(void)
  96 {
  97         unsigned int vpe_pending;
  98
  99         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
 100         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
 101         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
 102 }
 103
 104 void gic_bind_eic_interrupt(int irq, int set)
 105 {
 106         /* Convert irq vector # to hw int # */
 107         irq -= GIC_PIN_TO_VEC_OFFSET;
 108
 109         /* Set irq to use shadow set */
 110         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
 111 }
 112
 113 void gic_send_ipi(unsigned int intr)
 114 {
 115         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 116 }
 117
 118 static void gic_eic_irq_dispatch(void)
 119 {
 120         unsigned int cause = read_c0_cause();
 121         int irq;
 122
 123         irq = (cause & ST0_IM) >> STATUSB_IP2;
 124         if (irq == 0)
 125                 irq = -1;
 126
 127         if (irq >= 0)
 128                 do_IRQ(gic_irq_base + irq);
 129         else
 130                 spurious_interrupt();
 131 }
 132
 133 static void __init vpe_local_setup(unsigned int numvpes)
 134 {
 135         unsigned long timer_intr = GIC_INT_TMR;
 136         unsigned long perf_intr = GIC_INT_PERFCTR;
 137         unsigned int vpe_ctl;
 138         int i;
 139
 140         if (cpu_has_veic) {
 141                 /*
 142                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
 143                  * map to pin X+2-1 (since GIC adds 1)
 144                  */
 145                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 146                 /*
 147                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
 148                  * map to pin X+2-1 (since GIC adds 1)
 149                  */
 150                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 151         }
 152
 153         /*
 154          * Setup the default performance counter timer interrupts
 155          * for all VPEs
 156          */
 157         for (i = 0; i < numvpes; i++) {
 158                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 159
 160                 /* Are Interrupts locally routable? */
 161                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 162                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 163                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 164                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 165                 if (cpu_has_veic) {
 166                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 167                                 gic_eic_irq_dispatch);
 168                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 169                 }
 170
 171                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 172                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 173                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 174                 if (cpu_has_veic) {
 175                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 176                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 177                 }
 178         }
 179 }
 180
 181 unsigned int gic_compare_int(void)
 182 {
 183         unsigned int pending;
 184
 185         GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
 186         if (pending & GIC_VPE_PEND_CMP_MSK)
 187                 return 1;
 188         else
 189                 return 0;
 190 }
 191
 192 void gic_get_int_mask(unsigned long *dst, const unsigned long *src)
 193 {
 194         unsigned int i;
 195         unsigned long *pending, *intrmask, *pcpu_mask;
 196         unsigned long *pending_abs, *intrmask_abs;
 197
 198         /* Get per-cpu bitmaps */
 199         pending = pending_regs[smp_processor_id()].pending;
 200         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 201         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 202
 203         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 204                                                          GIC_SH_PEND_31_0_OFS);
 205         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 206                                                           GIC_SH_MASK_31_0_OFS);
 207
 208         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 209                 GICREAD(*pending_abs, pending[i]);
 210                 GICREAD(*intrmask_abs, intrmask[i]);
 211                 pending_abs++;
 212                 intrmask_abs++;
 213         }
 214
 215         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 216         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 217         bitmap_and(dst, src, pending, GIC_NUM_INTRS);
 218 }
 219
 220 unsigned int gic_get_int(void)
 221 {
 222         DECLARE_BITMAP(interrupts, GIC_NUM_INTRS);
 223
 224         bitmap_fill(interrupts, GIC_NUM_INTRS);
 225         gic_get_int_mask(interrupts, interrupts);
 226
 227         return find_first_bit(interrupts, GIC_NUM_INTRS);
 228 }
 229
 230 static void gic_mask_irq(struct irq_data *d)
 231 {
 232         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 233 }
 234
 235 static void gic_unmask_irq(struct irq_data *d)
 236 {
 237         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 238 }
 239
 240 #ifdef CONFIG_SMP
 241 static DEFINE_SPINLOCK(gic_lock);
 242
 243 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 244                             bool force)
 245 {
 246         unsigned int irq = (d->irq - gic_irq_base);
 247         cpumask_t       tmp = CPU_MASK_NONE;
 248         unsigned long   flags;
 249         int             i;
 250
 251         cpumask_and(&tmp, cpumask, cpu_online_mask);
 252         if (cpus_empty(tmp))
 253                 return -1;
 254
 255         /* Assumption : cpumask refers to a single CPU */
 256         spin_lock_irqsave(&gic_lock, flags);
 257
 258         /* Re-route this IRQ */
 259         GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 260
 261         /* Update the pcpu_masks */
 262         for (i = 0; i < NR_CPUS; i++)
 263                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 264         set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 265
 266         cpumask_copy(d->affinity, cpumask);
 267         spin_unlock_irqrestore(&gic_lock, flags);
 268
 269         return IRQ_SET_MASK_OK_NOCOPY;
 270 }
 271 #endif
 272
 273 static struct irq_chip gic_irq_controller = {
 274         .name                   =       "MIPS GIC",
 275         .irq_ack                =       gic_irq_ack,
 276         .irq_mask               =       gic_mask_irq,
 277         .irq_mask_ack           =       gic_mask_irq,
 278         .irq_unmask             =       gic_unmask_irq,
 279         .irq_eoi                =       gic_finish_irq,
 280 #ifdef CONFIG_SMP
 281         .irq_set_affinity       =       gic_set_affinity,
 282 #endif
 283 };
 284
 285 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 286         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 287         unsigned int flags)
 288 {
 289         struct gic_shared_intr_map *map_ptr;
 290
 291         /* Setup Intr to Pin mapping */
 292         if (pin & GIC_MAP_TO_NMI_MSK) {
 293                 int i;
 294
 295                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 296                 /* FIXME: hack to route NMI to all cpu's */
 297                 for (i = 0; i < NR_CPUS; i += 32) {
 298                         GICWRITE(GIC_REG_ADDR(SHARED,
 299                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
 300                                  0xffffffff);
 301                 }
 302         } else {
 303                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 304                          GIC_MAP_TO_PIN_MSK | pin);
 305                 /* Setup Intr to CPU mapping */
 306                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 307                 if (cpu_has_veic) {
 308                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 309                                 gic_eic_irq_dispatch);
 310                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 311                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 312                                 BUG();
 313                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 314                 }
 315         }
 316
 317         /* Setup Intr Polarity */
 318         GIC_SET_POLARITY(intr, polarity);
 319
 320         /* Setup Intr Trigger Type */
 321         GIC_SET_TRIGGER(intr, trigtype);
 322
 323         /* Init Intr Masks */
 324         GIC_CLR_INTR_MASK(intr);
 325
 326         /* Initialise per-cpu Interrupt software masks */
 327         set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 328
 329         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 330                 GIC_SET_INTR_MASK(intr);
 331         if (trigtype == GIC_TRIG_EDGE)
 332                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 333 }
 334
 335 static void __init gic_basic_init(int numintrs, int numvpes,
 336                         struct gic_intr_map *intrmap, int mapsize)
 337 {
 338         unsigned int i, cpu;
 339         unsigned int pin_offset = 0;
 340
 341         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 342
 343         /* Setup defaults */
 344         for (i = 0; i < numintrs; i++) {
 345                 GIC_SET_POLARITY(i, GIC_POL_POS);
 346                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 347                 GIC_CLR_INTR_MASK(i);
 348                 if (i < GIC_NUM_INTRS) {
 349                         gic_irq_flags[i] = 0;
 350                         gic_shared_intr_map[i].num_shared_intr = 0;
 351                         gic_shared_intr_map[i].local_intr_mask = 0;
 352                 }
 353         }
 354
 355         /*
 356          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 357          * one because the GIC will add one (since 0=no intr).
 358          */
 359         if (cpu_has_veic)
 360                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 361
 362         /* Setup specifics */
 363         for (i = 0; i < mapsize; i++) {
 364                 cpu = intrmap[i].cpunum;
 365                 if (cpu == GIC_UNUSED)
 366                         continue;
 367                 gic_setup_intr(i,
 368                         intrmap[i].cpunum,
 369                         intrmap[i].pin + pin_offset,
 370                         intrmap[i].polarity,
 371                         intrmap[i].trigtype,
 372                         intrmap[i].flags);
 373         }
 374
 375         vpe_local_setup(numvpes);
 376 }
 377
 378 void __init gic_init(unsigned long gic_base_addr,
 379                      unsigned long gic_addrspace_size,
 380                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 381                      unsigned int irqbase)
 382 {
 383         unsigned int gicconfig;
 384         int numvpes, numintrs;
 385
 386         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 387                                                     gic_addrspace_size);
 388         gic_irq_base = irqbase;
 389
 390         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 391         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 392                    GIC_SH_CONFIG_NUMINTRS_SHF;
 393         numintrs = ((numintrs + 1) * 8);
 394
 395         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 396                   GIC_SH_CONFIG_NUMVPES_SHF;
 397         numvpes = numvpes + 1;
 398
 399         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 400
 401         gic_platform_init(numintrs, &gic_irq_controller);
 402 }