2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
9 * This file define the irq handler for MIPS CPU interrupts.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
25 * Don't even think about using this on SMP. You have been warned.
27 * This file exports one global function:
28 * void mips_cpu_irq_init(void);
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33 #include <linux/irq.h>
34 #include <linux/irqdomain.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/mipsregs.h>
38 #include <asm/mipsmtregs.h>
39 #include <asm/setup.h>
41 static inline void unmask_mips_irq(struct irq_data *d)
43 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
47 static inline void mask_mips_irq(struct irq_data *d)
49 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
53 static struct irq_chip mips_cpu_irq_controller = {
55 .irq_ack = mask_mips_irq,
56 .irq_mask = mask_mips_irq,
57 .irq_mask_ack = mask_mips_irq,
58 .irq_unmask = unmask_mips_irq,
59 .irq_eoi = unmask_mips_irq,
63 * Basically the same as above but taking care of all the MT stuff
66 static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
68 unsigned int vpflags = dvpe();
70 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
77 * While we ack the interrupt interrupts are disabled and thus we don't need
78 * to deal with concurrency issues. Same for mips_cpu_irq_end.
80 static void mips_mt_cpu_irq_ack(struct irq_data *d)
82 unsigned int vpflags = dvpe();
83 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
88 static struct irq_chip mips_mt_cpu_irq_controller = {
90 .irq_startup = mips_mt_cpu_irq_startup,
91 .irq_ack = mips_mt_cpu_irq_ack,
92 .irq_mask = mask_mips_irq,
93 .irq_mask_ack = mips_mt_cpu_irq_ack,
94 .irq_unmask = unmask_mips_irq,
95 .irq_eoi = unmask_mips_irq,
98 asmlinkage void __weak plat_irq_dispatch(void)
100 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
104 spurious_interrupt();
108 pending >>= CAUSEB_IP;
110 irq = fls(pending) - 1;
111 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
112 pending &= ~BIT(irq);
116 static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
119 static struct irq_chip *chip;
121 if (hw < 2 && cpu_has_mipsmt) {
122 /* Software interrupts are used for MT/CMT IPI */
123 chip = &mips_mt_cpu_irq_controller;
125 chip = &mips_cpu_irq_controller;
129 set_vi_handler(hw, plat_irq_dispatch);
131 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
136 static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
137 .map = mips_cpu_intc_map,
138 .xlate = irq_domain_xlate_onecell,
141 static void __init __mips_cpu_irq_init(struct device_node *of_node)
143 struct irq_domain *domain;
145 /* Mask interrupts. */
146 clear_c0_status(ST0_IM);
147 clear_c0_cause(CAUSEF_IP);
149 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
150 &mips_cpu_intc_irq_domain_ops, NULL);
152 panic("Failed to add irqdomain for MIPS CPU");
155 void __init mips_cpu_irq_init(void)
157 __mips_cpu_irq_init(NULL);
160 int __init mips_cpu_irq_of_init(struct device_node *of_node,
161 struct device_node *parent)
163 __mips_cpu_irq_init(of_node);