arch/mips/kernel/mips-cpc.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/errno.h>
  12 #include <linux/percpu.h>
  13 #include <linux/spinlock.h>
  14
  15 #include <asm/mips-cm.h>
  16 #include <asm/mips-cpc.h>
  17
  18 void __iomem *mips_cpc_base;
  19
  20 static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
  21
  22 static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
  23
  24 phys_addr_t __weak mips_cpc_phys_base(void)
  25 {
  26         u32 cpc_base;
  27
  28         if (!mips_cm_present())
  29                 return 0;
  30
  31         if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
  32                 return 0;
  33
  34         /* If the CPC is already enabled, leave it so */
  35         cpc_base = read_gcr_cpc_base();
  36         if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
  37                 return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
  38
  39         /* Otherwise, give it the default address & enable it */
  40         cpc_base = mips_cpc_default_phys_base();
  41         write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
  42         return cpc_base;
  43 }
  44
  45 int mips_cpc_probe(void)
  46 {
  47         phys_addr_t addr;
  48         unsigned cpu;
  49
  50         for_each_possible_cpu(cpu)
  51                 spin_lock_init(&per_cpu(cpc_core_lock, cpu));
  52
  53         addr = mips_cpc_phys_base();
  54         if (!addr)
  55                 return -ENODEV;
  56
  57         mips_cpc_base = ioremap_nocache(addr, 0x8000);
  58         if (!mips_cpc_base)
  59                 return -ENXIO;
  60
  61         return 0;
  62 }
  63
  64 void mips_cpc_lock_other(unsigned int core)
  65 {
  66         unsigned curr_core;
  67         preempt_disable();
  68         curr_core = current_cpu_data.core;
  69         spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
  70                           per_cpu(cpc_core_lock_flags, curr_core));
  71         write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
  72 }
  73
  74 void mips_cpc_unlock_other(void)
  75 {
  76         unsigned curr_core = current_cpu_data.core;
  77         spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
  78                                per_cpu(cpc_core_lock_flags, curr_core));
  79         preempt_enable();
  80 }