2 * Linux performance counter support for MIPS.
4 * Copyright (C) 2010 MIPS Technologies, Inc.
5 * Copyright (C) 2011 Cavium Networks, Inc.
6 * Author: Deng-Cheng Zhu
8 * This code is based on the implementation for ARM, which is in turn
9 * based on the sparc64 perf event code and the x86 code. Performance
10 * counter access is based on the MIPS Oprofile code. And the callchain
11 * support references the code of MIPS stacktrace.c.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/cpumask.h>
19 #include <linux/interrupt.h>
20 #include <linux/smp.h>
21 #include <linux/kernel.h>
22 #include <linux/perf_event.h>
23 #include <linux/uaccess.h>
26 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
28 #include <asm/time.h> /* For perf_irq */
30 #define MIPS_MAX_HWEVENTS 4
31 #define MIPS_TCS_PER_COUNTER 2
32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
34 struct cpu_hw_events {
35 /* Array of events on this cpu. */
36 struct perf_event *events[MIPS_MAX_HWEVENTS];
39 * Set the bit (indexed by the counter number) when the counter
40 * is used for an event.
42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
45 * Software copy of the control register for each performance counter.
46 * MIPS CPUs vary in performance counters. They use this differently,
47 * and even may not use it.
49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 /* The description of MIPS performance events. */
56 struct mips_perf_event {
57 unsigned int event_id;
59 * MIPS performance counters are indexed starting from 0.
60 * CNTR_EVEN indicates the indexes of the counters to be used are
63 unsigned int cntr_mask;
64 #define CNTR_EVEN 0x55555555
65 #define CNTR_ODD 0xaaaaaaaa
66 #define CNTR_ALL 0xffffffff
67 #ifdef CONFIG_MIPS_MT_SMP
80 static struct mips_perf_event raw_event;
81 static DEFINE_MUTEX(raw_event_mutex);
83 #define C(x) PERF_COUNT_HW_CACHE_##x
91 u64 (*read_counter)(unsigned int idx);
92 void (*write_counter)(unsigned int idx, u64 val);
93 const struct mips_perf_event *(*map_raw_event)(u64 config);
94 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
95 const struct mips_perf_event (*cache_event_map)
96 [PERF_COUNT_HW_CACHE_MAX]
97 [PERF_COUNT_HW_CACHE_OP_MAX]
98 [PERF_COUNT_HW_CACHE_RESULT_MAX];
99 unsigned int num_counters;
102 static struct mips_pmu mipspmu;
104 #define M_CONFIG1_PC (1 << 4)
106 #define M_PERFCTL_EXL (1 << 0)
107 #define M_PERFCTL_KERNEL (1 << 1)
108 #define M_PERFCTL_SUPERVISOR (1 << 2)
109 #define M_PERFCTL_USER (1 << 3)
110 #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
111 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
112 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
114 #ifdef CONFIG_CPU_BMIPS5000
115 #define M_PERFCTL_MT_EN(filter) 0
116 #else /* !CONFIG_CPU_BMIPS5000 */
117 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
118 #endif /* CONFIG_CPU_BMIPS5000 */
120 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
121 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
122 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
123 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
124 #define M_PERFCTL_WIDE (1 << 30)
125 #define M_PERFCTL_MORE (1 << 31)
126 #define M_PERFCTL_TC (1 << 30)
128 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
131 M_PERFCTL_SUPERVISOR | \
132 M_PERFCTL_INTERRUPT_ENABLE)
134 #ifdef CONFIG_MIPS_MT_SMP
135 #define M_PERFCTL_CONFIG_MASK 0x3fff801f
137 #define M_PERFCTL_CONFIG_MASK 0x1f
139 #define M_PERFCTL_EVENT_MASK 0xfe0
142 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
143 static int cpu_has_mipsmt_pertccounters;
145 static DEFINE_RWLOCK(pmuint_rwlock);
147 #if defined(CONFIG_CPU_BMIPS5000)
148 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
149 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
152 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
153 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
155 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
156 0 : smp_processor_id())
159 /* Copied from op_model_mipsxx.c */
160 static unsigned int vpe_shift(void)
162 if (num_possible_cpus() > 1)
168 static unsigned int counters_total_to_per_cpu(unsigned int counters)
170 return counters >> vpe_shift();
173 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
176 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
178 static void resume_local_counters(void);
179 static void pause_local_counters(void);
180 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
181 static int mipsxx_pmu_handle_shared_irq(void);
183 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
190 static u64 mipsxx_pmu_read_counter(unsigned int idx)
192 idx = mipsxx_pmu_swizzle_perf_idx(idx);
197 * The counters are unsigned, we must cast to truncate
200 return (u32)read_c0_perfcntr0();
202 return (u32)read_c0_perfcntr1();
204 return (u32)read_c0_perfcntr2();
206 return (u32)read_c0_perfcntr3();
208 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
213 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
215 idx = mipsxx_pmu_swizzle_perf_idx(idx);
219 return read_c0_perfcntr0_64();
221 return read_c0_perfcntr1_64();
223 return read_c0_perfcntr2_64();
225 return read_c0_perfcntr3_64();
227 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
232 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
234 idx = mipsxx_pmu_swizzle_perf_idx(idx);
238 write_c0_perfcntr0(val);
241 write_c0_perfcntr1(val);
244 write_c0_perfcntr2(val);
247 write_c0_perfcntr3(val);
252 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
254 idx = mipsxx_pmu_swizzle_perf_idx(idx);
258 write_c0_perfcntr0_64(val);
261 write_c0_perfcntr1_64(val);
264 write_c0_perfcntr2_64(val);
267 write_c0_perfcntr3_64(val);
272 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
274 idx = mipsxx_pmu_swizzle_perf_idx(idx);
278 return read_c0_perfctrl0();
280 return read_c0_perfctrl1();
282 return read_c0_perfctrl2();
284 return read_c0_perfctrl3();
286 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
291 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
293 idx = mipsxx_pmu_swizzle_perf_idx(idx);
297 write_c0_perfctrl0(val);
300 write_c0_perfctrl1(val);
303 write_c0_perfctrl2(val);
306 write_c0_perfctrl3(val);
311 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
312 struct hw_perf_event *hwc)
317 * We only need to care the counter mask. The range has been
318 * checked definitely.
320 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
322 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
324 * Note that some MIPS perf events can be counted by both
325 * even and odd counters, wheresas many other are only by
326 * even _or_ odd counters. This introduces an issue that
327 * when the former kind of event takes the counter the
328 * latter kind of event wants to use, then the "counter
329 * allocation" for the latter event will fail. In fact if
330 * they can be dynamically swapped, they both feel happy.
331 * But here we leave this issue alone for now.
333 if (test_bit(i, &cntr_mask) &&
334 !test_and_set_bit(i, cpuc->used_mask))
341 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
345 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
347 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
348 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
349 /* Make sure interrupt enabled. */
350 M_PERFCTL_INTERRUPT_ENABLE;
351 if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
352 /* enable the counter for the calling thread */
353 cpuc->saved_ctrl[idx] |=
354 (1 << (12 + vpe_id())) | M_PERFCTL_TC;
357 * We do not actually let the counter run. Leave it until start().
361 static void mipsxx_pmu_disable_event(int idx)
363 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
366 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
368 local_irq_save(flags);
369 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
370 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
371 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
372 local_irq_restore(flags);
375 static int mipspmu_event_set_period(struct perf_event *event,
376 struct hw_perf_event *hwc,
379 u64 left = local64_read(&hwc->period_left);
380 u64 period = hwc->sample_period;
383 if (unlikely((left + period) & (1ULL << 63))) {
384 /* left underflowed by more than period. */
386 local64_set(&hwc->period_left, left);
387 hwc->last_period = period;
389 } else if (unlikely((left + period) <= period)) {
390 /* left underflowed by less than period. */
392 local64_set(&hwc->period_left, left);
393 hwc->last_period = period;
397 if (left > mipspmu.max_period) {
398 left = mipspmu.max_period;
399 local64_set(&hwc->period_left, left);
402 local64_set(&hwc->prev_count, mipspmu.overflow - left);
404 mipspmu.write_counter(idx, mipspmu.overflow - left);
406 perf_event_update_userpage(event);
411 static void mipspmu_event_update(struct perf_event *event,
412 struct hw_perf_event *hwc,
415 u64 prev_raw_count, new_raw_count;
419 prev_raw_count = local64_read(&hwc->prev_count);
420 new_raw_count = mipspmu.read_counter(idx);
422 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
423 new_raw_count) != prev_raw_count)
426 delta = new_raw_count - prev_raw_count;
428 local64_add(delta, &event->count);
429 local64_sub(delta, &hwc->period_left);
432 static void mipspmu_start(struct perf_event *event, int flags)
434 struct hw_perf_event *hwc = &event->hw;
436 if (flags & PERF_EF_RELOAD)
437 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
441 /* Set the period for the event. */
442 mipspmu_event_set_period(event, hwc, hwc->idx);
444 /* Enable the event. */
445 mipsxx_pmu_enable_event(hwc, hwc->idx);
448 static void mipspmu_stop(struct perf_event *event, int flags)
450 struct hw_perf_event *hwc = &event->hw;
452 if (!(hwc->state & PERF_HES_STOPPED)) {
453 /* We are working on a local event. */
454 mipsxx_pmu_disable_event(hwc->idx);
456 mipspmu_event_update(event, hwc, hwc->idx);
457 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
461 static int mipspmu_add(struct perf_event *event, int flags)
463 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
464 struct hw_perf_event *hwc = &event->hw;
468 perf_pmu_disable(event->pmu);
470 /* To look for a free counter for this event. */
471 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
478 * If there is an event in the counter we are going to use then
479 * make sure it is disabled.
482 mipsxx_pmu_disable_event(idx);
483 cpuc->events[idx] = event;
485 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
486 if (flags & PERF_EF_START)
487 mipspmu_start(event, PERF_EF_RELOAD);
489 /* Propagate our changes to the userspace mapping. */
490 perf_event_update_userpage(event);
493 perf_pmu_enable(event->pmu);
497 static void mipspmu_del(struct perf_event *event, int flags)
499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
500 struct hw_perf_event *hwc = &event->hw;
503 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
505 mipspmu_stop(event, PERF_EF_UPDATE);
506 cpuc->events[idx] = NULL;
507 clear_bit(idx, cpuc->used_mask);
509 perf_event_update_userpage(event);
512 static void mipspmu_read(struct perf_event *event)
514 struct hw_perf_event *hwc = &event->hw;
516 /* Don't read disabled counters! */
520 mipspmu_event_update(event, hwc, hwc->idx);
523 static void mipspmu_enable(struct pmu *pmu)
525 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
526 write_unlock(&pmuint_rwlock);
528 resume_local_counters();
532 * MIPS performance counters can be per-TC. The control registers can
533 * not be directly accessed accross CPUs. Hence if we want to do global
534 * control, we need cross CPU calls. on_each_cpu() can help us, but we
535 * can not make sure this function is called with interrupts enabled. So
536 * here we pause local counters and then grab a rwlock and leave the
537 * counters on other CPUs alone. If any counter interrupt raises while
538 * we own the write lock, simply pause local counters on that CPU and
539 * spin in the handler. Also we know we won't be switched to another
540 * CPU after pausing local counters and before grabbing the lock.
542 static void mipspmu_disable(struct pmu *pmu)
544 pause_local_counters();
545 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
546 write_lock(&pmuint_rwlock);
550 static atomic_t active_events = ATOMIC_INIT(0);
551 static DEFINE_MUTEX(pmu_reserve_mutex);
552 static int (*save_perf_irq)(void);
554 static int mipspmu_get_irq(void)
558 if (mipspmu.irq >= 0) {
559 /* Request my own irq handler. */
560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
561 IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
562 "mips_perf_pmu", NULL);
564 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
567 } else if (cp0_perfcount_irq < 0) {
569 * We are sharing the irq number with the timer interrupt.
571 save_perf_irq = perf_irq;
572 perf_irq = mipsxx_pmu_handle_shared_irq;
575 pr_warn("The platform hasn't properly defined its interrupt controller\n");
582 static void mipspmu_free_irq(void)
584 if (mipspmu.irq >= 0)
585 free_irq(mipspmu.irq, NULL);
586 else if (cp0_perfcount_irq < 0)
587 perf_irq = save_perf_irq;
591 * mipsxx/rm9000/loongson2 have different performance counters, they have
592 * specific low-level init routines.
594 static void reset_counters(void *arg);
595 static int __hw_perf_event_init(struct perf_event *event);
597 static void hw_perf_event_destroy(struct perf_event *event)
599 if (atomic_dec_and_mutex_lock(&active_events,
600 &pmu_reserve_mutex)) {
602 * We must not call the destroy function with interrupts
605 on_each_cpu(reset_counters,
606 (void *)(long)mipspmu.num_counters, 1);
608 mutex_unlock(&pmu_reserve_mutex);
612 static int mipspmu_event_init(struct perf_event *event)
616 /* does not support taken branch sampling */
617 if (has_branch_stack(event))
620 switch (event->attr.type) {
622 case PERF_TYPE_HARDWARE:
623 case PERF_TYPE_HW_CACHE:
630 if (event->cpu >= nr_cpumask_bits ||
631 (event->cpu >= 0 && !cpu_online(event->cpu)))
634 if (!atomic_inc_not_zero(&active_events)) {
635 mutex_lock(&pmu_reserve_mutex);
636 if (atomic_read(&active_events) == 0)
637 err = mipspmu_get_irq();
640 atomic_inc(&active_events);
641 mutex_unlock(&pmu_reserve_mutex);
647 return __hw_perf_event_init(event);
650 static struct pmu pmu = {
651 .pmu_enable = mipspmu_enable,
652 .pmu_disable = mipspmu_disable,
653 .event_init = mipspmu_event_init,
656 .start = mipspmu_start,
657 .stop = mipspmu_stop,
658 .read = mipspmu_read,
661 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
664 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
667 #ifdef CONFIG_MIPS_MT_SMP
668 return ((unsigned int)pev->range << 24) |
669 (pev->cntr_mask & 0xffff00) |
670 (pev->event_id & 0xff);
672 return (pev->cntr_mask & 0xffff00) |
673 (pev->event_id & 0xff);
677 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
680 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
681 return ERR_PTR(-EOPNOTSUPP);
682 return &(*mipspmu.general_event_map)[idx];
685 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
687 unsigned int cache_type, cache_op, cache_result;
688 const struct mips_perf_event *pev;
690 cache_type = (config >> 0) & 0xff;
691 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
692 return ERR_PTR(-EINVAL);
694 cache_op = (config >> 8) & 0xff;
695 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
696 return ERR_PTR(-EINVAL);
698 cache_result = (config >> 16) & 0xff;
699 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
700 return ERR_PTR(-EINVAL);
702 pev = &((*mipspmu.cache_event_map)
707 if (pev->cntr_mask == 0)
708 return ERR_PTR(-EOPNOTSUPP);
714 static int validate_group(struct perf_event *event)
716 struct perf_event *sibling, *leader = event->group_leader;
717 struct cpu_hw_events fake_cpuc;
719 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
724 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
725 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
729 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
735 /* This is needed by specific irq handlers in perf_event_*.c */
736 static void handle_associated_event(struct cpu_hw_events *cpuc,
737 int idx, struct perf_sample_data *data,
738 struct pt_regs *regs)
740 struct perf_event *event = cpuc->events[idx];
741 struct hw_perf_event *hwc = &event->hw;
743 mipspmu_event_update(event, hwc, idx);
744 data->period = event->hw.last_period;
745 if (!mipspmu_event_set_period(event, hwc, idx))
748 if (perf_event_overflow(event, data, regs))
749 mipsxx_pmu_disable_event(idx);
753 static int __n_counters(void)
755 if (!(read_c0_config1() & M_CONFIG1_PC))
757 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
759 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
761 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
767 static int n_counters(void)
771 switch (current_cpu_type()) {
782 counters = __n_counters();
788 static void reset_counters(void *arg)
790 int counters = (int)(long)arg;
793 mipsxx_pmu_write_control(3, 0);
794 mipspmu.write_counter(3, 0);
796 mipsxx_pmu_write_control(2, 0);
797 mipspmu.write_counter(2, 0);
799 mipsxx_pmu_write_control(1, 0);
800 mipspmu.write_counter(1, 0);
802 mipsxx_pmu_write_control(0, 0);
803 mipspmu.write_counter(0, 0);
807 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
808 static const struct mips_perf_event mipsxxcore_event_map
809 [PERF_COUNT_HW_MAX] = {
810 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
811 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
812 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
813 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
816 /* 74K/proAptiv core has different branch event code. */
817 static const struct mips_perf_event mipsxxcore_event_map2
818 [PERF_COUNT_HW_MAX] = {
819 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
820 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
821 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
822 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
825 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
826 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
827 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
828 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
829 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
830 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
831 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
832 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
835 static const struct mips_perf_event bmips5000_event_map
836 [PERF_COUNT_HW_MAX] = {
837 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
838 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
839 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
842 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
843 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
844 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
845 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
846 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
847 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
848 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
851 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
852 static const struct mips_perf_event mipsxxcore_cache_map
853 [PERF_COUNT_HW_CACHE_MAX]
854 [PERF_COUNT_HW_CACHE_OP_MAX]
855 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
858 * Like some other architectures (e.g. ARM), the performance
859 * counters don't differentiate between read and write
860 * accesses/misses, so this isn't strictly correct, but it's the
861 * best we can do. Writes and reads get combined.
864 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
865 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
868 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
869 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
874 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
875 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
878 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
879 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
882 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
884 * Note that MIPS has only "hit" events countable for
885 * the prefetch operation.
891 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
892 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
895 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
896 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
901 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
902 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
905 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
906 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
911 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
912 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
915 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
916 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
920 /* Using the same code for *HW_BRANCH* */
922 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
923 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
926 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
927 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
932 /* 74K/proAptiv core has completely different cache event map. */
933 static const struct mips_perf_event mipsxxcore_cache_map2
934 [PERF_COUNT_HW_CACHE_MAX]
935 [PERF_COUNT_HW_CACHE_OP_MAX]
936 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
939 * Like some other architectures (e.g. ARM), the performance
940 * counters don't differentiate between read and write
941 * accesses/misses, so this isn't strictly correct, but it's the
942 * best we can do. Writes and reads get combined.
945 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
946 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
949 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
950 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
955 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
956 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
959 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
960 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
963 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
965 * Note that MIPS has only "hit" events countable for
966 * the prefetch operation.
972 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
973 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
976 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
977 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
981 * 74K core does not have specific DTLB events. proAptiv core has
982 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
983 * not included here. One can use raw events if really needed.
987 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
988 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
991 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
992 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
996 /* Using the same code for *HW_BRANCH* */
998 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
999 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1002 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1003 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1009 static const struct mips_perf_event bmips5000_cache_map
1010 [PERF_COUNT_HW_CACHE_MAX]
1011 [PERF_COUNT_HW_CACHE_OP_MAX]
1012 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1015 * Like some other architectures (e.g. ARM), the performance
1016 * counters don't differentiate between read and write
1017 * accesses/misses, so this isn't strictly correct, but it's the
1018 * best we can do. Writes and reads get combined.
1021 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1025 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1026 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1031 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1035 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1036 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1038 [C(OP_PREFETCH)] = {
1039 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1041 * Note that MIPS has only "hit" events countable for
1042 * the prefetch operation.
1048 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1049 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1052 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1053 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1057 /* Using the same code for *HW_BRANCH* */
1059 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1062 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1068 static const struct mips_perf_event octeon_cache_map
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1074 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1075 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1078 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1083 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1085 [C(OP_PREFETCH)] = {
1086 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1091 * Only general DTLB misses are counted use the same event for
1095 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1098 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1103 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1108 static const struct mips_perf_event xlp_cache_map
1109 [PERF_COUNT_HW_CACHE_MAX]
1110 [PERF_COUNT_HW_CACHE_OP_MAX]
1111 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1114 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1115 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1118 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1119 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1124 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1125 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1130 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1131 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1134 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1135 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1140 * Only general DTLB misses are counted use the same event for
1144 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1147 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1152 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1155 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1160 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1165 #ifdef CONFIG_MIPS_MT_SMP
1166 static void check_and_calc_range(struct perf_event *event,
1167 const struct mips_perf_event *pev)
1169 struct hw_perf_event *hwc = &event->hw;
1171 if (event->cpu >= 0) {
1172 if (pev->range > V) {
1174 * The user selected an event that is processor
1175 * wide, while expecting it to be VPE wide.
1177 hwc->config_base |= M_TC_EN_ALL;
1180 * FIXME: cpu_data[event->cpu].vpe_id reports 0
1183 hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1184 hwc->config_base |= M_TC_EN_VPE;
1187 hwc->config_base |= M_TC_EN_ALL;
1190 static void check_and_calc_range(struct perf_event *event,
1191 const struct mips_perf_event *pev)
1196 static int __hw_perf_event_init(struct perf_event *event)
1198 struct perf_event_attr *attr = &event->attr;
1199 struct hw_perf_event *hwc = &event->hw;
1200 const struct mips_perf_event *pev;
1203 /* Returning MIPS event descriptor for generic perf event. */
1204 if (PERF_TYPE_HARDWARE == event->attr.type) {
1205 if (event->attr.config >= PERF_COUNT_HW_MAX)
1207 pev = mipspmu_map_general_event(event->attr.config);
1208 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1209 pev = mipspmu_map_cache_event(event->attr.config);
1210 } else if (PERF_TYPE_RAW == event->attr.type) {
1211 /* We are working on the global raw event. */
1212 mutex_lock(&raw_event_mutex);
1213 pev = mipspmu.map_raw_event(event->attr.config);
1215 /* The event type is not (yet) supported. */
1220 if (PERF_TYPE_RAW == event->attr.type)
1221 mutex_unlock(&raw_event_mutex);
1222 return PTR_ERR(pev);
1226 * We allow max flexibility on how each individual counter shared
1227 * by the single CPU operates (the mode exclusion and the range).
1229 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
1231 /* Calculate range bits and validate it. */
1232 if (num_possible_cpus() > 1)
1233 check_and_calc_range(event, pev);
1235 hwc->event_base = mipspmu_perf_event_encode(pev);
1236 if (PERF_TYPE_RAW == event->attr.type)
1237 mutex_unlock(&raw_event_mutex);
1239 if (!attr->exclude_user)
1240 hwc->config_base |= M_PERFCTL_USER;
1241 if (!attr->exclude_kernel) {
1242 hwc->config_base |= M_PERFCTL_KERNEL;
1243 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1244 hwc->config_base |= M_PERFCTL_EXL;
1246 if (!attr->exclude_hv)
1247 hwc->config_base |= M_PERFCTL_SUPERVISOR;
1249 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1251 * The event can belong to another cpu. We do not assign a local
1252 * counter for it for now.
1257 if (!hwc->sample_period) {
1258 hwc->sample_period = mipspmu.max_period;
1259 hwc->last_period = hwc->sample_period;
1260 local64_set(&hwc->period_left, hwc->sample_period);
1264 if (event->group_leader != event)
1265 err = validate_group(event);
1267 event->destroy = hw_perf_event_destroy;
1270 event->destroy(event);
1275 static void pause_local_counters(void)
1277 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1278 int ctr = mipspmu.num_counters;
1279 unsigned long flags;
1281 local_irq_save(flags);
1284 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1285 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1286 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1288 local_irq_restore(flags);
1291 static void resume_local_counters(void)
1293 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1294 int ctr = mipspmu.num_counters;
1298 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1302 static int mipsxx_pmu_handle_shared_irq(void)
1304 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1305 struct perf_sample_data data;
1306 unsigned int counters = mipspmu.num_counters;
1308 int handled = IRQ_NONE;
1309 struct pt_regs *regs;
1311 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1314 * First we pause the local counters, so that when we are locked
1315 * here, the counters are all paused. When it gets locked due to
1316 * perf_disable(), the timer interrupt handler will be delayed.
1318 * See also mipsxx_pmu_start().
1320 pause_local_counters();
1321 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1322 read_lock(&pmuint_rwlock);
1325 regs = get_irq_regs();
1327 perf_sample_data_init(&data, 0, 0);
1330 #define HANDLE_COUNTER(n) \
1332 if (test_bit(n, cpuc->used_mask)) { \
1333 counter = mipspmu.read_counter(n); \
1334 if (counter & mipspmu.overflow) { \
1335 handle_associated_event(cpuc, n, &data, regs); \
1336 handled = IRQ_HANDLED; \
1346 * Do all the work for the pending perf events. We can do this
1347 * in here because the performance counter interrupt is a regular
1348 * interrupt, not NMI.
1350 if (handled == IRQ_HANDLED)
1353 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1354 read_unlock(&pmuint_rwlock);
1356 resume_local_counters();
1360 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1362 return mipsxx_pmu_handle_shared_irq();
1366 #define IS_BOTH_COUNTERS_24K_EVENT(b) \
1367 ((b) == 0 || (b) == 1 || (b) == 11)
1370 #define IS_BOTH_COUNTERS_34K_EVENT(b) \
1371 ((b) == 0 || (b) == 1 || (b) == 11)
1372 #ifdef CONFIG_MIPS_MT_SMP
1373 #define IS_RANGE_P_34K_EVENT(r, b) \
1374 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1375 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1376 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1377 ((b) >= 64 && (b) <= 67))
1378 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1382 #define IS_BOTH_COUNTERS_74K_EVENT(b) \
1383 ((b) == 0 || (b) == 1)
1386 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
1387 ((b) == 0 || (b) == 1)
1389 #define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1390 ((b) == 0 || (b) == 1)
1393 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1394 ((b) == 0 || (b) == 1 || (b) == 11)
1395 #ifdef CONFIG_MIPS_MT_SMP
1396 #define IS_RANGE_P_1004K_EVENT(r, b) \
1397 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1398 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1399 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1400 (r) == 188 || (b) == 61 || (b) == 62 || \
1401 ((b) >= 64 && (b) <= 67))
1402 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1406 #define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
1407 ((b) == 0 || (b) == 1 || (b) == 11)
1408 #ifdef CONFIG_MIPS_MT_SMP
1409 /* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1410 #define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
1411 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1412 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
1413 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
1414 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
1415 ((b) >= 64 && (b) <= 67))
1416 #define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
1420 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
1421 ((b) == 0 || (b) == 1)
1425 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1426 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1427 * indicate the even/odd bank selector. So, for example, when user wants to take
1428 * the Event Num of 15 for odd counters (by referring to the user manual), then
1429 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1432 * Some newer cores have even more events, in which case the user can use raw
1433 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1434 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1436 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1438 /* currently most cores have 7-bit event numbers */
1439 unsigned int raw_id = config & 0xff;
1440 unsigned int base_id = raw_id & 0x7f;
1442 switch (current_cpu_type()) {
1444 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1445 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1447 raw_event.cntr_mask =
1448 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1449 #ifdef CONFIG_MIPS_MT_SMP
1451 * This is actually doing nothing. Non-multithreading
1452 * CPUs will not check and calculate the range.
1454 raw_event.range = P;
1458 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1459 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1461 raw_event.cntr_mask =
1462 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1463 #ifdef CONFIG_MIPS_MT_SMP
1464 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1465 raw_event.range = P;
1466 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1467 raw_event.range = V;
1469 raw_event.range = T;
1474 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1475 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1477 raw_event.cntr_mask =
1478 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1479 #ifdef CONFIG_MIPS_MT_SMP
1480 raw_event.range = P;
1484 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1485 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1487 raw_event.cntr_mask =
1488 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1489 #ifdef CONFIG_MIPS_MT_SMP
1490 raw_event.range = P;
1494 /* 8-bit event numbers */
1495 raw_id = config & 0x1ff;
1496 base_id = raw_id & 0xff;
1497 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1498 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1500 raw_event.cntr_mask =
1501 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1502 #ifdef CONFIG_MIPS_MT_SMP
1503 raw_event.range = P;
1507 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1508 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1510 raw_event.cntr_mask =
1511 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1512 #ifdef CONFIG_MIPS_MT_SMP
1513 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1514 raw_event.range = P;
1515 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1516 raw_event.range = V;
1518 raw_event.range = T;
1521 case CPU_INTERAPTIV:
1522 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1523 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1525 raw_event.cntr_mask =
1526 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1527 #ifdef CONFIG_MIPS_MT_SMP
1528 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1529 raw_event.range = P;
1530 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1531 raw_event.range = V;
1533 raw_event.range = T;
1537 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1538 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1540 raw_event.cntr_mask =
1541 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1544 raw_event.event_id = base_id;
1549 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1551 unsigned int raw_id = config & 0xff;
1552 unsigned int base_id = raw_id & 0x7f;
1555 raw_event.cntr_mask = CNTR_ALL;
1556 raw_event.event_id = base_id;
1558 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1560 return ERR_PTR(-EOPNOTSUPP);
1563 return ERR_PTR(-EOPNOTSUPP);
1574 return ERR_PTR(-EOPNOTSUPP);
1582 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1584 unsigned int raw_id = config & 0xff;
1586 /* Only 1-63 are defined */
1587 if ((raw_id < 0x01) || (raw_id > 0x3f))
1588 return ERR_PTR(-EOPNOTSUPP);
1590 raw_event.cntr_mask = CNTR_ALL;
1591 raw_event.event_id = raw_id;
1597 init_hw_perf_events(void)
1602 pr_info("Performance counters: ");
1604 counters = n_counters();
1605 if (counters == 0) {
1606 pr_cont("No available PMU.\n");
1610 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1611 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1612 if (!cpu_has_mipsmt_pertccounters)
1613 counters = counters_total_to_per_cpu(counters);
1616 if (get_c0_perfcount_int)
1617 irq = get_c0_perfcount_int();
1618 else if ((cp0_perfcount_irq >= 0) &&
1619 (cp0_compare_irq != cp0_perfcount_irq))
1620 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1624 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1626 switch (current_cpu_type()) {
1628 mipspmu.name = "mips/24K";
1629 mipspmu.general_event_map = &mipsxxcore_event_map;
1630 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1633 mipspmu.name = "mips/34K";
1634 mipspmu.general_event_map = &mipsxxcore_event_map;
1635 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1638 mipspmu.name = "mips/74K";
1639 mipspmu.general_event_map = &mipsxxcore_event_map2;
1640 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1643 mipspmu.name = "mips/proAptiv";
1644 mipspmu.general_event_map = &mipsxxcore_event_map2;
1645 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1648 mipspmu.name = "mips/P5600";
1649 mipspmu.general_event_map = &mipsxxcore_event_map2;
1650 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1653 mipspmu.name = "mips/1004K";
1654 mipspmu.general_event_map = &mipsxxcore_event_map;
1655 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1658 mipspmu.name = "mips/1074K";
1659 mipspmu.general_event_map = &mipsxxcore_event_map;
1660 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1662 case CPU_INTERAPTIV:
1663 mipspmu.name = "mips/interAptiv";
1664 mipspmu.general_event_map = &mipsxxcore_event_map;
1665 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1668 mipspmu.name = "mips/loongson1";
1669 mipspmu.general_event_map = &mipsxxcore_event_map;
1670 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1672 case CPU_CAVIUM_OCTEON:
1673 case CPU_CAVIUM_OCTEON_PLUS:
1674 case CPU_CAVIUM_OCTEON2:
1675 mipspmu.name = "octeon";
1676 mipspmu.general_event_map = &octeon_event_map;
1677 mipspmu.cache_event_map = &octeon_cache_map;
1678 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1681 mipspmu.name = "BMIPS5000";
1682 mipspmu.general_event_map = &bmips5000_event_map;
1683 mipspmu.cache_event_map = &bmips5000_cache_map;
1686 mipspmu.name = "xlp";
1687 mipspmu.general_event_map = &xlp_event_map;
1688 mipspmu.cache_event_map = &xlp_cache_map;
1689 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1692 pr_cont("Either hardware does not support performance "
1693 "counters, or not yet implemented.\n");
1697 mipspmu.num_counters = counters;
1700 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
1701 mipspmu.max_period = (1ULL << 63) - 1;
1702 mipspmu.valid_count = (1ULL << 63) - 1;
1703 mipspmu.overflow = 1ULL << 63;
1704 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1705 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1708 mipspmu.max_period = (1ULL << 31) - 1;
1709 mipspmu.valid_count = (1ULL << 31) - 1;
1710 mipspmu.overflow = 1ULL << 31;
1711 mipspmu.read_counter = mipsxx_pmu_read_counter;
1712 mipspmu.write_counter = mipsxx_pmu_write_counter;
1716 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1718 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1719 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1720 irq < 0 ? " (share with timer interrupt)" : "");
1722 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1726 early_initcall(init_hw_perf_events);