2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/delay.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/smp.h>
17 #include <linux/types.h>
19 #include <asm/bcache.h>
20 #include <asm/mips-cm.h>
21 #include <asm/mips-cpc.h>
22 #include <asm/mips_mt.h>
23 #include <asm/mipsregs.h>
24 #include <asm/pm-cps.h>
25 #include <asm/r4kcache.h>
26 #include <asm/smp-cps.h>
30 static bool threads_disabled;
31 static DECLARE_BITMAP(core_power, NR_CPUS);
33 struct core_boot_config *mips_cps_core_bootcfg;
35 static int __init setup_nothreads(char *s)
37 threads_disabled = true;
40 early_param("nothreads", setup_nothreads);
42 static unsigned core_vpe_count(unsigned core)
49 if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
50 && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
53 mips_cm_lock_other(core, 0);
54 cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
55 mips_cm_unlock_other();
56 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
59 static void __init cps_smp_setup(void)
61 unsigned int ncores, nvpes, core_vpes;
62 unsigned long core_entry;
65 /* Detect & record VPE topology */
66 ncores = mips_cm_numcores();
67 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
68 for (c = nvpes = 0; c < ncores; c++) {
69 core_vpes = core_vpe_count(c);
70 pr_cont("%c%u", c ? ',' : '{', core_vpes);
72 /* Use the number of VPEs in core 0 for smp_num_siblings */
74 smp_num_siblings = core_vpes;
76 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
77 cpu_data[nvpes + v].core = c;
78 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
79 cpu_data[nvpes + v].vpe_id = v;
85 pr_cont("} total %u\n", nvpes);
87 /* Indicate present CPUs (CPU being synonymous with VPE) */
88 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
89 set_cpu_possible(v, true);
90 set_cpu_present(v, true);
91 __cpu_number_map[v] = v;
92 __cpu_logical_map[v] = v;
95 /* Set a coherent default CCA (CWB) */
96 change_c0_config(CONF_CM_CMASK, 0x5);
98 /* Core 0 is powered up (we're running on it) */
99 bitmap_set(core_power, 0, 1);
101 /* Initialise core 0 */
102 mips_cps_core_init();
104 /* Make core 0 coherent with everything */
105 write_gcr_cl_coherence(0xff);
107 if (mips_cm_revision() >= CM_REV_CM3) {
108 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
109 write_gcr_bev_base(core_entry);
112 #ifdef CONFIG_MIPS_MT_FPAFF
113 /* If we have an FPU, enroll ourselves in the FPU-full mask */
115 cpumask_set_cpu(0, &mt_fpu_cpumask);
116 #endif /* CONFIG_MIPS_MT_FPAFF */
119 static void __init cps_prepare_cpus(unsigned int max_cpus)
121 unsigned ncores, core_vpes, c, cca;
125 mips_mt_set_cpuoptions();
127 /* Detect whether the CCA is unsuited to multi-core SMP */
128 cca = read_c0_config() & CONF_CM_CMASK;
132 /* The CCA is coherent, multi-core is fine */
133 cca_unsuitable = false;
137 /* CCA is not coherent, multi-core is not usable */
138 cca_unsuitable = true;
141 /* Warn the user if the CCA prevents multi-core */
142 ncores = mips_cm_numcores();
143 if (cca_unsuitable && ncores > 1) {
144 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
147 for_each_present_cpu(c) {
148 if (cpu_data[c].core)
149 set_cpu_present(c, false);
154 * Patch the start of mips_cps_core_entry to provide:
158 entry_code = (u32 *)&mips_cps_core_entry;
159 uasm_i_addiu(&entry_code, 16, 0, cca);
160 blast_dcache_range((unsigned long)&mips_cps_core_entry,
161 (unsigned long)entry_code);
162 bc_wback_inv((unsigned long)&mips_cps_core_entry,
163 (void *)entry_code - (void *)&mips_cps_core_entry);
166 /* Allocate core boot configuration structs */
167 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
169 if (!mips_cps_core_bootcfg) {
170 pr_err("Failed to allocate boot config for %u cores\n", ncores);
174 /* Allocate VPE boot configuration structs */
175 for (c = 0; c < ncores; c++) {
176 core_vpes = core_vpe_count(c);
177 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
178 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
180 if (!mips_cps_core_bootcfg[c].vpe_config) {
181 pr_err("Failed to allocate %u VPE boot configs\n",
187 /* Mark this CPU as booted */
188 atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
189 1 << cpu_vpe_id(¤t_cpu_data));
193 /* Clean up allocations */
194 if (mips_cps_core_bootcfg) {
195 for (c = 0; c < ncores; c++)
196 kfree(mips_cps_core_bootcfg[c].vpe_config);
197 kfree(mips_cps_core_bootcfg);
198 mips_cps_core_bootcfg = NULL;
201 /* Effectively disable SMP by declaring CPUs not present */
202 for_each_possible_cpu(c) {
205 set_cpu_present(c, false);
209 static void boot_core(unsigned core)
211 u32 access, stat, seq_state;
214 /* Select the appropriate core */
215 mips_cm_lock_other(core, 0);
217 /* Set its reset vector */
218 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
220 /* Ensure its coherency is disabled */
221 write_gcr_co_coherence(0);
223 /* Start it with the legacy memory map and exception base */
224 write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
226 /* Ensure the core can access the GCRs */
227 access = read_gcr_access();
228 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
229 write_gcr_access(access);
231 if (mips_cpc_present()) {
233 mips_cpc_lock_other(core);
235 if (mips_cm_revision() >= CM_REV_CM3) {
236 /* Run VP0 following the reset */
237 write_cpc_co_vp_run(0x1);
240 * Ensure that the VP_RUN register is written before the
246 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
250 stat = read_cpc_co_stat_conf();
251 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
253 /* U6 == coherent execution, ie. the core is up */
254 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
257 /* Delay a little while before we start warning */
264 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
269 mips_cpc_unlock_other();
271 /* Take the core out of reset */
272 write_gcr_co_reset_release(0);
275 mips_cm_unlock_other();
277 /* The core is now powered up */
278 bitmap_set(core_power, core, 1);
281 static void remote_vpe_boot(void *dummy)
283 unsigned core = current_cpu_data.core;
284 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
286 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
289 static void cps_boot_secondary(int cpu, struct task_struct *idle)
291 unsigned core = cpu_data[cpu].core;
292 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
293 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
294 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
295 unsigned long core_entry;
299 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
300 vpe_cfg->sp = __KSTK_TOS(idle);
301 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
303 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
307 if (!test_bit(core, core_power)) {
308 /* Boot a VPE on a powered down core */
314 mips_cm_lock_other(core, vpe_id);
315 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
316 write_gcr_co_reset_base(core_entry);
317 mips_cm_unlock_other();
320 if (core != current_cpu_data.core) {
321 /* Boot a VPE on another powered up core */
322 for (remote = 0; remote < NR_CPUS; remote++) {
323 if (cpu_data[remote].core != core)
325 if (cpu_online(remote))
328 BUG_ON(remote >= NR_CPUS);
330 err = smp_call_function_single(remote, remote_vpe_boot,
333 panic("Failed to call remote CPU\n");
337 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
339 /* Boot a VPE on this core */
340 mips_cps_boot_vpes(core_cfg, vpe_id);
345 static void cps_init_secondary(void)
347 /* Disable MT - we only want to run 1 TC per VPE */
351 if (mips_cm_revision() >= CM_REV_CM3) {
352 unsigned ident = gic_read_local_vp_id();
355 * Ensure that our calculation of the VP ID matches up with
356 * what the GIC reports, otherwise we'll have configured
357 * interrupts incorrectly.
359 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
363 clear_c0_status(ST0_IM);
365 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
366 STATUSF_IP4 | STATUSF_IP5 |
367 STATUSF_IP6 | STATUSF_IP7);
370 static void cps_smp_finish(void)
372 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
374 #ifdef CONFIG_MIPS_MT_FPAFF
375 /* If we have an FPU, enroll ourselves in the FPU-full mask */
377 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
378 #endif /* CONFIG_MIPS_MT_FPAFF */
383 #ifdef CONFIG_HOTPLUG_CPU
385 static int cps_cpu_disable(void)
387 unsigned cpu = smp_processor_id();
388 struct core_boot_config *core_cfg;
393 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
396 core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
397 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
398 smp_mb__after_atomic();
399 set_cpu_online(cpu, false);
400 cpumask_clear_cpu(cpu, &cpu_callin_map);
405 static DECLARE_COMPLETION(cpu_death_chosen);
406 static unsigned cpu_death_sibling;
418 cpu = smp_processor_id();
419 cpu_death = CPU_DEATH_POWER;
421 if (cpu_has_mipsmt) {
422 core = cpu_data[cpu].core;
424 /* Look for another online VPE within the core */
425 for_each_online_cpu(cpu_death_sibling) {
426 if (cpu_data[cpu_death_sibling].core != core)
430 * There is an online VPE within the core. Just halt
431 * this TC and leave the core alone.
433 cpu_death = CPU_DEATH_HALT;
438 /* This CPU has chosen its way out */
439 complete(&cpu_death_chosen);
441 if (cpu_death == CPU_DEATH_HALT) {
443 write_c0_tchalt(TCHALT_H);
444 instruction_hazard();
446 /* Power down the core */
447 cps_pm_enter_state(CPS_PM_POWER_GATED);
450 /* This should never be reached */
451 panic("Failed to offline CPU %u", cpu);
454 static void wait_for_sibling_halt(void *ptr_cpu)
456 unsigned cpu = (unsigned long)ptr_cpu;
457 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
462 local_irq_save(flags);
464 halted = read_tc_c0_tchalt();
465 local_irq_restore(flags);
466 } while (!(halted & TCHALT_H));
469 static void cps_cpu_die(unsigned int cpu)
471 unsigned core = cpu_data[cpu].core;
475 /* Wait for the cpu to choose its way out */
476 if (!wait_for_completion_timeout(&cpu_death_chosen,
477 msecs_to_jiffies(5000))) {
478 pr_err("CPU%u: didn't offline\n", cpu);
483 * Now wait for the CPU to actually offline. Without doing this that
484 * offlining may race with one or more of:
486 * - Onlining the CPU again.
487 * - Powering down the core if another VPE within it is offlined.
488 * - A sibling VPE entering a non-coherent state.
490 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
491 * with which we could race, so do nothing.
493 if (cpu_death == CPU_DEATH_POWER) {
495 * Wait for the core to enter a powered down or clock gated
496 * state, the latter happening when a JTAG probe is connected
497 * in which case the CPC will refuse to power down the core.
500 mips_cpc_lock_other(core);
501 stat = read_cpc_co_stat_conf();
502 stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
503 mips_cpc_unlock_other();
504 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
505 stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
506 stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
508 /* Indicate the core is powered off */
509 bitmap_clear(core_power, core, 1);
510 } else if (cpu_has_mipsmt) {
512 * Have a CPU with access to the offlined CPUs registers wait
513 * for its TC to halt.
515 err = smp_call_function_single(cpu_death_sibling,
516 wait_for_sibling_halt,
517 (void *)(unsigned long)cpu, 1);
519 panic("Failed to call remote sibling CPU\n");
523 #endif /* CONFIG_HOTPLUG_CPU */
525 static struct plat_smp_ops cps_smp_ops = {
526 .smp_setup = cps_smp_setup,
527 .prepare_cpus = cps_prepare_cpus,
528 .boot_secondary = cps_boot_secondary,
529 .init_secondary = cps_init_secondary,
530 .smp_finish = cps_smp_finish,
531 .send_ipi_single = mips_smp_send_ipi_single,
532 .send_ipi_mask = mips_smp_send_ipi_mask,
533 #ifdef CONFIG_HOTPLUG_CPU
534 .cpu_disable = cps_cpu_disable,
535 .cpu_die = cps_cpu_die,
539 bool mips_cps_smp_in_use(void)
541 extern struct plat_smp_ops *mp_ops;
542 return mp_ops == &cps_smp_ops;
545 int register_cps_smp_ops(void)
547 if (!mips_cm_present()) {
548 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
552 /* check we have a GIC - we need one for IPIs */
553 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
554 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
558 register_smp_ops(&cps_smp_ops);