arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/cpu-info.h>
  49 #include <asm/processor.h>
  50 #include <asm/fpu_emulator.h>
  51 #include <asm/fpu.h>
  52 #include <asm/mips-r2-to-r6-emul.h>
  53
  54 #include "ieee754.h"
  55
  56 /* Function which emulates a floating point instruction. */
  57
  58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  59         mips_instruction);
  60
  61 static int fpux_emu(struct pt_regs *,
  62         struct mips_fpu_struct *, mips_instruction, void *__user *);
  63
  64 /* Control registers */
  65
  66 #define FPCREG_RID      0       /* $0  = revision id */
  67 #define FPCREG_FCCR     25      /* $25 = fccr */
  68 #define FPCREG_FEXR     26      /* $26 = fexr */
  69 #define FPCREG_FENR     28      /* $28 = fenr */
  70 #define FPCREG_CSR      31      /* $31 = csr */
  71
  72 /* convert condition code register number to csr bit */
  73 const unsigned int fpucondbit[8] = {
  74         FPU_CSR_COND,
  75         FPU_CSR_COND1,
  76         FPU_CSR_COND2,
  77         FPU_CSR_COND3,
  78         FPU_CSR_COND4,
  79         FPU_CSR_COND5,
  80         FPU_CSR_COND6,
  81         FPU_CSR_COND7
  82 };
  83
  84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  89
  90 /*
  91  * This functions translates a 32-bit microMIPS instruction
  92  * into a 32-bit MIPS32 instruction. Returns 0 on success
  93  * and SIGILL otherwise.
  94  */
  95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  96 {
  97         union mips_instruction insn = *insn_ptr;
  98         union mips_instruction mips32_insn = insn;
  99         int func, fmt, op;
 100
 101         switch (insn.mm_i_format.opcode) {
 102         case mm_ldc132_op:
 103                 mips32_insn.mm_i_format.opcode = ldc1_op;
 104                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 105                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 106                 break;
 107         case mm_lwc132_op:
 108                 mips32_insn.mm_i_format.opcode = lwc1_op;
 109                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 110                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 111                 break;
 112         case mm_sdc132_op:
 113                 mips32_insn.mm_i_format.opcode = sdc1_op;
 114                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 115                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 116                 break;
 117         case mm_swc132_op:
 118                 mips32_insn.mm_i_format.opcode = swc1_op;
 119                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 120                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 121                 break;
 122         case mm_pool32i_op:
 123                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 124                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 125                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 126                         mips32_insn.fb_format.opcode = cop1_op;
 127                         mips32_insn.fb_format.bc = bc_op;
 128                         mips32_insn.fb_format.flag =
 129                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 130                 } else
 131                         return SIGILL;
 132                 break;
 133         case mm_pool32f_op:
 134                 switch (insn.mm_fp0_format.func) {
 135                 case mm_32f_01_op:
 136                 case mm_32f_11_op:
 137                 case mm_32f_02_op:
 138                 case mm_32f_12_op:
 139                 case mm_32f_41_op:
 140                 case mm_32f_51_op:
 141                 case mm_32f_42_op:
 142                 case mm_32f_52_op:
 143                         op = insn.mm_fp0_format.func;
 144                         if (op == mm_32f_01_op)
 145                                 func = madd_s_op;
 146                         else if (op == mm_32f_11_op)
 147                                 func = madd_d_op;
 148                         else if (op == mm_32f_02_op)
 149                                 func = nmadd_s_op;
 150                         else if (op == mm_32f_12_op)
 151                                 func = nmadd_d_op;
 152                         else if (op == mm_32f_41_op)
 153                                 func = msub_s_op;
 154                         else if (op == mm_32f_51_op)
 155                                 func = msub_d_op;
 156                         else if (op == mm_32f_42_op)
 157                                 func = nmsub_s_op;
 158                         else
 159                                 func = nmsub_d_op;
 160                         mips32_insn.fp6_format.opcode = cop1x_op;
 161                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 162                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 163                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 164                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 165                         mips32_insn.fp6_format.func = func;
 166                         break;
 167                 case mm_32f_10_op:
 168                         func = -1;      /* Invalid */
 169                         op = insn.mm_fp5_format.op & 0x7;
 170                         if (op == mm_ldxc1_op)
 171                                 func = ldxc1_op;
 172                         else if (op == mm_sdxc1_op)
 173                                 func = sdxc1_op;
 174                         else if (op == mm_lwxc1_op)
 175                                 func = lwxc1_op;
 176                         else if (op == mm_swxc1_op)
 177                                 func = swxc1_op;
 178
 179                         if (func != -1) {
 180                                 mips32_insn.r_format.opcode = cop1x_op;
 181                                 mips32_insn.r_format.rs =
 182                                         insn.mm_fp5_format.base;
 183                                 mips32_insn.r_format.rt =
 184                                         insn.mm_fp5_format.index;
 185                                 mips32_insn.r_format.rd = 0;
 186                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 187                                 mips32_insn.r_format.func = func;
 188                         } else
 189                                 return SIGILL;
 190                         break;
 191                 case mm_32f_40_op:
 192                         op = -1;        /* Invalid */
 193                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 194                                 op = 1;
 195                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 196                                 op = 0;
 197                         if (op != -1) {
 198                                 mips32_insn.fp0_format.opcode = cop1_op;
 199                                 mips32_insn.fp0_format.fmt =
 200                                         sdps_format[insn.mm_fp2_format.fmt];
 201                                 mips32_insn.fp0_format.ft =
 202                                         (insn.mm_fp2_format.cc<<2) + op;
 203                                 mips32_insn.fp0_format.fs =
 204                                         insn.mm_fp2_format.fs;
 205                                 mips32_insn.fp0_format.fd =
 206                                         insn.mm_fp2_format.fd;
 207                                 mips32_insn.fp0_format.func = fmovc_op;
 208                         } else
 209                                 return SIGILL;
 210                         break;
 211                 case mm_32f_60_op:
 212                         func = -1;      /* Invalid */
 213                         if (insn.mm_fp0_format.op == mm_fadd_op)
 214                                 func = fadd_op;
 215                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 216                                 func = fsub_op;
 217                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 218                                 func = fmul_op;
 219                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 220                                 func = fdiv_op;
 221                         if (func != -1) {
 222                                 mips32_insn.fp0_format.opcode = cop1_op;
 223                                 mips32_insn.fp0_format.fmt =
 224                                         sdps_format[insn.mm_fp0_format.fmt];
 225                                 mips32_insn.fp0_format.ft =
 226                                         insn.mm_fp0_format.ft;
 227                                 mips32_insn.fp0_format.fs =
 228                                         insn.mm_fp0_format.fs;
 229                                 mips32_insn.fp0_format.fd =
 230                                         insn.mm_fp0_format.fd;
 231                                 mips32_insn.fp0_format.func = func;
 232                         } else
 233                                 return SIGILL;
 234                         break;
 235                 case mm_32f_70_op:
 236                         func = -1;      /* Invalid */
 237                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 238                                 func = fmovn_op;
 239                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 240                                 func = fmovz_op;
 241                         if (func != -1) {
 242                                 mips32_insn.fp0_format.opcode = cop1_op;
 243                                 mips32_insn.fp0_format.fmt =
 244                                         sdps_format[insn.mm_fp0_format.fmt];
 245                                 mips32_insn.fp0_format.ft =
 246                                         insn.mm_fp0_format.ft;
 247                                 mips32_insn.fp0_format.fs =
 248                                         insn.mm_fp0_format.fs;
 249                                 mips32_insn.fp0_format.fd =
 250                                         insn.mm_fp0_format.fd;
 251                                 mips32_insn.fp0_format.func = func;
 252                         } else
 253                                 return SIGILL;
 254                         break;
 255                 case mm_32f_73_op:    /* POOL32FXF */
 256                         switch (insn.mm_fp1_format.op) {
 257                         case mm_movf0_op:
 258                         case mm_movf1_op:
 259                         case mm_movt0_op:
 260                         case mm_movt1_op:
 261                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 262                                     mm_movf0_op)
 263                                         op = 0;
 264                                 else
 265                                         op = 1;
 266                                 mips32_insn.r_format.opcode = spec_op;
 267                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 268                                 mips32_insn.r_format.rt =
 269                                         (insn.mm_fp4_format.cc << 2) + op;
 270                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 271                                 mips32_insn.r_format.re = 0;
 272                                 mips32_insn.r_format.func = movc_op;
 273                                 break;
 274                         case mm_fcvtd0_op:
 275                         case mm_fcvtd1_op:
 276                         case mm_fcvts0_op:
 277                         case mm_fcvts1_op:
 278                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 279                                     mm_fcvtd0_op) {
 280                                         func = fcvtd_op;
 281                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 282                                 } else {
 283                                         func = fcvts_op;
 284                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 285                                 }
 286                                 mips32_insn.fp0_format.opcode = cop1_op;
 287                                 mips32_insn.fp0_format.fmt = fmt;
 288                                 mips32_insn.fp0_format.ft = 0;
 289                                 mips32_insn.fp0_format.fs =
 290                                         insn.mm_fp3_format.fs;
 291                                 mips32_insn.fp0_format.fd =
 292                                         insn.mm_fp3_format.rt;
 293                                 mips32_insn.fp0_format.func = func;
 294                                 break;
 295                         case mm_fmov0_op:
 296                         case mm_fmov1_op:
 297                         case mm_fabs0_op:
 298                         case mm_fabs1_op:
 299                         case mm_fneg0_op:
 300                         case mm_fneg1_op:
 301                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 302                                     mm_fmov0_op)
 303                                         func = fmov_op;
 304                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 305                                          mm_fabs0_op)
 306                                         func = fabs_op;
 307                                 else
 308                                         func = fneg_op;
 309                                 mips32_insn.fp0_format.opcode = cop1_op;
 310                                 mips32_insn.fp0_format.fmt =
 311                                         sdps_format[insn.mm_fp3_format.fmt];
 312                                 mips32_insn.fp0_format.ft = 0;
 313                                 mips32_insn.fp0_format.fs =
 314                                         insn.mm_fp3_format.fs;
 315                                 mips32_insn.fp0_format.fd =
 316                                         insn.mm_fp3_format.rt;
 317                                 mips32_insn.fp0_format.func = func;
 318                                 break;
 319                         case mm_ffloorl_op:
 320                         case mm_ffloorw_op:
 321                         case mm_fceill_op:
 322                         case mm_fceilw_op:
 323                         case mm_ftruncl_op:
 324                         case mm_ftruncw_op:
 325                         case mm_froundl_op:
 326                         case mm_froundw_op:
 327                         case mm_fcvtl_op:
 328                         case mm_fcvtw_op:
 329                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 330                                         func = ffloorl_op;
 331                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 332                                         func = ffloor_op;
 333                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 334                                         func = fceill_op;
 335                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 336                                         func = fceil_op;
 337                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 338                                         func = ftruncl_op;
 339                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 340                                         func = ftrunc_op;
 341                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 342                                         func = froundl_op;
 343                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 344                                         func = fround_op;
 345                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 346                                         func = fcvtl_op;
 347                                 else
 348                                         func = fcvtw_op;
 349                                 mips32_insn.fp0_format.opcode = cop1_op;
 350                                 mips32_insn.fp0_format.fmt =
 351                                         sd_format[insn.mm_fp1_format.fmt];
 352                                 mips32_insn.fp0_format.ft = 0;
 353                                 mips32_insn.fp0_format.fs =
 354                                         insn.mm_fp1_format.fs;
 355                                 mips32_insn.fp0_format.fd =
 356                                         insn.mm_fp1_format.rt;
 357                                 mips32_insn.fp0_format.func = func;
 358                                 break;
 359                         case mm_frsqrt_op:
 360                         case mm_fsqrt_op:
 361                         case mm_frecip_op:
 362                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 363                                         func = frsqrt_op;
 364                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 365                                         func = fsqrt_op;
 366                                 else
 367                                         func = frecip_op;
 368                                 mips32_insn.fp0_format.opcode = cop1_op;
 369                                 mips32_insn.fp0_format.fmt =
 370                                         sdps_format[insn.mm_fp1_format.fmt];
 371                                 mips32_insn.fp0_format.ft = 0;
 372                                 mips32_insn.fp0_format.fs =
 373                                         insn.mm_fp1_format.fs;
 374                                 mips32_insn.fp0_format.fd =
 375                                         insn.mm_fp1_format.rt;
 376                                 mips32_insn.fp0_format.func = func;
 377                                 break;
 378                         case mm_mfc1_op:
 379                         case mm_mtc1_op:
 380                         case mm_cfc1_op:
 381                         case mm_ctc1_op:
 382                         case mm_mfhc1_op:
 383                         case mm_mthc1_op:
 384                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 385                                         op = mfc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 387                                         op = mtc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 389                                         op = cfc_op;
 390                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 391                                         op = ctc_op;
 392                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 393                                         op = mfhc_op;
 394                                 else
 395                                         op = mthc_op;
 396                                 mips32_insn.fp1_format.opcode = cop1_op;
 397                                 mips32_insn.fp1_format.op = op;
 398                                 mips32_insn.fp1_format.rt =
 399                                         insn.mm_fp1_format.rt;
 400                                 mips32_insn.fp1_format.fs =
 401                                         insn.mm_fp1_format.fs;
 402                                 mips32_insn.fp1_format.fd = 0;
 403                                 mips32_insn.fp1_format.func = 0;
 404                                 break;
 405                         default:
 406                                 return SIGILL;
 407                         }
 408                         break;
 409                 case mm_32f_74_op:      /* c.cond.fmt */
 410                         mips32_insn.fp0_format.opcode = cop1_op;
 411                         mips32_insn.fp0_format.fmt =
 412                                 sdps_format[insn.mm_fp4_format.fmt];
 413                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 414                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 415                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 416                         mips32_insn.fp0_format.func =
 417                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 418                         break;
 419                 default:
 420                         return SIGILL;
 421                 }
 422                 break;
 423         default:
 424                 return SIGILL;
 425         }
 426
 427         *insn_ptr = mips32_insn;
 428         return 0;
 429 }
 430
 431 /*
 432  * Redundant with logic already in kernel/branch.c,
 433  * embedded in compute_return_epc.  At some point,
 434  * a single subroutine should be used across both
 435  * modules.
 436  */
 437 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 438                   unsigned long *contpc)
 439 {
 440         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 441         unsigned int fcr31;
 442         unsigned int bit = 0;
 443
 444         switch (insn.i_format.opcode) {
 445         case spec_op:
 446                 switch (insn.r_format.func) {
 447                 case jalr_op:
 448                         if (insn.r_format.rd != 0) {
 449                                 regs->regs[insn.r_format.rd] =
 450                                         regs->cp0_epc + dec_insn.pc_inc +
 451                                         dec_insn.next_pc_inc;
 452                         }
 453                         /* Fall through */
 454                 case jr_op:
 455                         /* For R6, JR already emulated in jalr_op */
 456                         if (NO_R6EMU && insn.r_format.func == jr_op)
 457                                 break;
 458                         *contpc = regs->regs[insn.r_format.rs];
 459                         return 1;
 460                 }
 461                 break;
 462         case bcond_op:
 463                 switch (insn.i_format.rt) {
 464                 case bltzal_op:
 465                 case bltzall_op:
 466                         if (NO_R6EMU && (insn.i_format.rs ||
 467                             insn.i_format.rt == bltzall_op))
 468                                 break;
 469
 470                         regs->regs[31] = regs->cp0_epc +
 471                                 dec_insn.pc_inc +
 472                                 dec_insn.next_pc_inc;
 473                         /* Fall through */
 474                 case bltzl_op:
 475                         if (NO_R6EMU)
 476                                 break;
 477                 case bltz_op:
 478                         if ((long)regs->regs[insn.i_format.rs] < 0)
 479                                 *contpc = regs->cp0_epc +
 480                                         dec_insn.pc_inc +
 481                                         (insn.i_format.simmediate << 2);
 482                         else
 483                                 *contpc = regs->cp0_epc +
 484                                         dec_insn.pc_inc +
 485                                         dec_insn.next_pc_inc;
 486                         return 1;
 487                 case bgezal_op:
 488                 case bgezall_op:
 489                         if (NO_R6EMU && (insn.i_format.rs ||
 490                             insn.i_format.rt == bgezall_op))
 491                                 break;
 492
 493                         regs->regs[31] = regs->cp0_epc +
 494                                 dec_insn.pc_inc +
 495                                 dec_insn.next_pc_inc;
 496                         /* Fall through */
 497                 case bgezl_op:
 498                         if (NO_R6EMU)
 499                                 break;
 500                 case bgez_op:
 501                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 502                                 *contpc = regs->cp0_epc +
 503                                         dec_insn.pc_inc +
 504                                         (insn.i_format.simmediate << 2);
 505                         else
 506                                 *contpc = regs->cp0_epc +
 507                                         dec_insn.pc_inc +
 508                                         dec_insn.next_pc_inc;
 509                         return 1;
 510                 }
 511                 break;
 512         case jalx_op:
 513                 set_isa16_mode(bit);
 514         case jal_op:
 515                 regs->regs[31] = regs->cp0_epc +
 516                         dec_insn.pc_inc +
 517                         dec_insn.next_pc_inc;
 518                 /* Fall through */
 519         case j_op:
 520                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 521                 *contpc >>= 28;
 522                 *contpc <<= 28;
 523                 *contpc |= (insn.j_format.target << 2);
 524                 /* Set microMIPS mode bit: XOR for jalx. */
 525                 *contpc ^= bit;
 526                 return 1;
 527         case beql_op:
 528                 if (NO_R6EMU)
 529                         break;
 530         case beq_op:
 531                 if (regs->regs[insn.i_format.rs] ==
 532                     regs->regs[insn.i_format.rt])
 533                         *contpc = regs->cp0_epc +
 534                                 dec_insn.pc_inc +
 535                                 (insn.i_format.simmediate << 2);
 536                 else
 537                         *contpc = regs->cp0_epc +
 538                                 dec_insn.pc_inc +
 539                                 dec_insn.next_pc_inc;
 540                 return 1;
 541         case bnel_op:
 542                 if (NO_R6EMU)
 543                         break;
 544         case bne_op:
 545                 if (regs->regs[insn.i_format.rs] !=
 546                     regs->regs[insn.i_format.rt])
 547                         *contpc = regs->cp0_epc +
 548                                 dec_insn.pc_inc +
 549                                 (insn.i_format.simmediate << 2);
 550                 else
 551                         *contpc = regs->cp0_epc +
 552                                 dec_insn.pc_inc +
 553                                 dec_insn.next_pc_inc;
 554                 return 1;
 555         case blezl_op:
 556                 if (!insn.i_format.rt && NO_R6EMU)
 557                         break;
 558         case blez_op:
 559
 560                 /*
 561                  * Compact branches for R6 for the
 562                  * blez and blezl opcodes.
 563                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 564                  * BLEZ  | rs = rt != 0      == BGEZALC
 565                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 566                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 567                  * BLEZL | rs = rt != 0      == BGEZC
 568                  * BLEZL | rs != 0 | rt != 0 == BGEC
 569                  *
 570                  * For real BLEZ{,L}, rt is always 0.
 571                  */
 572                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 573                         if ((insn.i_format.opcode == blez_op) &&
 574                             ((!insn.i_format.rs && insn.i_format.rt) ||
 575                              (insn.i_format.rs == insn.i_format.rt)))
 576                                 regs->regs[31] = regs->cp0_epc +
 577                                         dec_insn.pc_inc;
 578                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 579                                 dec_insn.next_pc_inc;
 580
 581                         return 1;
 582                 }
 583                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 584                         *contpc = regs->cp0_epc +
 585                                 dec_insn.pc_inc +
 586                                 (insn.i_format.simmediate << 2);
 587                 else
 588                         *contpc = regs->cp0_epc +
 589                                 dec_insn.pc_inc +
 590                                 dec_insn.next_pc_inc;
 591                 return 1;
 592         case bgtzl_op:
 593                 if (!insn.i_format.rt && NO_R6EMU)
 594                         break;
 595         case bgtz_op:
 596                 /*
 597                  * Compact branches for R6 for the
 598                  * bgtz and bgtzl opcodes.
 599                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 600                  * BGTZ  | rs = rt != 0      == BLTZALC
 601                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 602                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 603                  * BGTZL | rs = rt != 0      == BLTZC
 604                  * BGTZL | rs != 0 | rt != 0 == BLTC
 605                  *
 606                  * *ZALC varint for BGTZ &&& rt != 0
 607                  * For real GTZ{,L}, rt is always 0.
 608                  */
 609                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 610                         if ((insn.i_format.opcode == blez_op) &&
 611                             ((!insn.i_format.rs && insn.i_format.rt) ||
 612                              (insn.i_format.rs == insn.i_format.rt)))
 613                                 regs->regs[31] = regs->cp0_epc +
 614                                         dec_insn.pc_inc;
 615                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 616                                 dec_insn.next_pc_inc;
 617
 618                         return 1;
 619                 }
 620
 621                 if ((long)regs->regs[insn.i_format.rs] > 0)
 622                         *contpc = regs->cp0_epc +
 623                                 dec_insn.pc_inc +
 624                                 (insn.i_format.simmediate << 2);
 625                 else
 626                         *contpc = regs->cp0_epc +
 627                                 dec_insn.pc_inc +
 628                                 dec_insn.next_pc_inc;
 629                 return 1;
 630         case cbcond0_op:
 631         case cbcond1_op:
 632                 if (!cpu_has_mips_r6)
 633                         break;
 634                 if (insn.i_format.rt && !insn.i_format.rs)
 635                         regs->regs[31] = regs->cp0_epc + 4;
 636                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 637                         dec_insn.next_pc_inc;
 638
 639                 return 1;
 640 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 641         case lwc2_op: /* This is bbit0 on Octeon */
 642                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 643                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 644                 else
 645                         *contpc = regs->cp0_epc + 8;
 646                 return 1;
 647         case ldc2_op: /* This is bbit032 on Octeon */
 648                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 649                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 650                 else
 651                         *contpc = regs->cp0_epc + 8;
 652                 return 1;
 653         case swc2_op: /* This is bbit1 on Octeon */
 654                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 655                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 656                 else
 657                         *contpc = regs->cp0_epc + 8;
 658                 return 1;
 659         case sdc2_op: /* This is bbit132 on Octeon */
 660                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 661                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 662                 else
 663                         *contpc = regs->cp0_epc + 8;
 664                 return 1;
 665 #else
 666         case bc6_op:
 667                 /*
 668                  * Only valid for MIPS R6 but we can still end up
 669                  * here from a broken userland so just tell emulator
 670                  * this is not a branch and let it break later on.
 671                  */
 672                 if  (!cpu_has_mips_r6)
 673                         break;
 674                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 675                         dec_insn.next_pc_inc;
 676
 677                 return 1;
 678         case balc6_op:
 679                 if (!cpu_has_mips_r6)
 680                         break;
 681                 regs->regs[31] = regs->cp0_epc + 4;
 682                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 683                         dec_insn.next_pc_inc;
 684
 685                 return 1;
 686         case beqzcjic_op:
 687                 if (!cpu_has_mips_r6)
 688                         break;
 689                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 690                         dec_insn.next_pc_inc;
 691
 692                 return 1;
 693         case bnezcjialc_op:
 694                 if (!cpu_has_mips_r6)
 695                         break;
 696                 if (!insn.i_format.rs)
 697                         regs->regs[31] = regs->cp0_epc + 4;
 698                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 699                         dec_insn.next_pc_inc;
 700
 701                 return 1;
 702 #endif
 703         case cop0_op:
 704         case cop1_op:
 705                 /* Need to check for R6 bc1nez and bc1eqz branches */
 706                 if (cpu_has_mips_r6 &&
 707                     ((insn.i_format.rs == bc1eqz_op) ||
 708                      (insn.i_format.rs == bc1nez_op))) {
 709                         bit = 0;
 710                         switch (insn.i_format.rs) {
 711                         case bc1eqz_op:
 712                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
 713                                     bit = 1;
 714                                 break;
 715                         case bc1nez_op:
 716                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
 717                                     bit = 1;
 718                                 break;
 719                         }
 720                         if (bit)
 721                                 *contpc = regs->cp0_epc +
 722                                         dec_insn.pc_inc +
 723                                         (insn.i_format.simmediate << 2);
 724                         else
 725                                 *contpc = regs->cp0_epc +
 726                                         dec_insn.pc_inc +
 727                                         dec_insn.next_pc_inc;
 728
 729                         return 1;
 730                 }
 731                 /* R2/R6 compatible cop1 instruction. Fall through */
 732         case cop2_op:
 733         case cop1x_op:
 734                 if (insn.i_format.rs == bc_op) {
 735                         preempt_disable();
 736                         if (is_fpu_owner())
 737                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 738                         else
 739                                 fcr31 = current->thread.fpu.fcr31;
 740                         preempt_enable();
 741
 742                         bit = (insn.i_format.rt >> 2);
 743                         bit += (bit != 0);
 744                         bit += 23;
 745                         switch (insn.i_format.rt & 3) {
 746                         case 0: /* bc1f */
 747                         case 2: /* bc1fl */
 748                                 if (~fcr31 & (1 << bit))
 749                                         *contpc = regs->cp0_epc +
 750                                                 dec_insn.pc_inc +
 751                                                 (insn.i_format.simmediate << 2);
 752                                 else
 753                                         *contpc = regs->cp0_epc +
 754                                                 dec_insn.pc_inc +
 755                                                 dec_insn.next_pc_inc;
 756                                 return 1;
 757                         case 1: /* bc1t */
 758                         case 3: /* bc1tl */
 759                                 if (fcr31 & (1 << bit))
 760                                         *contpc = regs->cp0_epc +
 761                                                 dec_insn.pc_inc +
 762                                                 (insn.i_format.simmediate << 2);
 763                                 else
 764                                         *contpc = regs->cp0_epc +
 765                                                 dec_insn.pc_inc +
 766                                                 dec_insn.next_pc_inc;
 767                                 return 1;
 768                         }
 769                 }
 770                 break;
 771         }
 772         return 0;
 773 }
 774
 775 /*
 776  * In the Linux kernel, we support selection of FPR format on the
 777  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 778  * is hardwired to zero, which would imply a 32-bit FPU even for
 779  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 780  * FPU emu is slow and bulky and optimizing this function offers fairly
 781  * sizeable benefits so we try to be clever and make this function return
 782  * a constant whenever possible, that is on 64-bit kernels without O32
 783  * compatibility enabled and on 32-bit without 64-bit FPU support.
 784  */
 785 static inline int cop1_64bit(struct pt_regs *xcp)
 786 {
 787         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 788                 return 1;
 789         else if (config_enabled(CONFIG_32BIT) &&
 790                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 791                 return 0;
 792
 793         return !test_thread_flag(TIF_32BIT_FPREGS);
 794 }
 795
 796 static inline bool hybrid_fprs(void)
 797 {
 798         return test_thread_flag(TIF_HYBRID_FPREGS);
 799 }
 800
 801 #define SIFROMREG(si, x)                                                \
 802 do {                                                                    \
 803         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 804                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 805         else                                                            \
 806                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 807 } while (0)
 808
 809 #define SITOREG(si, x)                                                  \
 810 do {                                                                    \
 811         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 812                 unsigned i;                                             \
 813                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 814                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 815                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 816         } else {                                                        \
 817                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 818         }                                                               \
 819 } while (0)
 820
 821 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 822
 823 #define SITOHREG(si, x)                                                 \
 824 do {                                                                    \
 825         unsigned i;                                                     \
 826         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 827         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 828                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 829 } while (0)
 830
 831 #define DIFROMREG(di, x)                                                \
 832         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 833
 834 #define DITOREG(di, x)                                                  \
 835 do {                                                                    \
 836         unsigned fpr, i;                                                \
 837         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 838         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 839         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 840                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 841 } while (0)
 842
 843 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 844 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 845 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 846 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 847
 848 /*
 849  * Emulate a CFC1 instruction.
 850  */
 851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 852                             mips_instruction ir)
 853 {
 854         u32 fcr31 = ctx->fcr31;
 855         u32 value = 0;
 856
 857         switch (MIPSInst_RD(ir)) {
 858         case FPCREG_CSR:
 859                 value = fcr31;
 860                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 861                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 862                 break;
 863
 864         case FPCREG_FENR:
 865                 if (!cpu_has_mips_r)
 866                         break;
 867                 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 868                         MIPS_FENR_FS;
 869                 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
 870                 pr_debug("%p gpr[%d]<-enr=%08x\n",
 871                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 872                 break;
 873
 874         case FPCREG_FEXR:
 875                 if (!cpu_has_mips_r)
 876                         break;
 877                 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 878                 pr_debug("%p gpr[%d]<-exr=%08x\n",
 879                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 880                 break;
 881
 882         case FPCREG_FCCR:
 883                 if (!cpu_has_mips_r)
 884                         break;
 885                 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 886                         MIPS_FCCR_COND0;
 887                 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 888                          (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
 889                 pr_debug("%p gpr[%d]<-ccr=%08x\n",
 890                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 891                 break;
 892
 893         case FPCREG_RID:
 894                 value = boot_cpu_data.fpu_id;
 895                 break;
 896
 897         default:
 898                 break;
 899         }
 900
 901         if (MIPSInst_RT(ir))
 902                 xcp->regs[MIPSInst_RT(ir)] = value;
 903 }
 904
 905 /*
 906  * Emulate a CTC1 instruction.
 907  */
 908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 909                             mips_instruction ir)
 910 {
 911         u32 fcr31 = ctx->fcr31;
 912         u32 value;
 913         u32 mask;
 914
 915         if (MIPSInst_RT(ir) == 0)
 916                 value = 0;
 917         else
 918                 value = xcp->regs[MIPSInst_RT(ir)];
 919
 920         switch (MIPSInst_RD(ir)) {
 921         case FPCREG_CSR:
 922                 pr_debug("%p gpr[%d]->csr=%08x\n",
 923                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 924
 925                 /* Preserve read-only bits.  */
 926                 mask = boot_cpu_data.fpu_msk31;
 927                 fcr31 = (value & ~mask) | (fcr31 & mask);
 928                 break;
 929
 930         case FPCREG_FENR:
 931                 if (!cpu_has_mips_r)
 932                         break;
 933                 pr_debug("%p gpr[%d]->enr=%08x\n",
 934                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 935                 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
 936                 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 937                          FPU_CSR_FS;
 938                 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
 939                 break;
 940
 941         case FPCREG_FEXR:
 942                 if (!cpu_has_mips_r)
 943                         break;
 944                 pr_debug("%p gpr[%d]->exr=%08x\n",
 945                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 946                 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 947                 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 948                 break;
 949
 950         case FPCREG_FCCR:
 951                 if (!cpu_has_mips_r)
 952                         break;
 953                 pr_debug("%p gpr[%d]->ccr=%08x\n",
 954                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 955                 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
 956                 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 957                          FPU_CSR_COND;
 958                 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 959                          FPU_CSR_CONDX;
 960                 break;
 961
 962         default:
 963                 break;
 964         }
 965
 966         ctx->fcr31 = fcr31;
 967 }
 968
 969 /*
 970  * Emulate the single floating point instruction pointed at by EPC.
 971  * Two instructions if the instruction is in a branch delay slot.
 972  */
 973
 974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 975                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 976 {
 977         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 978         unsigned int cond, cbit, bit0;
 979         mips_instruction ir;
 980         int likely, pc_inc;
 981         union fpureg *fpr;
 982         u32 __user *wva;
 983         u64 __user *dva;
 984         u32 wval;
 985         u64 dval;
 986         int sig;
 987
 988         /*
 989          * These are giving gcc a gentle hint about what to expect in
 990          * dec_inst in order to do better optimization.
 991          */
 992         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 993                 unreachable();
 994
 995         /* XXX NEC Vr54xx bug workaround */
 996         if (delay_slot(xcp)) {
 997                 if (dec_insn.micro_mips_mode) {
 998                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 999                                 clear_delay_slot(xcp);
1000                 } else {
1001                         if (!isBranchInstr(xcp, dec_insn, &contpc))
1002                                 clear_delay_slot(xcp);
1003                 }
1004         }
1005
1006         if (delay_slot(xcp)) {
1007                 /*
1008                  * The instruction to be emulated is in a branch delay slot
1009                  * which means that we have to  emulate the branch instruction
1010                  * BEFORE we do the cop1 instruction.
1011                  *
1012                  * This branch could be a COP1 branch, but in that case we
1013                  * would have had a trap for that instruction, and would not
1014                  * come through this route.
1015                  *
1016                  * Linux MIPS branch emulator operates on context, updating the
1017                  * cp0_epc.
1018                  */
1019                 ir = dec_insn.next_insn;  /* process delay slot instr */
1020                 pc_inc = dec_insn.next_pc_inc;
1021         } else {
1022                 ir = dec_insn.insn;       /* process current instr */
1023                 pc_inc = dec_insn.pc_inc;
1024         }
1025
1026         /*
1027          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1028          * instructions, we want to convert microMIPS FPU instructions
1029          * into MIPS32 instructions so that we could reuse all of the
1030          * FPU emulation code.
1031          *
1032          * NOTE: We cannot do this for branch instructions since they
1033          *       are not a subset. Example: Cannot emulate a 16-bit
1034          *       aligned target address with a MIPS32 instruction.
1035          */
1036         if (dec_insn.micro_mips_mode) {
1037                 /*
1038                  * If next instruction is a 16-bit instruction, then it
1039                  * it cannot be a FPU instruction. This could happen
1040                  * since we can be called for non-FPU instructions.
1041                  */
1042                 if ((pc_inc == 2) ||
1043                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1044                          == SIGILL))
1045                         return SIGILL;
1046         }
1047
1048 emul:
1049         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1050         MIPS_FPU_EMU_INC_STATS(emulated);
1051         switch (MIPSInst_OPCODE(ir)) {
1052         case ldc1_op:
1053                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1054                                      MIPSInst_SIMM(ir));
1055                 MIPS_FPU_EMU_INC_STATS(loads);
1056
1057                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1058                         MIPS_FPU_EMU_INC_STATS(errors);
1059                         *fault_addr = dva;
1060                         return SIGBUS;
1061                 }
1062                 if (__get_user(dval, dva)) {
1063                         MIPS_FPU_EMU_INC_STATS(errors);
1064                         *fault_addr = dva;
1065                         return SIGSEGV;
1066                 }
1067                 DITOREG(dval, MIPSInst_RT(ir));
1068                 break;
1069
1070         case sdc1_op:
1071                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1072                                       MIPSInst_SIMM(ir));
1073                 MIPS_FPU_EMU_INC_STATS(stores);
1074                 DIFROMREG(dval, MIPSInst_RT(ir));
1075                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1076                         MIPS_FPU_EMU_INC_STATS(errors);
1077                         *fault_addr = dva;
1078                         return SIGBUS;
1079                 }
1080                 if (__put_user(dval, dva)) {
1081                         MIPS_FPU_EMU_INC_STATS(errors);
1082                         *fault_addr = dva;
1083                         return SIGSEGV;
1084                 }
1085                 break;
1086
1087         case lwc1_op:
1088                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1089                                       MIPSInst_SIMM(ir));
1090                 MIPS_FPU_EMU_INC_STATS(loads);
1091                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1092                         MIPS_FPU_EMU_INC_STATS(errors);
1093                         *fault_addr = wva;
1094                         return SIGBUS;
1095                 }
1096                 if (__get_user(wval, wva)) {
1097                         MIPS_FPU_EMU_INC_STATS(errors);
1098                         *fault_addr = wva;
1099                         return SIGSEGV;
1100                 }
1101                 SITOREG(wval, MIPSInst_RT(ir));
1102                 break;
1103
1104         case swc1_op:
1105                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1106                                       MIPSInst_SIMM(ir));
1107                 MIPS_FPU_EMU_INC_STATS(stores);
1108                 SIFROMREG(wval, MIPSInst_RT(ir));
1109                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1110                         MIPS_FPU_EMU_INC_STATS(errors);
1111                         *fault_addr = wva;
1112                         return SIGBUS;
1113                 }
1114                 if (__put_user(wval, wva)) {
1115                         MIPS_FPU_EMU_INC_STATS(errors);
1116                         *fault_addr = wva;
1117                         return SIGSEGV;
1118                 }
1119                 break;
1120
1121         case cop1_op:
1122                 switch (MIPSInst_RS(ir)) {
1123                 case dmfc_op:
1124                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1125                                 return SIGILL;
1126
1127                         /* copregister fs -> gpr[rt] */
1128                         if (MIPSInst_RT(ir) != 0) {
1129                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1130                                         MIPSInst_RD(ir));
1131                         }
1132                         break;
1133
1134                 case dmtc_op:
1135                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1136                                 return SIGILL;
1137
1138                         /* copregister fs <- rt */
1139                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1140                         break;
1141
1142                 case mfhc_op:
1143                         if (!cpu_has_mips_r2_r6)
1144                                 goto sigill;
1145
1146                         /* copregister rd -> gpr[rt] */
1147                         if (MIPSInst_RT(ir) != 0) {
1148                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1149                                         MIPSInst_RD(ir));
1150                         }
1151                         break;
1152
1153                 case mthc_op:
1154                         if (!cpu_has_mips_r2_r6)
1155                                 goto sigill;
1156
1157                         /* copregister rd <- gpr[rt] */
1158                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1159                         break;
1160
1161                 case mfc_op:
1162                         /* copregister rd -> gpr[rt] */
1163                         if (MIPSInst_RT(ir) != 0) {
1164                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1165                                         MIPSInst_RD(ir));
1166                         }
1167                         break;
1168
1169                 case mtc_op:
1170                         /* copregister rd <- rt */
1171                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1172                         break;
1173
1174                 case cfc_op:
1175                         /* cop control register rd -> gpr[rt] */
1176                         cop1_cfc(xcp, ctx, ir);
1177                         break;
1178
1179                 case ctc_op:
1180                         /* copregister rd <- rt */
1181                         cop1_ctc(xcp, ctx, ir);
1182                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1183                                 return SIGFPE;
1184                         }
1185                         break;
1186
1187                 case bc1eqz_op:
1188                 case bc1nez_op:
1189                         if (!cpu_has_mips_r6 || delay_slot(xcp))
1190                                 return SIGILL;
1191
1192                         cond = likely = 0;
1193                         fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1194                         bit0 = get_fpr32(fpr, 0) & 0x1;
1195                         switch (MIPSInst_RS(ir)) {
1196                         case bc1eqz_op:
1197                                 cond = bit0 == 0;
1198                                 break;
1199                         case bc1nez_op:
1200                                 cond = bit0 != 0;
1201                                 break;
1202                         }
1203                         goto branch_common;
1204
1205                 case bc_op:
1206                         if (delay_slot(xcp))
1207                                 return SIGILL;
1208
1209                         if (cpu_has_mips_4_5_r)
1210                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1211                         else
1212                                 cbit = FPU_CSR_COND;
1213                         cond = ctx->fcr31 & cbit;
1214
1215                         likely = 0;
1216                         switch (MIPSInst_RT(ir) & 3) {
1217                         case bcfl_op:
1218                                 if (cpu_has_mips_2_3_4_5_r)
1219                                         likely = 1;
1220                                 /* Fall through */
1221                         case bcf_op:
1222                                 cond = !cond;
1223                                 break;
1224                         case bctl_op:
1225                                 if (cpu_has_mips_2_3_4_5_r)
1226                                         likely = 1;
1227                                 /* Fall through */
1228                         case bct_op:
1229                                 break;
1230                         }
1231 branch_common:
1232                         set_delay_slot(xcp);
1233                         if (cond) {
1234                                 /*
1235                                  * Branch taken: emulate dslot instruction
1236                                  */
1237                                 unsigned long bcpc;
1238
1239                                 /*
1240                                  * Remember EPC at the branch to point back
1241                                  * at so that any delay-slot instruction
1242                                  * signal is not silently ignored.
1243                                  */
1244                                 bcpc = xcp->cp0_epc;
1245                                 xcp->cp0_epc += dec_insn.pc_inc;
1246
1247                                 contpc = MIPSInst_SIMM(ir);
1248                                 ir = dec_insn.next_insn;
1249                                 if (dec_insn.micro_mips_mode) {
1250                                         contpc = (xcp->cp0_epc + (contpc << 1));
1251
1252                                         /* If 16-bit instruction, not FPU. */
1253                                         if ((dec_insn.next_pc_inc == 2) ||
1254                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1255
1256                                                 /*
1257                                                  * Since this instruction will
1258                                                  * be put on the stack with
1259                                                  * 32-bit words, get around
1260                                                  * this problem by putting a
1261                                                  * NOP16 as the second one.
1262                                                  */
1263                                                 if (dec_insn.next_pc_inc == 2)
1264                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1265
1266                                                 /*
1267                                                  * Single step the non-CP1
1268                                                  * instruction in the dslot.
1269                                                  */
1270                                                 sig = mips_dsemul(xcp, ir,
1271                                                                   bcpc, contpc);
1272                                                 if (sig < 0)
1273                                                         break;
1274                                                 if (sig)
1275                                                         xcp->cp0_epc = bcpc;
1276                                                 /*
1277                                                  * SIGILL forces out of
1278                                                  * the emulation loop.
1279                                                  */
1280                                                 return sig ? sig : SIGILL;
1281                                         }
1282                                 } else
1283                                         contpc = (xcp->cp0_epc + (contpc << 2));
1284
1285                                 switch (MIPSInst_OPCODE(ir)) {
1286                                 case lwc1_op:
1287                                 case swc1_op:
1288                                         goto emul;
1289
1290                                 case ldc1_op:
1291                                 case sdc1_op:
1292                                         if (cpu_has_mips_2_3_4_5_r)
1293                                                 goto emul;
1294
1295                                         goto bc_sigill;
1296
1297                                 case cop1_op:
1298                                         goto emul;
1299
1300                                 case cop1x_op:
1301                                         if (cpu_has_mips_4_5_64_r2_r6)
1302                                                 /* its one of ours */
1303                                                 goto emul;
1304
1305                                         goto bc_sigill;
1306
1307                                 case spec_op:
1308                                         switch (MIPSInst_FUNC(ir)) {
1309                                         case movc_op:
1310                                                 if (cpu_has_mips_4_5_r)
1311                                                         goto emul;
1312
1313                                                 goto bc_sigill;
1314                                         }
1315                                         break;
1316
1317                                 bc_sigill:
1318                                         xcp->cp0_epc = bcpc;
1319                                         return SIGILL;
1320                                 }
1321
1322                                 /*
1323                                  * Single step the non-cp1
1324                                  * instruction in the dslot
1325                                  */
1326                                 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1327                                 if (sig < 0)
1328                                         break;
1329                                 if (sig)
1330                                         xcp->cp0_epc = bcpc;
1331                                 /* SIGILL forces out of the emulation loop.  */
1332                                 return sig ? sig : SIGILL;
1333                         } else if (likely) {    /* branch not taken */
1334                                 /*
1335                                  * branch likely nullifies
1336                                  * dslot if not taken
1337                                  */
1338                                 xcp->cp0_epc += dec_insn.pc_inc;
1339                                 contpc += dec_insn.pc_inc;
1340                                 /*
1341                                  * else continue & execute
1342                                  * dslot as normal insn
1343                                  */
1344                         }
1345                         break;
1346
1347                 default:
1348                         if (!(MIPSInst_RS(ir) & 0x10))
1349                                 return SIGILL;
1350
1351                         /* a real fpu computation instruction */
1352                         if ((sig = fpu_emu(xcp, ctx, ir)))
1353                                 return sig;
1354                 }
1355                 break;
1356
1357         case cop1x_op:
1358                 if (!cpu_has_mips_4_5_64_r2_r6)
1359                         return SIGILL;
1360
1361                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1362                 if (sig)
1363                         return sig;
1364                 break;
1365
1366         case spec_op:
1367                 if (!cpu_has_mips_4_5_r)
1368                         return SIGILL;
1369
1370                 if (MIPSInst_FUNC(ir) != movc_op)
1371                         return SIGILL;
1372                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1373                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1374                         xcp->regs[MIPSInst_RD(ir)] =
1375                                 xcp->regs[MIPSInst_RS(ir)];
1376                 break;
1377         default:
1378 sigill:
1379                 return SIGILL;
1380         }
1381
1382         /* we did it !! */
1383         xcp->cp0_epc = contpc;
1384         clear_delay_slot(xcp);
1385
1386         return 0;
1387 }
1388
1389 /*
1390  * Conversion table from MIPS compare ops 48-63
1391  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1392  */
1393 static const unsigned char cmptab[8] = {
1394         0,                      /* cmp_0 (sig) cmp_sf */
1395         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1396         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1397         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1398         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1399         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1400         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1401         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1402 };
1403
1404 static const unsigned char negative_cmptab[8] = {
1405         0, /* Reserved */
1406         IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1407         IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1408         IEEE754_CLT | IEEE754_CGT,
1409         /* Reserved */
1410 };
1411
1412
1413 /*
1414  * Additional MIPS4 instructions
1415  */
1416
1417 #define DEF3OP(name, p, f1, f2, f3)                                     \
1418 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1419         union ieee754##p s, union ieee754##p t)                         \
1420 {                                                                       \
1421         struct _ieee754_csr ieee754_csr_save;                           \
1422         s = f1(s, t);                                                   \
1423         ieee754_csr_save = ieee754_csr;                                 \
1424         s = f2(s, r);                                                   \
1425         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1426         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1427         s = f3(s);                                                      \
1428         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1429         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1430         return s;                                                       \
1431 }
1432
1433 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1434 {
1435         return ieee754dp_div(ieee754dp_one(0), d);
1436 }
1437
1438 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1439 {
1440         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1441 }
1442
1443 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1444 {
1445         return ieee754sp_div(ieee754sp_one(0), s);
1446 }
1447
1448 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1449 {
1450         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1451 }
1452
1453 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1454 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1455 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1456 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1457 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1458 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1459 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1460 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1461
1462 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1463         mips_instruction ir, void *__user *fault_addr)
1464 {
1465         unsigned rcsr = 0;      /* resulting csr */
1466
1467         MIPS_FPU_EMU_INC_STATS(cp1xops);
1468
1469         switch (MIPSInst_FMA_FFMT(ir)) {
1470         case s_fmt:{            /* 0 */
1471
1472                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1473                 union ieee754sp fd, fr, fs, ft;
1474                 u32 __user *va;
1475                 u32 val;
1476
1477                 switch (MIPSInst_FUNC(ir)) {
1478                 case lwxc1_op:
1479                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1480                                 xcp->regs[MIPSInst_FT(ir)]);
1481
1482                         MIPS_FPU_EMU_INC_STATS(loads);
1483                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1484                                 MIPS_FPU_EMU_INC_STATS(errors);
1485                                 *fault_addr = va;
1486                                 return SIGBUS;
1487                         }
1488                         if (__get_user(val, va)) {
1489                                 MIPS_FPU_EMU_INC_STATS(errors);
1490                                 *fault_addr = va;
1491                                 return SIGSEGV;
1492                         }
1493                         SITOREG(val, MIPSInst_FD(ir));
1494                         break;
1495
1496                 case swxc1_op:
1497                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1498                                 xcp->regs[MIPSInst_FT(ir)]);
1499
1500                         MIPS_FPU_EMU_INC_STATS(stores);
1501
1502                         SIFROMREG(val, MIPSInst_FS(ir));
1503                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1504                                 MIPS_FPU_EMU_INC_STATS(errors);
1505                                 *fault_addr = va;
1506                                 return SIGBUS;
1507                         }
1508                         if (put_user(val, va)) {
1509                                 MIPS_FPU_EMU_INC_STATS(errors);
1510                                 *fault_addr = va;
1511                                 return SIGSEGV;
1512                         }
1513                         break;
1514
1515                 case madd_s_op:
1516                         handler = fpemu_sp_madd;
1517                         goto scoptop;
1518                 case msub_s_op:
1519                         handler = fpemu_sp_msub;
1520                         goto scoptop;
1521                 case nmadd_s_op:
1522                         handler = fpemu_sp_nmadd;
1523                         goto scoptop;
1524                 case nmsub_s_op:
1525                         handler = fpemu_sp_nmsub;
1526                         goto scoptop;
1527
1528                       scoptop:
1529                         SPFROMREG(fr, MIPSInst_FR(ir));
1530                         SPFROMREG(fs, MIPSInst_FS(ir));
1531                         SPFROMREG(ft, MIPSInst_FT(ir));
1532                         fd = (*handler) (fr, fs, ft);
1533                         SPTOREG(fd, MIPSInst_FD(ir));
1534
1535                       copcsr:
1536                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1537                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1538                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1539                         }
1540                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1541                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1542                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1543                         }
1544                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1545                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1546                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1547                         }
1548                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1549                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1550                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1551                         }
1552
1553                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1554                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1555                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1556                                    ctx->fcr31); */
1557                                 return SIGFPE;
1558                         }
1559
1560                         break;
1561
1562                 default:
1563                         return SIGILL;
1564                 }
1565                 break;
1566         }
1567
1568         case d_fmt:{            /* 1 */
1569                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1570                 union ieee754dp fd, fr, fs, ft;
1571                 u64 __user *va;
1572                 u64 val;
1573
1574                 switch (MIPSInst_FUNC(ir)) {
1575                 case ldxc1_op:
1576                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1577                                 xcp->regs[MIPSInst_FT(ir)]);
1578
1579                         MIPS_FPU_EMU_INC_STATS(loads);
1580                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1581                                 MIPS_FPU_EMU_INC_STATS(errors);
1582                                 *fault_addr = va;
1583                                 return SIGBUS;
1584                         }
1585                         if (__get_user(val, va)) {
1586                                 MIPS_FPU_EMU_INC_STATS(errors);
1587                                 *fault_addr = va;
1588                                 return SIGSEGV;
1589                         }
1590                         DITOREG(val, MIPSInst_FD(ir));
1591                         break;
1592
1593                 case sdxc1_op:
1594                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1595                                 xcp->regs[MIPSInst_FT(ir)]);
1596
1597                         MIPS_FPU_EMU_INC_STATS(stores);
1598                         DIFROMREG(val, MIPSInst_FS(ir));
1599                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1600                                 MIPS_FPU_EMU_INC_STATS(errors);
1601                                 *fault_addr = va;
1602                                 return SIGBUS;
1603                         }
1604                         if (__put_user(val, va)) {
1605                                 MIPS_FPU_EMU_INC_STATS(errors);
1606                                 *fault_addr = va;
1607                                 return SIGSEGV;
1608                         }
1609                         break;
1610
1611                 case madd_d_op:
1612                         handler = fpemu_dp_madd;
1613                         goto dcoptop;
1614                 case msub_d_op:
1615                         handler = fpemu_dp_msub;
1616                         goto dcoptop;
1617                 case nmadd_d_op:
1618                         handler = fpemu_dp_nmadd;
1619                         goto dcoptop;
1620                 case nmsub_d_op:
1621                         handler = fpemu_dp_nmsub;
1622                         goto dcoptop;
1623
1624                       dcoptop:
1625                         DPFROMREG(fr, MIPSInst_FR(ir));
1626                         DPFROMREG(fs, MIPSInst_FS(ir));
1627                         DPFROMREG(ft, MIPSInst_FT(ir));
1628                         fd = (*handler) (fr, fs, ft);
1629                         DPTOREG(fd, MIPSInst_FD(ir));
1630                         goto copcsr;
1631
1632                 default:
1633                         return SIGILL;
1634                 }
1635                 break;
1636         }
1637
1638         case 0x3:
1639                 if (MIPSInst_FUNC(ir) != pfetch_op)
1640                         return SIGILL;
1641
1642                 /* ignore prefx operation */
1643                 break;
1644
1645         default:
1646                 return SIGILL;
1647         }
1648
1649         return 0;
1650 }
1651
1652
1653
1654 /*
1655  * Emulate a single COP1 arithmetic instruction.
1656  */
1657 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1658         mips_instruction ir)
1659 {
1660         int rfmt;               /* resulting format */
1661         unsigned rcsr = 0;      /* resulting csr */
1662         unsigned int oldrm;
1663         unsigned int cbit;
1664         unsigned cond;
1665         union {
1666                 union ieee754dp d;
1667                 union ieee754sp s;
1668                 int w;
1669                 s64 l;
1670         } rv;                   /* resulting value */
1671         u64 bits;
1672
1673         MIPS_FPU_EMU_INC_STATS(cp1ops);
1674         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1675         case s_fmt: {           /* 0 */
1676                 union {
1677                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1678                         union ieee754sp(*u) (union ieee754sp);
1679                 } handler;
1680                 union ieee754sp fd, fs, ft;
1681
1682                 switch (MIPSInst_FUNC(ir)) {
1683                         /* binary ops */
1684                 case fadd_op:
1685                         handler.b = ieee754sp_add;
1686                         goto scopbop;
1687                 case fsub_op:
1688                         handler.b = ieee754sp_sub;
1689                         goto scopbop;
1690                 case fmul_op:
1691                         handler.b = ieee754sp_mul;
1692                         goto scopbop;
1693                 case fdiv_op:
1694                         handler.b = ieee754sp_div;
1695                         goto scopbop;
1696
1697                         /* unary  ops */
1698                 case fsqrt_op:
1699                         if (!cpu_has_mips_2_3_4_5_r)
1700                                 return SIGILL;
1701
1702                         handler.u = ieee754sp_sqrt;
1703                         goto scopuop;
1704
1705                 /*
1706                  * Note that on some MIPS IV implementations such as the
1707                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1708                  * achieve full IEEE-754 accuracy - however this emulator does.
1709                  */
1710                 case frsqrt_op:
1711                         if (!cpu_has_mips_4_5_64_r2_r6)
1712                                 return SIGILL;
1713
1714                         handler.u = fpemu_sp_rsqrt;
1715                         goto scopuop;
1716
1717                 case frecip_op:
1718                         if (!cpu_has_mips_4_5_64_r2_r6)
1719                                 return SIGILL;
1720
1721                         handler.u = fpemu_sp_recip;
1722                         goto scopuop;
1723
1724                 case fmovc_op:
1725                         if (!cpu_has_mips_4_5_r)
1726                                 return SIGILL;
1727
1728                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1729                         if (((ctx->fcr31 & cond) != 0) !=
1730                                 ((MIPSInst_FT(ir) & 1) != 0))
1731                                 return 0;
1732                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1733                         break;
1734
1735                 case fmovz_op:
1736                         if (!cpu_has_mips_4_5_r)
1737                                 return SIGILL;
1738
1739                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1740                                 return 0;
1741                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1742                         break;
1743
1744                 case fmovn_op:
1745                         if (!cpu_has_mips_4_5_r)
1746                                 return SIGILL;
1747
1748                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1749                                 return 0;
1750                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1751                         break;
1752
1753                 case fseleqz_op:
1754                         if (!cpu_has_mips_r6)
1755                                 return SIGILL;
1756
1757                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1758                         if (rv.w & 0x1)
1759                                 rv.w = 0;
1760                         else
1761                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1762                         break;
1763
1764                 case fselnez_op:
1765                         if (!cpu_has_mips_r6)
1766                                 return SIGILL;
1767
1768                         SPFROMREG(rv.s, MIPSInst_FT(ir));
1769                         if (rv.w & 0x1)
1770                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1771                         else
1772                                 rv.w = 0;
1773                         break;
1774
1775                 case fmaddf_op: {
1776                         union ieee754sp ft, fs, fd;
1777
1778                         if (!cpu_has_mips_r6)
1779                                 return SIGILL;
1780
1781                         SPFROMREG(ft, MIPSInst_FT(ir));
1782                         SPFROMREG(fs, MIPSInst_FS(ir));
1783                         SPFROMREG(fd, MIPSInst_FD(ir));
1784                         rv.s = ieee754sp_maddf(fd, fs, ft);
1785                         break;
1786                 }
1787
1788                 case fmsubf_op: {
1789                         union ieee754sp ft, fs, fd;
1790
1791                         if (!cpu_has_mips_r6)
1792                                 return SIGILL;
1793
1794                         SPFROMREG(ft, MIPSInst_FT(ir));
1795                         SPFROMREG(fs, MIPSInst_FS(ir));
1796                         SPFROMREG(fd, MIPSInst_FD(ir));
1797                         rv.s = ieee754sp_msubf(fd, fs, ft);
1798                         break;
1799                 }
1800
1801                 case frint_op: {
1802                         union ieee754sp fs;
1803
1804                         if (!cpu_has_mips_r6)
1805                                 return SIGILL;
1806
1807                         SPFROMREG(fs, MIPSInst_FS(ir));
1808                         rv.l = ieee754sp_tlong(fs);
1809                         rv.s = ieee754sp_flong(rv.l);
1810                         goto copcsr;
1811                 }
1812
1813                 case fclass_op: {
1814                         union ieee754sp fs;
1815
1816                         if (!cpu_has_mips_r6)
1817                                 return SIGILL;
1818
1819                         SPFROMREG(fs, MIPSInst_FS(ir));
1820                         rv.w = ieee754sp_2008class(fs);
1821                         rfmt = w_fmt;
1822                         break;
1823                 }
1824
1825                 case fmin_op: {
1826                         union ieee754sp fs, ft;
1827
1828                         if (!cpu_has_mips_r6)
1829                                 return SIGILL;
1830
1831                         SPFROMREG(ft, MIPSInst_FT(ir));
1832                         SPFROMREG(fs, MIPSInst_FS(ir));
1833                         rv.s = ieee754sp_fmin(fs, ft);
1834                         break;
1835                 }
1836
1837                 case fmina_op: {
1838                         union ieee754sp fs, ft;
1839
1840                         if (!cpu_has_mips_r6)
1841                                 return SIGILL;
1842
1843                         SPFROMREG(ft, MIPSInst_FT(ir));
1844                         SPFROMREG(fs, MIPSInst_FS(ir));
1845                         rv.s = ieee754sp_fmina(fs, ft);
1846                         break;
1847                 }
1848
1849                 case fmax_op: {
1850                         union ieee754sp fs, ft;
1851
1852                         if (!cpu_has_mips_r6)
1853                                 return SIGILL;
1854
1855                         SPFROMREG(ft, MIPSInst_FT(ir));
1856                         SPFROMREG(fs, MIPSInst_FS(ir));
1857                         rv.s = ieee754sp_fmax(fs, ft);
1858                         break;
1859                 }
1860
1861                 case fmaxa_op: {
1862                         union ieee754sp fs, ft;
1863
1864                         if (!cpu_has_mips_r6)
1865                                 return SIGILL;
1866
1867                         SPFROMREG(ft, MIPSInst_FT(ir));
1868                         SPFROMREG(fs, MIPSInst_FS(ir));
1869                         rv.s = ieee754sp_fmaxa(fs, ft);
1870                         break;
1871                 }
1872
1873                 case fabs_op:
1874                         handler.u = ieee754sp_abs;
1875                         goto scopuop;
1876
1877                 case fneg_op:
1878                         handler.u = ieee754sp_neg;
1879                         goto scopuop;
1880
1881                 case fmov_op:
1882                         /* an easy one */
1883                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1884                         goto copcsr;
1885
1886                         /* binary op on handler */
1887 scopbop:
1888                         SPFROMREG(fs, MIPSInst_FS(ir));
1889                         SPFROMREG(ft, MIPSInst_FT(ir));
1890
1891                         rv.s = (*handler.b) (fs, ft);
1892                         goto copcsr;
1893 scopuop:
1894                         SPFROMREG(fs, MIPSInst_FS(ir));
1895                         rv.s = (*handler.u) (fs);
1896                         goto copcsr;
1897 copcsr:
1898                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1899                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1900                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1901                         }
1902                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1903                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1904                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1905                         }
1906                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1907                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1908                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1909                         }
1910                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1911                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1912                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1913                         }
1914                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1915                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1916                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1917                         }
1918                         break;
1919
1920                         /* unary conv ops */
1921                 case fcvts_op:
1922                         return SIGILL;  /* not defined */
1923
1924                 case fcvtd_op:
1925                         SPFROMREG(fs, MIPSInst_FS(ir));
1926                         rv.d = ieee754dp_fsp(fs);
1927                         rfmt = d_fmt;
1928                         goto copcsr;
1929
1930                 case fcvtw_op:
1931                         SPFROMREG(fs, MIPSInst_FS(ir));
1932                         rv.w = ieee754sp_tint(fs);
1933                         rfmt = w_fmt;
1934                         goto copcsr;
1935
1936                 case fround_op:
1937                 case ftrunc_op:
1938                 case fceil_op:
1939                 case ffloor_op:
1940                         if (!cpu_has_mips_2_3_4_5_r)
1941                                 return SIGILL;
1942
1943                         oldrm = ieee754_csr.rm;
1944                         SPFROMREG(fs, MIPSInst_FS(ir));
1945                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1946                         rv.w = ieee754sp_tint(fs);
1947                         ieee754_csr.rm = oldrm;
1948                         rfmt = w_fmt;
1949                         goto copcsr;
1950
1951                 case fsel_op:
1952                         if (!cpu_has_mips_r6)
1953                                 return SIGILL;
1954
1955                         SPFROMREG(fd, MIPSInst_FD(ir));
1956                         if (fd.bits & 0x1)
1957                                 SPFROMREG(rv.s, MIPSInst_FT(ir));
1958                         else
1959                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
1960                         break;
1961
1962                 case fcvtl_op:
1963                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1964                                 return SIGILL;
1965
1966                         SPFROMREG(fs, MIPSInst_FS(ir));
1967                         rv.l = ieee754sp_tlong(fs);
1968                         rfmt = l_fmt;
1969                         goto copcsr;
1970
1971                 case froundl_op:
1972                 case ftruncl_op:
1973                 case fceill_op:
1974                 case ffloorl_op:
1975                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1976                                 return SIGILL;
1977
1978                         oldrm = ieee754_csr.rm;
1979                         SPFROMREG(fs, MIPSInst_FS(ir));
1980                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1981                         rv.l = ieee754sp_tlong(fs);
1982                         ieee754_csr.rm = oldrm;
1983                         rfmt = l_fmt;
1984                         goto copcsr;
1985
1986                 default:
1987                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1988                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1989                                 union ieee754sp fs, ft;
1990
1991                                 SPFROMREG(fs, MIPSInst_FS(ir));
1992                                 SPFROMREG(ft, MIPSInst_FT(ir));
1993                                 rv.w = ieee754sp_cmp(fs, ft,
1994                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1995                                 rfmt = -1;
1996                                 if ((cmpop & 0x8) && ieee754_cxtest
1997                                         (IEEE754_INVALID_OPERATION))
1998                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1999                                 else
2000                                         goto copcsr;
2001
2002                         } else
2003                                 return SIGILL;
2004                         break;
2005                 }
2006                 break;
2007         }
2008
2009         case d_fmt: {
2010                 union ieee754dp fd, fs, ft;
2011                 union {
2012                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2013                         union ieee754dp(*u) (union ieee754dp);
2014                 } handler;
2015
2016                 switch (MIPSInst_FUNC(ir)) {
2017                         /* binary ops */
2018                 case fadd_op:
2019                         handler.b = ieee754dp_add;
2020                         goto dcopbop;
2021                 case fsub_op:
2022                         handler.b = ieee754dp_sub;
2023                         goto dcopbop;
2024                 case fmul_op:
2025                         handler.b = ieee754dp_mul;
2026                         goto dcopbop;
2027                 case fdiv_op:
2028                         handler.b = ieee754dp_div;
2029                         goto dcopbop;
2030
2031                         /* unary  ops */
2032                 case fsqrt_op:
2033                         if (!cpu_has_mips_2_3_4_5_r)
2034                                 return SIGILL;
2035
2036                         handler.u = ieee754dp_sqrt;
2037                         goto dcopuop;
2038                 /*
2039                  * Note that on some MIPS IV implementations such as the
2040                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
2041                  * achieve full IEEE-754 accuracy - however this emulator does.
2042                  */
2043                 case frsqrt_op:
2044                         if (!cpu_has_mips_4_5_64_r2_r6)
2045                                 return SIGILL;
2046
2047                         handler.u = fpemu_dp_rsqrt;
2048                         goto dcopuop;
2049                 case frecip_op:
2050                         if (!cpu_has_mips_4_5_64_r2_r6)
2051                                 return SIGILL;
2052
2053                         handler.u = fpemu_dp_recip;
2054                         goto dcopuop;
2055                 case fmovc_op:
2056                         if (!cpu_has_mips_4_5_r)
2057                                 return SIGILL;
2058
2059                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2060                         if (((ctx->fcr31 & cond) != 0) !=
2061                                 ((MIPSInst_FT(ir) & 1) != 0))
2062                                 return 0;
2063                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2064                         break;
2065                 case fmovz_op:
2066                         if (!cpu_has_mips_4_5_r)
2067                                 return SIGILL;
2068
2069                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
2070                                 return 0;
2071                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2072                         break;
2073                 case fmovn_op:
2074                         if (!cpu_has_mips_4_5_r)
2075                                 return SIGILL;
2076
2077                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
2078                                 return 0;
2079                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2080                         break;
2081
2082                 case fseleqz_op:
2083                         if (!cpu_has_mips_r6)
2084                                 return SIGILL;
2085
2086                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2087                         if (rv.l & 0x1)
2088                                 rv.l = 0;
2089                         else
2090                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2091                         break;
2092
2093                 case fselnez_op:
2094                         if (!cpu_has_mips_r6)
2095                                 return SIGILL;
2096
2097                         DPFROMREG(rv.d, MIPSInst_FT(ir));
2098                         if (rv.l & 0x1)
2099                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2100                         else
2101                                 rv.l = 0;
2102                         break;
2103
2104                 case fmaddf_op: {
2105                         union ieee754dp ft, fs, fd;
2106
2107                         if (!cpu_has_mips_r6)
2108                                 return SIGILL;
2109
2110                         DPFROMREG(ft, MIPSInst_FT(ir));
2111                         DPFROMREG(fs, MIPSInst_FS(ir));
2112                         DPFROMREG(fd, MIPSInst_FD(ir));
2113                         rv.d = ieee754dp_maddf(fd, fs, ft);
2114                         break;
2115                 }
2116
2117                 case fmsubf_op: {
2118                         union ieee754dp ft, fs, fd;
2119
2120                         if (!cpu_has_mips_r6)
2121                                 return SIGILL;
2122
2123                         DPFROMREG(ft, MIPSInst_FT(ir));
2124                         DPFROMREG(fs, MIPSInst_FS(ir));
2125                         DPFROMREG(fd, MIPSInst_FD(ir));
2126                         rv.d = ieee754dp_msubf(fd, fs, ft);
2127                         break;
2128                 }
2129
2130                 case frint_op: {
2131                         union ieee754dp fs;
2132
2133                         if (!cpu_has_mips_r6)
2134                                 return SIGILL;
2135
2136                         DPFROMREG(fs, MIPSInst_FS(ir));
2137                         rv.l = ieee754dp_tlong(fs);
2138                         rv.d = ieee754dp_flong(rv.l);
2139                         goto copcsr;
2140                 }
2141
2142                 case fclass_op: {
2143                         union ieee754dp fs;
2144
2145                         if (!cpu_has_mips_r6)
2146                                 return SIGILL;
2147
2148                         DPFROMREG(fs, MIPSInst_FS(ir));
2149                         rv.w = ieee754dp_2008class(fs);
2150                         rfmt = w_fmt;
2151                         break;
2152                 }
2153
2154                 case fmin_op: {
2155                         union ieee754dp fs, ft;
2156
2157                         if (!cpu_has_mips_r6)
2158                                 return SIGILL;
2159
2160                         DPFROMREG(ft, MIPSInst_FT(ir));
2161                         DPFROMREG(fs, MIPSInst_FS(ir));
2162                         rv.d = ieee754dp_fmin(fs, ft);
2163                         break;
2164                 }
2165
2166                 case fmina_op: {
2167                         union ieee754dp fs, ft;
2168
2169                         if (!cpu_has_mips_r6)
2170                                 return SIGILL;
2171
2172                         DPFROMREG(ft, MIPSInst_FT(ir));
2173                         DPFROMREG(fs, MIPSInst_FS(ir));
2174                         rv.d = ieee754dp_fmina(fs, ft);
2175                         break;
2176                 }
2177
2178                 case fmax_op: {
2179                         union ieee754dp fs, ft;
2180
2181                         if (!cpu_has_mips_r6)
2182                                 return SIGILL;
2183
2184                         DPFROMREG(ft, MIPSInst_FT(ir));
2185                         DPFROMREG(fs, MIPSInst_FS(ir));
2186                         rv.d = ieee754dp_fmax(fs, ft);
2187                         break;
2188                 }
2189
2190                 case fmaxa_op: {
2191                         union ieee754dp fs, ft;
2192
2193                         if (!cpu_has_mips_r6)
2194                                 return SIGILL;
2195
2196                         DPFROMREG(ft, MIPSInst_FT(ir));
2197                         DPFROMREG(fs, MIPSInst_FS(ir));
2198                         rv.d = ieee754dp_fmaxa(fs, ft);
2199                         break;
2200                 }
2201
2202                 case fabs_op:
2203                         handler.u = ieee754dp_abs;
2204                         goto dcopuop;
2205
2206                 case fneg_op:
2207                         handler.u = ieee754dp_neg;
2208                         goto dcopuop;
2209
2210                 case fmov_op:
2211                         /* an easy one */
2212                         DPFROMREG(rv.d, MIPSInst_FS(ir));
2213                         goto copcsr;
2214
2215                         /* binary op on handler */
2216 dcopbop:
2217                         DPFROMREG(fs, MIPSInst_FS(ir));
2218                         DPFROMREG(ft, MIPSInst_FT(ir));
2219
2220                         rv.d = (*handler.b) (fs, ft);
2221                         goto copcsr;
2222 dcopuop:
2223                         DPFROMREG(fs, MIPSInst_FS(ir));
2224                         rv.d = (*handler.u) (fs);
2225                         goto copcsr;
2226
2227                 /*
2228                  * unary conv ops
2229                  */
2230                 case fcvts_op:
2231                         DPFROMREG(fs, MIPSInst_FS(ir));
2232                         rv.s = ieee754sp_fdp(fs);
2233                         rfmt = s_fmt;
2234                         goto copcsr;
2235
2236                 case fcvtd_op:
2237                         return SIGILL;  /* not defined */
2238
2239                 case fcvtw_op:
2240                         DPFROMREG(fs, MIPSInst_FS(ir));
2241                         rv.w = ieee754dp_tint(fs);      /* wrong */
2242                         rfmt = w_fmt;
2243                         goto copcsr;
2244
2245                 case fround_op:
2246                 case ftrunc_op:
2247                 case fceil_op:
2248                 case ffloor_op:
2249                         if (!cpu_has_mips_2_3_4_5_r)
2250                                 return SIGILL;
2251
2252                         oldrm = ieee754_csr.rm;
2253                         DPFROMREG(fs, MIPSInst_FS(ir));
2254                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2255                         rv.w = ieee754dp_tint(fs);
2256                         ieee754_csr.rm = oldrm;
2257                         rfmt = w_fmt;
2258                         goto copcsr;
2259
2260                 case fsel_op:
2261                         if (!cpu_has_mips_r6)
2262                                 return SIGILL;
2263
2264                         DPFROMREG(fd, MIPSInst_FD(ir));
2265                         if (fd.bits & 0x1)
2266                                 DPFROMREG(rv.d, MIPSInst_FT(ir));
2267                         else
2268                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
2269                         break;
2270
2271                 case fcvtl_op:
2272                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2273                                 return SIGILL;
2274
2275                         DPFROMREG(fs, MIPSInst_FS(ir));
2276                         rv.l = ieee754dp_tlong(fs);
2277                         rfmt = l_fmt;
2278                         goto copcsr;
2279
2280                 case froundl_op:
2281                 case ftruncl_op:
2282                 case fceill_op:
2283                 case ffloorl_op:
2284                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2285                                 return SIGILL;
2286
2287                         oldrm = ieee754_csr.rm;
2288                         DPFROMREG(fs, MIPSInst_FS(ir));
2289                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2290                         rv.l = ieee754dp_tlong(fs);
2291                         ieee754_csr.rm = oldrm;
2292                         rfmt = l_fmt;
2293                         goto copcsr;
2294
2295                 default:
2296                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2297                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2298                                 union ieee754dp fs, ft;
2299
2300                                 DPFROMREG(fs, MIPSInst_FS(ir));
2301                                 DPFROMREG(ft, MIPSInst_FT(ir));
2302                                 rv.w = ieee754dp_cmp(fs, ft,
2303                                         cmptab[cmpop & 0x7], cmpop & 0x8);
2304                                 rfmt = -1;
2305                                 if ((cmpop & 0x8)
2306                                         &&
2307                                         ieee754_cxtest
2308                                         (IEEE754_INVALID_OPERATION))
2309                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2310                                 else
2311                                         goto copcsr;
2312
2313                         }
2314                         else {
2315                                 return SIGILL;
2316                         }
2317                         break;
2318                 }
2319                 break;
2320         }
2321
2322         case w_fmt: {
2323                 union ieee754dp fs;
2324
2325                 switch (MIPSInst_FUNC(ir)) {
2326                 case fcvts_op:
2327                         /* convert word to single precision real */
2328                         SPFROMREG(fs, MIPSInst_FS(ir));
2329                         rv.s = ieee754sp_fint(fs.bits);
2330                         rfmt = s_fmt;
2331                         goto copcsr;
2332                 case fcvtd_op:
2333                         /* convert word to double precision real */
2334                         SPFROMREG(fs, MIPSInst_FS(ir));
2335                         rv.d = ieee754dp_fint(fs.bits);
2336                         rfmt = d_fmt;
2337                         goto copcsr;
2338                 default: {
2339                         /* Emulating the new CMP.condn.fmt R6 instruction */
2340 #define CMPOP_MASK      0x7
2341 #define SIGN_BIT        (0x1 << 3)
2342 #define PREDICATE_BIT   (0x1 << 4)
2343
2344                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2345                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2346                         union ieee754sp fs, ft;
2347
2348                         /* This is an R6 only instruction */
2349                         if (!cpu_has_mips_r6 ||
2350                             (MIPSInst_FUNC(ir) & 0x20))
2351                                 return SIGILL;
2352
2353                         /* fmt is w_fmt for single precision so fix it */
2354                         rfmt = s_fmt;
2355                         /* default to false */
2356                         rv.w = 0;
2357
2358                         /* CMP.condn.S */
2359                         SPFROMREG(fs, MIPSInst_FS(ir));
2360                         SPFROMREG(ft, MIPSInst_FT(ir));
2361
2362                         /* positive predicates */
2363                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2364                                 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2365                                                   sig))
2366                                     rv.w = -1; /* true, all 1s */
2367                                 if ((sig) &&
2368                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2369                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2370                                 else
2371                                         goto copcsr;
2372                         } else {
2373                                 /* negative predicates */
2374                                 switch (cmpop) {
2375                                 case 1:
2376                                 case 2:
2377                                 case 3:
2378                                         if (ieee754sp_cmp(fs, ft,
2379                                                           negative_cmptab[cmpop],
2380                                                           sig))
2381                                                 rv.w = -1; /* true, all 1s */
2382                                         if (sig &&
2383                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2384                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2385                                         else
2386                                                 goto copcsr;
2387                                         break;
2388                                 default:
2389                                         /* Reserved R6 ops */
2390                                         pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2391                                         return SIGILL;
2392                                 }
2393                         }
2394                         break;
2395                         }
2396                 }
2397         }
2398
2399         case l_fmt:
2400
2401                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2402                         return SIGILL;
2403
2404                 DIFROMREG(bits, MIPSInst_FS(ir));
2405
2406                 switch (MIPSInst_FUNC(ir)) {
2407                 case fcvts_op:
2408                         /* convert long to single precision real */
2409                         rv.s = ieee754sp_flong(bits);
2410                         rfmt = s_fmt;
2411                         goto copcsr;
2412                 case fcvtd_op:
2413                         /* convert long to double precision real */
2414                         rv.d = ieee754dp_flong(bits);
2415                         rfmt = d_fmt;
2416                         goto copcsr;
2417                 default: {
2418                         /* Emulating the new CMP.condn.fmt R6 instruction */
2419                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2420                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2421                         union ieee754dp fs, ft;
2422
2423                         if (!cpu_has_mips_r6 ||
2424                             (MIPSInst_FUNC(ir) & 0x20))
2425                                 return SIGILL;
2426
2427                         /* fmt is l_fmt for double precision so fix it */
2428                         rfmt = d_fmt;
2429                         /* default to false */
2430                         rv.l = 0;
2431
2432                         /* CMP.condn.D */
2433                         DPFROMREG(fs, MIPSInst_FS(ir));
2434                         DPFROMREG(ft, MIPSInst_FT(ir));
2435
2436                         /* positive predicates */
2437                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2438                                 if (ieee754dp_cmp(fs, ft,
2439                                                   cmptab[cmpop], sig))
2440                                     rv.l = -1LL; /* true, all 1s */
2441                                 if (sig &&
2442                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2443                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2444                                 else
2445                                         goto copcsr;
2446                         } else {
2447                                 /* negative predicates */
2448                                 switch (cmpop) {
2449                                 case 1:
2450                                 case 2:
2451                                 case 3:
2452                                         if (ieee754dp_cmp(fs, ft,
2453                                                           negative_cmptab[cmpop],
2454                                                           sig))
2455                                                 rv.l = -1LL; /* true, all 1s */
2456                                         if (sig &&
2457                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2458                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2459                                         else
2460                                                 goto copcsr;
2461                                         break;
2462                                 default:
2463                                         /* Reserved R6 ops */
2464                                         pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2465                                         return SIGILL;
2466                                 }
2467                         }
2468                         break;
2469                         }
2470                 }
2471         default:
2472                 return SIGILL;
2473         }
2474
2475         /*
2476          * Update the fpu CSR register for this operation.
2477          * If an exception is required, generate a tidy SIGFPE exception,
2478          * without updating the result register.
2479          * Note: cause exception bits do not accumulate, they are rewritten
2480          * for each op; only the flag/sticky bits accumulate.
2481          */
2482         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2483         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2484                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2485                 return SIGFPE;
2486         }
2487
2488         /*
2489          * Now we can safely write the result back to the register file.
2490          */
2491         switch (rfmt) {
2492         case -1:
2493
2494                 if (cpu_has_mips_4_5_r)
2495                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2496                 else
2497                         cbit = FPU_CSR_COND;
2498                 if (rv.w)
2499                         ctx->fcr31 |= cbit;
2500                 else
2501                         ctx->fcr31 &= ~cbit;
2502                 break;
2503
2504         case d_fmt:
2505                 DPTOREG(rv.d, MIPSInst_FD(ir));
2506                 break;
2507         case s_fmt:
2508                 SPTOREG(rv.s, MIPSInst_FD(ir));
2509                 break;
2510         case w_fmt:
2511                 SITOREG(rv.w, MIPSInst_FD(ir));
2512                 break;
2513         case l_fmt:
2514                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2515                         return SIGILL;
2516
2517                 DITOREG(rv.l, MIPSInst_FD(ir));
2518                 break;
2519         default:
2520                 return SIGILL;
2521         }
2522
2523         return 0;
2524 }
2525
2526 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2527         int has_fpu, void *__user *fault_addr)
2528 {
2529         unsigned long oldepc, prevepc;
2530         struct mm_decoded_insn dec_insn;
2531         u16 instr[4];
2532         u16 *instr_ptr;
2533         int sig = 0;
2534
2535         oldepc = xcp->cp0_epc;
2536         do {
2537                 prevepc = xcp->cp0_epc;
2538
2539                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2540                         /*
2541                          * Get next 2 microMIPS instructions and convert them
2542                          * into 32-bit instructions.
2543                          */
2544                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2545                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2546                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2547                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2548                                 MIPS_FPU_EMU_INC_STATS(errors);
2549                                 return SIGBUS;
2550                         }
2551                         instr_ptr = instr;
2552
2553                         /* Get first instruction. */
2554                         if (mm_insn_16bit(*instr_ptr)) {
2555                                 /* Duplicate the half-word. */
2556                                 dec_insn.insn = (*instr_ptr << 16) |
2557                                         (*instr_ptr);
2558                                 /* 16-bit instruction. */
2559                                 dec_insn.pc_inc = 2;
2560                                 instr_ptr += 1;
2561                         } else {
2562                                 dec_insn.insn = (*instr_ptr << 16) |
2563                                         *(instr_ptr+1);
2564                                 /* 32-bit instruction. */
2565                                 dec_insn.pc_inc = 4;
2566                                 instr_ptr += 2;
2567                         }
2568                         /* Get second instruction. */
2569                         if (mm_insn_16bit(*instr_ptr)) {
2570                                 /* Duplicate the half-word. */
2571                                 dec_insn.next_insn = (*instr_ptr << 16) |
2572                                         (*instr_ptr);
2573                                 /* 16-bit instruction. */
2574                                 dec_insn.next_pc_inc = 2;
2575                         } else {
2576                                 dec_insn.next_insn = (*instr_ptr << 16) |
2577                                         *(instr_ptr+1);
2578                                 /* 32-bit instruction. */
2579                                 dec_insn.next_pc_inc = 4;
2580                         }
2581                         dec_insn.micro_mips_mode = 1;
2582                 } else {
2583                         if ((get_user(dec_insn.insn,
2584                             (mips_instruction __user *) xcp->cp0_epc)) ||
2585                             (get_user(dec_insn.next_insn,
2586                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2587                                 MIPS_FPU_EMU_INC_STATS(errors);
2588                                 return SIGBUS;
2589                         }
2590                         dec_insn.pc_inc = 4;
2591                         dec_insn.next_pc_inc = 4;
2592                         dec_insn.micro_mips_mode = 0;
2593                 }
2594
2595                 if ((dec_insn.insn == 0) ||
2596                    ((dec_insn.pc_inc == 2) &&
2597                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2598                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2599                 else {
2600                         /*
2601                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2602                          * No need to copy ctx->fcr31 to ieee754_csr.
2603                          */
2604                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2605                 }
2606
2607                 if (has_fpu)
2608                         break;
2609                 if (sig)
2610                         break;
2611
2612                 cond_resched();
2613         } while (xcp->cp0_epc > prevepc);
2614
2615         /* SIGILL indicates a non-fpu instruction */
2616         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2617                 /* but if EPC has advanced, then ignore it */
2618                 sig = 0;
2619
2620         return sig;
2621 }