arch/powerpc/boot/dts/fsl/p5040si-post.dtsi

   1 /*
   2  * P5040 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * This software is provided by Freescale Semiconductor "as is" and any
  24  * express or implied warranties, including, but not limited to, the implied
  25  * warranties of merchantability and fitness for a particular purpose are
  26  * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27  * direct, indirect, incidental, special, exemplary, or consequential damages
  28  * (including, but not limited to, procurement of substitute goods or services;
  29  * loss of use, data, or profits; or business interruption) however caused and
  30  * on any theory of liability, whether in contract, strict liability, or tort
  31  * (including negligence or otherwise) arising in any way out of the use of this
  32  * software, even if advised of the possibility of such damage.
  33  */
  34
  35 &lbc {
  36         compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
  37         interrupts = <25 2 0 0>;
  38         #address-cells = <2>;
  39         #size-cells = <1>;
  40 };
  41
  42 /* controller at 0x200000 */
  43 &pci0 {
  44         compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0x0 0xff>;
  49         clock-frequency = <33333333>;
  50         interrupts = <16 2 1 15>;
  51         fsl,iommu-parent = <&pamu0>;
  52         pcie@0 {
  53                 reg = <0 0 0 0 0>;
  54                 #interrupt-cells = <1>;
  55                 #size-cells = <2>;
  56                 #address-cells = <3>;
  57                 device_type = "pci";
  58                 interrupts = <16 2 1 15>;
  59                 interrupt-map-mask = <0xf800 0 0 7>;
  60                 interrupt-map = <
  61                         /* IDSEL 0x0 */
  62                         0000 0 0 1 &mpic 40 1 0 0
  63                         0000 0 0 2 &mpic 1 1 0 0
  64                         0000 0 0 3 &mpic 2 1 0 0
  65                         0000 0 0 4 &mpic 3 1 0 0
  66                         >;
  67         };
  68 };
  69
  70 /* controller at 0x201000 */
  71 &pci1 {
  72         compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  73         device_type = "pci";
  74         #size-cells = <2>;
  75         #address-cells = <3>;
  76         bus-range = <0 0xff>;
  77         clock-frequency = <33333333>;
  78         interrupts = <16 2 1 14>;
  79         fsl,iommu-parent = <&pamu0>;
  80         pcie@0 {
  81                 reg = <0 0 0 0 0>;
  82                 #interrupt-cells = <1>;
  83                 #size-cells = <2>;
  84                 #address-cells = <3>;
  85                 device_type = "pci";
  86                 interrupts = <16 2 1 14>;
  87                 interrupt-map-mask = <0xf800 0 0 7>;
  88                 interrupt-map = <
  89                         /* IDSEL 0x0 */
  90                         0000 0 0 1 &mpic 41 1 0 0
  91                         0000 0 0 2 &mpic 5 1 0 0
  92                         0000 0 0 3 &mpic 6 1 0 0
  93                         0000 0 0 4 &mpic 7 1 0 0
  94                         >;
  95         };
  96 };
  97
  98 /* controller at 0x202000 */
  99 &pci2 {
 100         compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
 101         device_type = "pci";
 102         #size-cells = <2>;
 103         #address-cells = <3>;
 104         bus-range = <0x0 0xff>;
 105         clock-frequency = <33333333>;
 106         interrupts = <16 2 1 13>;
 107         fsl,iommu-parent = <&pamu0>;
 108         pcie@0 {
 109                 reg = <0 0 0 0 0>;
 110                 #interrupt-cells = <1>;
 111                 #size-cells = <2>;
 112                 #address-cells = <3>;
 113                 device_type = "pci";
 114                 interrupts = <16 2 1 13>;
 115                 interrupt-map-mask = <0xf800 0 0 7>;
 116                 interrupt-map = <
 117                         /* IDSEL 0x0 */
 118                         0000 0 0 1 &mpic 42 1 0 0
 119                         0000 0 0 2 &mpic 9 1 0 0
 120                         0000 0 0 3 &mpic 10 1 0 0
 121                         0000 0 0 4 &mpic 11 1 0 0
 122                         >;
 123         };
 124 };
 125
 126 &dcsr {
 127         #address-cells = <1>;
 128         #size-cells = <1>;
 129         compatible = "fsl,dcsr", "simple-bus";
 130
 131         dcsr-epu@0 {
 132                 compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
 133                 interrupts = <52 2 0 0
 134                               84 2 0 0
 135                               85 2 0 0>;
 136                 reg = <0x0 0x1000>;
 137         };
 138         dcsr-npc {
 139                 compatible = "fsl,dcsr-npc";
 140                 reg = <0x1000 0x1000 0x1000000 0x8000>;
 141         };
 142         dcsr-nxc@2000 {
 143                 compatible = "fsl,dcsr-nxc";
 144                 reg = <0x2000 0x1000>;
 145         };
 146         dcsr-corenet {
 147                 compatible = "fsl,dcsr-corenet";
 148                 reg = <0x8000 0x1000 0xB0000 0x1000>;
 149         };
 150         dcsr-dpaa@9000 {
 151                 compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
 152                 reg = <0x9000 0x1000>;
 153         };
 154         dcsr-ocn@11000 {
 155                 compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
 156                 reg = <0x11000 0x1000>;
 157         };
 158         dcsr-ddr@12000 {
 159                 compatible = "fsl,dcsr-ddr";
 160                 dev-handle = <&ddr1>;
 161                 reg = <0x12000 0x1000>;
 162         };
 163         dcsr-ddr@13000 {
 164                 compatible = "fsl,dcsr-ddr";
 165                 dev-handle = <&ddr2>;
 166                 reg = <0x13000 0x1000>;
 167         };
 168         dcsr-nal@18000 {
 169                 compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
 170                 reg = <0x18000 0x1000>;
 171         };
 172         dcsr-rcpm@22000 {
 173                 compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
 174                 reg = <0x22000 0x1000>;
 175         };
 176         dcsr-cpu-sb-proxy@40000 {
 177                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 178                 cpu-handle = <&cpu0>;
 179                 reg = <0x40000 0x1000>;
 180         };
 181         dcsr-cpu-sb-proxy@41000 {
 182                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 183                 cpu-handle = <&cpu1>;
 184                 reg = <0x41000 0x1000>;
 185         };
 186         dcsr-cpu-sb-proxy@42000 {
 187                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 188                 cpu-handle = <&cpu2>;
 189                 reg = <0x42000 0x1000>;
 190         };
 191         dcsr-cpu-sb-proxy@43000 {
 192                 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 193                 cpu-handle = <&cpu3>;
 194                 reg = <0x43000 0x1000>;
 195         };
 196 };
 197
 198 &soc {
 199         #address-cells = <1>;
 200         #size-cells = <1>;
 201         device_type = "soc";
 202         compatible = "simple-bus";
 203
 204         soc-sram-error {
 205                 compatible = "fsl,soc-sram-error";
 206                 interrupts = <16 2 1 29>;
 207         };
 208
 209         corenet-law@0 {
 210                 compatible = "fsl,corenet-law";
 211                 reg = <0x0 0x1000>;
 212                 fsl,num-laws = <32>;
 213         };
 214
 215         ddr1: memory-controller@8000 {
 216                 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 217                 reg = <0x8000 0x1000>;
 218                 interrupts = <16 2 1 23>;
 219         };
 220
 221         ddr2: memory-controller@9000 {
 222                 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
 223                 reg = <0x9000 0x1000>;
 224                 interrupts = <16 2 1 22>;
 225         };
 226
 227         cpc: l3-cache-controller@10000 {
 228                 compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 229                 reg = <0x10000 0x1000
 230                        0x11000 0x1000>;
 231                 interrupts = <16 2 1 27
 232                               16 2 1 26>;
 233         };
 234
 235         corenet-cf@18000 {
 236                 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
 237                 reg = <0x18000 0x1000>;
 238                 interrupts = <16 2 1 31>;
 239                 fsl,ccf-num-csdids = <32>;
 240                 fsl,ccf-num-snoopids = <32>;
 241         };
 242
 243         iommu@20000 {
 244                 compatible = "fsl,pamu-v1.0", "fsl,pamu";
 245                 reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
 246                 ranges = <0 0x20000 0x5000>;
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 interrupts = <24 2 0 0
 250                               16 2 1 30>;
 251                 fsl,portid-mapping = <0x0f800000>;
 252
 253                 pamu0: pamu@0 {
 254                         reg = <0 0x1000>;
 255                         fsl,primary-cache-geometry = <32 1>;
 256                         fsl,secondary-cache-geometry = <128 2>;
 257                 };
 258
 259                 pamu1: pamu@1000 {
 260                         reg = <0x1000 0x1000>;
 261                         fsl,primary-cache-geometry = <32 1>;
 262                         fsl,secondary-cache-geometry = <128 2>;
 263                 };
 264
 265                 pamu2: pamu@2000 {
 266                         reg = <0x2000 0x1000>;
 267                         fsl,primary-cache-geometry = <32 1>;
 268                         fsl,secondary-cache-geometry = <128 2>;
 269                 };
 270
 271                 pamu3: pamu@3000 {
 272                         reg = <0x3000 0x1000>;
 273                         fsl,primary-cache-geometry = <32 1>;
 274                         fsl,secondary-cache-geometry = <128 2>;
 275                 };
 276
 277                 pamu4: pamu@4000 {
 278                         reg = <0x4000 0x1000>;
 279                         fsl,primary-cache-geometry = <32 1>;
 280                         fsl,secondary-cache-geometry = <128 2>;
 281                 };
 282         };
 283
 284 /include/ "qoriq-mpic.dtsi"
 285
 286         guts: global-utilities@e0000 {
 287                 compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
 288                 reg = <0xe0000 0xe00>;
 289                 fsl,has-rstcr;
 290                 #sleep-cells = <1>;
 291                 fsl,liodn-bits = <12>;
 292         };
 293
 294         pins: global-utilities@e0e00 {
 295                 compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
 296                 reg = <0xe0e00 0x200>;
 297                 #sleep-cells = <2>;
 298         };
 299
 300 /include/ "qoriq-clockgen1.dtsi"
 301         global-utilities@e1000 {
 302                 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
 303
 304                 mux2: mux2@40 {
 305                         #clock-cells = <0>;
 306                         reg = <0x40 0x4>;
 307                         compatible = "fsl,qoriq-core-mux-1.0";
 308                         clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 309                         clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 310                         clock-output-names = "cmux2";
 311                 };
 312
 313                 mux3: mux3@60 {
 314                         #clock-cells = <0>;
 315                         reg = <0x60 0x4>;
 316                         compatible = "fsl,qoriq-core-mux-1.0";
 317                         clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 318                         clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 319                         clock-output-names = "cmux3";
 320                 };
 321         };
 322
 323         rcpm: global-utilities@e2000 {
 324                 compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
 325                 reg = <0xe2000 0x1000>;
 326                 #sleep-cells = <1>;
 327         };
 328
 329         sfp: sfp@e8000 {
 330                 compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
 331                 reg        = <0xe8000 0x1000>;
 332         };
 333
 334         serdes: serdes@ea000 {
 335                 compatible = "fsl,p5040-serdes";
 336                 reg        = <0xea000 0x1000>;
 337         };
 338
 339 /include/ "qoriq-dma-0.dtsi"
 340         dma@100300 {
 341                 fsl,iommu-parent = <&pamu0>;
 342                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 343         };
 344
 345 /include/ "qoriq-dma-1.dtsi"
 346         dma@101300 {
 347                 fsl,iommu-parent = <&pamu0>;
 348                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 349         };
 350
 351 /include/ "qoriq-espi-0.dtsi"
 352         spi@110000 {
 353                 fsl,espi-num-chipselects = <4>;
 354         };
 355
 356 /include/ "qoriq-esdhc-0.dtsi"
 357         sdhc@114000 {
 358                 fsl,iommu-parent = <&pamu2>;
 359                 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 360                 sdhci,auto-cmd12;
 361         };
 362
 363 /include/ "qoriq-i2c-0.dtsi"
 364 /include/ "qoriq-i2c-1.dtsi"
 365 /include/ "qoriq-duart-0.dtsi"
 366 /include/ "qoriq-duart-1.dtsi"
 367 /include/ "qoriq-gpio-0.dtsi"
 368 /include/ "qoriq-usb2-mph-0.dtsi"
 369         usb0: usb@210000 {
 370                 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 371                 fsl,iommu-parent = <&pamu4>;
 372                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 373                 phy_type = "utmi";
 374                 port0;
 375         };
 376
 377 /include/ "qoriq-usb2-dr-0.dtsi"
 378         usb1: usb@211000 {
 379                 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 380                 fsl,iommu-parent = <&pamu4>;
 381                 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
 382                 dr_mode = "host";
 383                 phy_type = "utmi";
 384         };
 385
 386 /include/ "qoriq-sata2-0.dtsi"
 387         sata@220000 {
 388                 fsl,iommu-parent = <&pamu4>;
 389                 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
 390         };
 391
 392 /include/ "qoriq-sata2-1.dtsi"
 393         sata@221000 {
 394                 fsl,iommu-parent = <&pamu4>;
 395                 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
 396         };
 397
 398 /include/ "qoriq-sec5.2-0.dtsi"
 399         crypto@300000 {
 400                 fsl,iommu-parent = <&pamu4>;
 401         };
 402 };