2 * T4240 emulator Device Tree Source
4 * Copyright 2013 Freescale Semiconductor Inc.
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37 /include/ "fsl/e6500_power_isa.dtsi"
39 compatible = "fsl,T4240";
42 interrupt-parent = <&mpic>;
59 cpu0: PowerPC,e6500@0 {
62 next-level-cache = <&L2_1>;
63 fsl,portid-mapping = <0x80000000>;
65 cpu1: PowerPC,e6500@2 {
68 next-level-cache = <&L2_1>;
69 fsl,portid-mapping = <0x80000000>;
71 cpu2: PowerPC,e6500@4 {
74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>;
77 cpu3: PowerPC,e6500@6 {
80 next-level-cache = <&L2_1>;
81 fsl,portid-mapping = <0x80000000>;
84 cpu4: PowerPC,e6500@8 {
87 next-level-cache = <&L2_2>;
88 fsl,portid-mapping = <0x40000000>;
90 cpu5: PowerPC,e6500@10 {
93 next-level-cache = <&L2_2>;
94 fsl,portid-mapping = <0x40000000>;
96 cpu6: PowerPC,e6500@12 {
99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
102 cpu7: PowerPC,e6500@14 {
105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x40000000>;
109 cpu8: PowerPC,e6500@16 {
112 next-level-cache = <&L2_3>;
113 fsl,portid-mapping = <0x20000000>;
115 cpu9: PowerPC,e6500@18 {
118 next-level-cache = <&L2_3>;
119 fsl,portid-mapping = <0x20000000>;
121 cpu10: PowerPC,e6500@20 {
124 next-level-cache = <&L2_3>;
125 fsl,portid-mapping = <0x20000000>;
127 cpu11: PowerPC,e6500@22 {
130 next-level-cache = <&L2_3>;
131 fsl,portid-mapping = <0x20000000>;
137 model = "fsl,T4240QDS";
138 compatible = "fsl,T4240EMU", "fsl,T4240QDS";
139 #address-cells = <2>;
141 interrupt-parent = <&mpic>;
143 ifc: localbus@ffe124000 {
144 reg = <0xf 0xfe124000 0 0x2000>;
145 ranges = <0 0 0xf 0xe8000000 0x08000000
146 2 0 0xf 0xff800000 0x00010000
147 3 0 0xf 0xffdf0000 0x00008000>;
150 #address-cells = <1>;
152 compatible = "cfi-flash";
153 reg = <0x0 0x0 0x8000000>;
162 device_type = "memory";
166 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
167 reg = <0xf 0xfe000000 0 0x00001000>;
173 #address-cells = <2>;
175 compatible = "fsl,ifc", "simple-bus";
176 interrupts = <25 2 0 0>;
180 #address-cells = <1>;
183 compatible = "simple-bus";
186 compatible = "fsl,soc-sram-error";
187 interrupts = <16 2 1 29>;
191 compatible = "fsl,corenet-law";
196 ddr1: memory-controller@8000 {
197 compatible = "fsl,qoriq-memory-controller-v4.7",
198 "fsl,qoriq-memory-controller";
199 reg = <0x8000 0x1000>;
200 interrupts = <16 2 1 23>;
203 ddr2: memory-controller@9000 {
204 compatible = "fsl,qoriq-memory-controller-v4.7",
205 "fsl,qoriq-memory-controller";
206 reg = <0x9000 0x1000>;
207 interrupts = <16 2 1 22>;
210 ddr3: memory-controller@a000 {
211 compatible = "fsl,qoriq-memory-controller-v4.7",
212 "fsl,qoriq-memory-controller";
213 reg = <0xa000 0x1000>;
214 interrupts = <16 2 1 21>;
217 cpc: l3-cache-controller@10000 {
218 compatible = "fsl,t4240-l3-cache-controller", "cache";
219 reg = <0x10000 0x1000
222 interrupts = <16 2 1 27
228 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
229 reg = <0x18000 0x1000>;
230 interrupts = <16 2 1 31>;
231 fsl,ccf-num-csdids = <32>;
232 fsl,ccf-num-snoopids = <32>;
236 compatible = "fsl,pamu-v1.0", "fsl,pamu";
237 reg = <0x20000 0x6000>;
238 fsl,portid-mapping = <0x8000>;
244 /include/ "fsl/qoriq-mpic.dtsi"
246 guts: global-utilities@e0000 {
247 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
248 reg = <0xe0000 0xe00>;
250 fsl,liodn-bits = <12>;
253 /include/ "fsl/qoriq-clockgen2.dtsi"
254 global-utilities@e1000 {
255 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
258 /include/ "fsl/qoriq-dma-0.dtsi"
259 /include/ "fsl/qoriq-dma-1.dtsi"
261 /include/ "fsl/qoriq-i2c-0.dtsi"
262 /include/ "fsl/qoriq-i2c-1.dtsi"
263 /include/ "fsl/qoriq-duart-0.dtsi"
264 /include/ "fsl/qoriq-duart-1.dtsi"
266 L2_1: l2-cache-controller@c20000 {
267 compatible = "fsl,t4240-l2-cache-controller";
268 reg = <0xc20000 0x40000>;
269 next-level-cache = <&cpc>;
271 L2_2: l2-cache-controller@c60000 {
272 compatible = "fsl,t4240-l2-cache-controller";
273 reg = <0xc60000 0x40000>;
274 next-level-cache = <&cpc>;
276 L2_3: l2-cache-controller@ca0000 {
277 compatible = "fsl,t4240-l2-cache-controller";
278 reg = <0xca0000 0x40000>;
279 next-level-cache = <&cpc>;