1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
2 #define _ASM_POWERPC_MMU_HASH64_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
19 * This is necessary to get the definition of PGTABLE_RANGE which we
20 * need for various slices related matters. Note that this isn't the
21 * complete pgtable.h but only a portion of it.
23 #include <asm/pgtable-ppc64.h>
25 #include <asm/processor.h>
31 #define SLB_NUM_BOLTED 3
32 #define SLB_CACHE_ENTRIES 8
33 #define SLB_MIN_SIZE 32
35 /* Bits in the SLB ESID word */
36 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
38 /* Bits in the SLB VSID word */
39 #define SLB_VSID_SHIFT 12
40 #define SLB_VSID_SHIFT_1T 24
41 #define SLB_VSID_SSIZE_SHIFT 62
42 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
43 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
44 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
45 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
46 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
47 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
48 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
49 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
50 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
51 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
52 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
53 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
54 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
55 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
57 #define SLB_VSID_KERNEL (SLB_VSID_KP)
58 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
60 #define SLBIE_C (0x08000000)
61 #define SLBIE_SSIZE_SHIFT 25
67 #define HPTES_PER_GROUP 8
69 #define HPTE_V_SSIZE_SHIFT 62
70 #define HPTE_V_AVPN_SHIFT 7
71 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
72 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
73 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
74 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
75 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
76 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
77 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
78 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
80 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
81 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
82 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
83 #define HPTE_R_RPN_SHIFT 12
84 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
85 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
86 #define HPTE_R_N ASM_CONST(0x0000000000000004)
87 #define HPTE_R_G ASM_CONST(0x0000000000000008)
88 #define HPTE_R_M ASM_CONST(0x0000000000000010)
89 #define HPTE_R_I ASM_CONST(0x0000000000000020)
90 #define HPTE_R_W ASM_CONST(0x0000000000000040)
91 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
92 #define HPTE_R_C ASM_CONST(0x0000000000000080)
93 #define HPTE_R_R ASM_CONST(0x0000000000000100)
94 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
96 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
97 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
99 /* Values for PP (assumes Ks=0, Kp=1) */
100 #define PP_RWXX 0 /* Supervisor read/write, User none */
101 #define PP_RWRX 1 /* Supervisor read/write, User read */
102 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
103 #define PP_RXRX 3 /* Supervisor read, User read */
104 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
106 /* Fields for tlbiel instruction in architecture 2.06 */
107 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
108 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
109 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
110 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
111 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
112 #define TLBIEL_INVAL_SET_SHIFT 12
114 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
123 extern struct hash_pte *htab_address;
124 extern unsigned long htab_size_bytes;
125 extern unsigned long htab_hash_mask;
128 * Page size definition
130 * shift : is the "PAGE_SHIFT" value for that page size
131 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
132 * directly to a slbmte "vsid" value
133 * penc : is the HPTE encoding mask for the "LP" field:
138 unsigned int shift; /* number of bits */
139 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
140 unsigned int tlbiel; /* tlbiel supported for that page size */
141 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
142 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
144 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
146 static inline int shift_to_mmu_psize(unsigned int shift)
150 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
151 if (mmu_psize_defs[psize].shift == shift)
156 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
158 if (mmu_psize_defs[mmu_psize].shift)
159 return mmu_psize_defs[mmu_psize].shift;
163 #endif /* __ASSEMBLY__ */
167 * These are the values used by hardware in the B field of
168 * SLB entries and the first dword of MMU hashtable entries.
169 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
171 #define MMU_SEGSIZE_256M 0
172 #define MMU_SEGSIZE_1T 1
175 * encode page number shift.
176 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
177 * 12 bits. This enable us to address upto 76 bit va.
178 * For hpt hash from a va we can ignore the page size bits of va and for
179 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
180 * we work in all cases including 4k page size.
185 * HPTE Large Page (LP) details
189 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
193 static inline int slb_vsid_shift(int ssize)
195 if (ssize == MMU_SEGSIZE_256M)
196 return SLB_VSID_SHIFT;
197 return SLB_VSID_SHIFT_1T;
200 static inline int segment_shift(int ssize)
202 if (ssize == MMU_SEGSIZE_256M)
208 * The current system page and segment sizes
210 extern int mmu_linear_psize;
211 extern int mmu_virtual_psize;
212 extern int mmu_vmalloc_psize;
213 extern int mmu_vmemmap_psize;
214 extern int mmu_io_psize;
215 extern int mmu_kernel_ssize;
216 extern int mmu_highuser_ssize;
217 extern u16 mmu_slb_size;
218 extern unsigned long tce_alloc_start, tce_alloc_end;
221 * If the processor supports 64k normal pages but not 64k cache
222 * inhibited pages, we have to be prepared to switch processes
223 * to use 4k pages when they create cache-inhibited mappings.
224 * If this is the case, mmu_ci_restrictions will be set to 1.
226 extern int mmu_ci_restrictions;
229 * This computes the AVPN and B fields of the first dword of a HPTE,
230 * for use when we want to match an existing PTE. The bottom 7 bits
231 * of the returned value are zero.
233 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
238 * The AVA field omits the low-order 23 bits of the 78 bits VA.
239 * These bits are not needed in the PTE, because the
240 * low-order b of these bits are part of the byte offset
241 * into the virtual page and, if b < 23, the high-order
242 * 23-b of these bits are always used in selecting the
243 * PTEGs to be searched
245 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
246 v <<= HPTE_V_AVPN_SHIFT;
247 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
252 * This function sets the AVPN and L fields of the HPTE appropriately
253 * using the base page size and actual page size.
255 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
256 int actual_psize, int ssize)
259 v = hpte_encode_avpn(vpn, base_psize, ssize);
260 if (actual_psize != MMU_PAGE_4K)
266 * This function sets the ARPN, and LP fields of the HPTE appropriately
267 * for the page size. We assume the pa is already "clean" that is properly
268 * aligned for the requested page size
270 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
273 /* A 4K page needs no special encoding */
274 if (actual_psize == MMU_PAGE_4K)
275 return pa & HPTE_R_RPN;
277 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
278 unsigned int shift = mmu_psize_defs[actual_psize].shift;
279 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
284 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
286 static inline unsigned long hpt_vpn(unsigned long ea,
287 unsigned long vsid, int ssize)
290 int s_shift = segment_shift(ssize);
292 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
293 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
297 * This hashes a virtual address
299 static inline unsigned long hpt_hash(unsigned long vpn,
300 unsigned int shift, int ssize)
303 unsigned long hash, vsid;
305 /* VPN_SHIFT can be atmost 12 */
306 if (ssize == MMU_SEGSIZE_256M) {
307 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
308 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
309 ((vpn & mask) >> (shift - VPN_SHIFT));
311 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
312 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
313 hash = vsid ^ (vsid << 25) ^
314 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
316 return hash & 0x7fffffffffUL;
319 #define HPTE_LOCAL_UPDATE 0x1
320 #define HPTE_NOHPTE_UPDATE 0x2
322 extern int __hash_page_4K(unsigned long ea, unsigned long access,
323 unsigned long vsid, pte_t *ptep, unsigned long trap,
324 unsigned long flags, int ssize, int subpage_prot);
325 extern int __hash_page_64K(unsigned long ea, unsigned long access,
326 unsigned long vsid, pte_t *ptep, unsigned long trap,
327 unsigned long flags, int ssize);
329 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
330 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
331 unsigned long access, unsigned long trap,
332 unsigned long flags);
333 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
334 unsigned long dsisr);
335 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
336 pte_t *ptep, unsigned long trap, unsigned long flags,
337 int ssize, unsigned int shift, unsigned int mmu_psize);
338 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
339 extern int __hash_page_thp(unsigned long ea, unsigned long access,
340 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
341 unsigned long flags, int ssize, unsigned int psize);
343 static inline int __hash_page_thp(unsigned long ea, unsigned long access,
344 unsigned long vsid, pmd_t *pmdp,
345 unsigned long trap, unsigned long flags,
346 int ssize, unsigned int psize)
352 extern void hash_failure_debug(unsigned long ea, unsigned long access,
353 unsigned long vsid, unsigned long trap,
354 int ssize, int psize, int lpsize,
356 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
357 unsigned long pstart, unsigned long prot,
358 int psize, int ssize);
359 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
360 int psize, int ssize);
361 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
362 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
364 extern void hpte_init_native(void);
365 extern void hpte_init_lpar(void);
366 extern void hpte_init_beat(void);
367 extern void hpte_init_beat_v3(void);
369 extern void slb_initialize(void);
370 extern void slb_flush_and_rebolt(void);
372 extern void slb_vmalloc_update(void);
373 extern void slb_set_size(u16 size);
374 #endif /* __ASSEMBLY__ */
377 * VSID allocation (256MB segment)
379 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
380 * from mmu context id and effective segment id of the address.
382 * For user processes max context id is limited to ((1ul << 19) - 5)
383 * for kernel space, we use the top 4 context ids to map address as below
384 * NOTE: each context only support 64TB now.
385 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
386 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
387 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
388 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
390 * The proto-VSIDs are then scrambled into real VSIDs with the
391 * multiplicative hash:
393 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
395 * VSID_MULTIPLIER is prime, so in particular it is
396 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
397 * Because the modulus is 2^n-1 we can compute it efficiently without
398 * a divide or extra multiply (see below). The scramble function gives
399 * robust scattering in the hash table (at least based on some initial
402 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
403 * bad address. This enables us to consolidate bad address handling in
406 * We also need to avoid the last segment of the last context, because that
407 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
408 * because of the modulo operation in vsid scramble. But the vmemmap
409 * (which is what uses region 0xf) will never be close to 64TB in size
410 * (it's 56 bytes per page of system memory).
413 #define CONTEXT_BITS 19
415 #define ESID_BITS_1T 6
419 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
420 * available for user + kernel mapping. The top 4 contexts are used for
421 * kernel mapping. Each segment contains 2^28 bytes. Each
422 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
423 * (19 == 37 + 28 - 46).
425 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
428 * This should be computed such that protovosid * vsid_mulitplier
429 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
431 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
432 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
433 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
435 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
436 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
437 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
440 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
443 * This macro generates asm code to compute the VSID scramble
444 * function. Used in slb_allocate() and do_stab_bolted. The function
445 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
447 * rt = register continaing the proto-VSID and into which the
448 * VSID will be stored
449 * rx = scratch register (clobbered)
451 * - rt and rx must be different registers
452 * - The answer will end up in the low VSID_BITS bits of rt. The higher
453 * bits may contain other garbage, so you may need to mask the
456 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
457 lis rx,VSID_MULTIPLIER_##size@h; \
458 ori rx,rx,VSID_MULTIPLIER_##size@l; \
459 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
461 srdi rx,rt,VSID_BITS_##size; \
462 clrldi rt,rt,(64-VSID_BITS_##size); \
463 add rt,rt,rx; /* add high and low bits */ \
464 /* NOTE: explanation based on VSID_BITS_##size = 36 \
465 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
466 * 2^36-1+2^28-1. That in particular means that if r3 >= \
467 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
468 * the bit clear, r3 already has the answer we want, if it \
469 * doesn't, the answer is the low 36 bits of r3+1. So in all \
470 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
472 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
475 /* 4 bits per slice and we have one slice per 1TB */
476 #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
480 #ifdef CONFIG_PPC_SUBPAGE_PROT
482 * For the sub-page protection option, we extend the PGD with one of
483 * these. Basically we have a 3-level tree, with the top level being
484 * the protptrs array. To optimize speed and memory consumption when
485 * only addresses < 4GB are being protected, pointers to the first
486 * four pages of sub-page protection words are stored in the low_prot
488 * Each page of sub-page protection words protects 1GB (4 bytes
489 * protects 64k). For the 3-level tree, each page of pointers then
492 struct subpage_prot_table {
493 unsigned long maxaddr; /* only addresses < this are protected */
494 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
495 unsigned int *low_prot[4];
498 #define SBP_L1_BITS (PAGE_SHIFT - 2)
499 #define SBP_L2_BITS (PAGE_SHIFT - 3)
500 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
501 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
502 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
503 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
505 extern void subpage_prot_free(struct mm_struct *mm);
506 extern void subpage_prot_init_new_context(struct mm_struct *mm);
508 static inline void subpage_prot_free(struct mm_struct *mm) {}
509 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
510 #endif /* CONFIG_PPC_SUBPAGE_PROT */
512 typedef unsigned long mm_context_id_t;
517 u16 user_psize; /* page size index */
519 #ifdef CONFIG_PPC_MM_SLICES
520 u64 low_slices_psize; /* SLB page size encodings */
521 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
523 u16 sllp; /* SLB page size encoding */
525 unsigned long vdso_base;
526 #ifdef CONFIG_PPC_SUBPAGE_PROT
527 struct subpage_prot_table spt;
528 #endif /* CONFIG_PPC_SUBPAGE_PROT */
529 #ifdef CONFIG_PPC_ICSWX
530 struct spinlock *cop_lockp; /* guard acop and cop_pid */
531 unsigned long acop; /* mask of enabled coprocessor types */
532 unsigned int cop_pid; /* pid value used with coprocessors */
533 #endif /* CONFIG_PPC_ICSWX */
534 #ifdef CONFIG_PPC_64K_PAGES
535 /* for 4K PTE fragment support */
543 * The code below is equivalent to this function for arguments
544 * < 2^VSID_BITS, which is all this should ever be called
545 * with. However gcc is not clever enough to compute the
546 * modulus (2^n-1) without a second multiply.
548 #define vsid_scramble(protovsid, size) \
549 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
552 #define vsid_scramble(protovsid, size) \
555 x = (protovsid) * VSID_MULTIPLIER_##size; \
556 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
557 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
561 /* Returns the segment size indicator for a user address */
562 static inline int user_segment_size(unsigned long addr)
564 /* Use 1T segments if possible for addresses >= 1T */
565 if (addr >= (1UL << SID_SHIFT_1T))
566 return mmu_highuser_ssize;
567 return MMU_SEGSIZE_256M;
570 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
574 * Bad address. We return VSID 0 for that
576 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
579 if (ssize == MMU_SEGSIZE_256M)
580 return vsid_scramble((context << ESID_BITS)
581 | (ea >> SID_SHIFT), 256M);
582 return vsid_scramble((context << ESID_BITS_1T)
583 | (ea >> SID_SHIFT_1T), 1T);
587 * This is only valid for addresses >= PAGE_OFFSET
589 * For kernel space, we use the top 4 context ids to map address as below
590 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
591 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
592 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
593 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
595 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
597 unsigned long context;
600 * kernel take the top 4 context from the available range
602 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
603 return get_vsid(context, ea, ssize);
605 #endif /* __ASSEMBLY__ */
607 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */