arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * OPAL API definitions.
   3  *
   4  * Copyright 2011-2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_EMPTY              -16
  35 #define OPAL_I2C_TIMEOUT        -17
  36 #define OPAL_I2C_INVALID_CMD    -18
  37 #define OPAL_I2C_LBUS_PARITY    -19
  38 #define OPAL_I2C_BKEND_OVERRUN  -20
  39 #define OPAL_I2C_BKEND_ACCESS   -21
  40 #define OPAL_I2C_ARBT_LOST      -22
  41 #define OPAL_I2C_NACK_RCVD      -23
  42 #define OPAL_I2C_STOP_ERR       -24
  43
  44 /* API Tokens (in r0) */
  45 #define OPAL_INVALID_CALL                      -1
  46 #define OPAL_TEST                               0
  47 #define OPAL_CONSOLE_WRITE                      1
  48 #define OPAL_CONSOLE_READ                       2
  49 #define OPAL_RTC_READ                           3
  50 #define OPAL_RTC_WRITE                          4
  51 #define OPAL_CEC_POWER_DOWN                     5
  52 #define OPAL_CEC_REBOOT                         6
  53 #define OPAL_READ_NVRAM                         7
  54 #define OPAL_WRITE_NVRAM                        8
  55 #define OPAL_HANDLE_INTERRUPT                   9
  56 #define OPAL_POLL_EVENTS                        10
  57 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  58 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  59 #define OPAL_PCI_CONFIG_READ_BYTE               13
  60 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  61 #define OPAL_PCI_CONFIG_READ_WORD               15
  62 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  64 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  65 #define OPAL_SET_XIVE                           19
  66 #define OPAL_GET_XIVE                           20
  67 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  69 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  70 #define OPAL_PCI_SHPC                           24
  71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  72 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  73 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  74 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  77 #define OPAL_PCI_SET_PE                         31
  78 #define OPAL_PCI_SET_PELTV                      32
  79 #define OPAL_PCI_SET_MVE                        33
  80 #define OPAL_PCI_SET_MVE_ENABLE                 34
  81 #define OPAL_PCI_GET_XIVE_REISSUE               35
  82 #define OPAL_PCI_SET_XIVE_REISSUE               36
  83 #define OPAL_PCI_SET_XIVE_PE                    37
  84 #define OPAL_GET_XIVE_SOURCE                    38
  85 #define OPAL_GET_MSI_32                         39
  86 #define OPAL_GET_MSI_64                         40
  87 #define OPAL_START_CPU                          41
  88 #define OPAL_QUERY_CPU_STATUS                   42
  89 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
  90 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  92 #define OPAL_PCI_RESET                          49
  93 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  94 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  95 #define OPAL_PCI_FENCE_PHB                      52
  96 #define OPAL_PCI_REINIT                         53
  97 #define OPAL_PCI_MASK_PE_ERROR                  54
  98 #define OPAL_SET_SLOT_LED_STATUS                55
  99 #define OPAL_GET_EPOW_STATUS                    56
 100 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 101 #define OPAL_RESERVED1                          58
 102 #define OPAL_RESERVED2                          59
 103 #define OPAL_PCI_NEXT_ERROR                     60
 104 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 105 #define OPAL_PCI_POLL                           62
 106 #define OPAL_PCI_MSI_EOI                        63
 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 108 #define OPAL_XSCOM_READ                         65
 109 #define OPAL_XSCOM_WRITE                        66
 110 #define OPAL_LPC_READ                           67
 111 #define OPAL_LPC_WRITE                          68
 112 #define OPAL_RETURN_CPU                         69
 113 #define OPAL_REINIT_CPUS                        70
 114 #define OPAL_ELOG_READ                          71
 115 #define OPAL_ELOG_WRITE                         72
 116 #define OPAL_ELOG_ACK                           73
 117 #define OPAL_ELOG_RESEND                        74
 118 #define OPAL_ELOG_SIZE                          75
 119 #define OPAL_FLASH_VALIDATE                     76
 120 #define OPAL_FLASH_MANAGE                       77
 121 #define OPAL_FLASH_UPDATE                       78
 122 #define OPAL_RESYNC_TIMEBASE                    79
 123 #define OPAL_CHECK_TOKEN                        80
 124 #define OPAL_DUMP_INIT                          81
 125 #define OPAL_DUMP_INFO                          82
 126 #define OPAL_DUMP_READ                          83
 127 #define OPAL_DUMP_ACK                           84
 128 #define OPAL_GET_MSG                            85
 129 #define OPAL_CHECK_ASYNC_COMPLETION             86
 130 #define OPAL_SYNC_HOST_REBOOT                   87
 131 #define OPAL_SENSOR_READ                        88
 132 #define OPAL_GET_PARAM                          89
 133 #define OPAL_SET_PARAM                          90
 134 #define OPAL_DUMP_RESEND                        91
 135 #define OPAL_ELOG_SEND                          92      /* Deprecated */
 136 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
 137 #define OPAL_DUMP_INFO2                         94
 138 #define OPAL_WRITE_OPPANEL_ASYNC                95
 139 #define OPAL_PCI_ERR_INJECT                     96
 140 #define OPAL_PCI_EEH_FREEZE_SET                 97
 141 #define OPAL_HANDLE_HMI                         98
 142 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 143 #define OPAL_SLW_SET_REG                        100
 144 #define OPAL_REGISTER_DUMP_REGION               101
 145 #define OPAL_UNREGISTER_DUMP_REGION             102
 146 #define OPAL_WRITE_TPO                          103
 147 #define OPAL_READ_TPO                           104
 148 #define OPAL_GET_DPO_STATUS                     105
 149 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
 150 #define OPAL_IPMI_SEND                          107
 151 #define OPAL_IPMI_RECV                          108
 152 #define OPAL_I2C_REQUEST                        109
 153 #define OPAL_FLASH_READ                         110
 154 #define OPAL_FLASH_WRITE                        111
 155 #define OPAL_FLASH_ERASE                        112
 156 #define OPAL_PRD_MSG                            113
 157 #define OPAL_LEDS_GET_INDICATOR                 114
 158 #define OPAL_LEDS_SET_INDICATOR                 115
 159 #define OPAL_CEC_REBOOT2                        116
 160 #define OPAL_CONSOLE_FLUSH                      117
 161 #define OPAL_GET_DEVICE_TREE                    118
 162 #define OPAL_PCI_GET_PRESENCE_STATE             119
 163 #define OPAL_PCI_GET_POWER_STATE                120
 164 #define OPAL_PCI_SET_POWER_STATE                121
 165 #define OPAL_INT_GET_XIRR                       122
 166 #define OPAL_INT_SET_CPPR                       123
 167 #define OPAL_INT_EOI                            124
 168 #define OPAL_INT_SET_MFRR                       125
 169 #define OPAL_PCI_TCE_KILL                       126
 170 #define OPAL_LAST                               126
 171
 172 /* Device tree flags */
 173
 174 /*
 175  * Flags set in power-mgmt nodes in device tree describing
 176  * idle states that are supported in the platform.
 177  */
 178
 179 #define OPAL_PM_TIMEBASE_STOP           0x00000002
 180 #define OPAL_PM_LOSE_HYP_CONTEXT        0x00002000
 181 #define OPAL_PM_LOSE_FULL_CONTEXT       0x00004000
 182 #define OPAL_PM_NAP_ENABLED             0x00010000
 183 #define OPAL_PM_SLEEP_ENABLED           0x00020000
 184 #define OPAL_PM_WINKLE_ENABLED          0x00040000
 185 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
 186 #define OPAL_PM_STOP_INST_FAST          0x00100000
 187 #define OPAL_PM_STOP_INST_DEEP          0x00200000
 188
 189 /*
 190  * OPAL_CONFIG_CPU_IDLE_STATE parameters
 191  */
 192 #define OPAL_CONFIG_IDLE_FASTSLEEP      1
 193 #define OPAL_CONFIG_IDLE_UNDO           0
 194 #define OPAL_CONFIG_IDLE_APPLY          1
 195
 196 #ifndef __ASSEMBLY__
 197
 198 /* Other enums */
 199 enum OpalFreezeState {
 200         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 201         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 202         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 203         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 204         OPAL_EEH_STOPPED_RESET = 4,
 205         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 206         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 207 };
 208
 209 enum OpalEehFreezeActionToken {
 210         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 211         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 212         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 213
 214         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 215         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 216         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 217 };
 218
 219 enum OpalPciStatusToken {
 220         OPAL_EEH_NO_ERROR       = 0,
 221         OPAL_EEH_IOC_ERROR      = 1,
 222         OPAL_EEH_PHB_ERROR      = 2,
 223         OPAL_EEH_PE_ERROR       = 3,
 224         OPAL_EEH_PE_MMIO_ERROR  = 4,
 225         OPAL_EEH_PE_DMA_ERROR   = 5
 226 };
 227
 228 enum OpalPciErrorSeverity {
 229         OPAL_EEH_SEV_NO_ERROR   = 0,
 230         OPAL_EEH_SEV_IOC_DEAD   = 1,
 231         OPAL_EEH_SEV_PHB_DEAD   = 2,
 232         OPAL_EEH_SEV_PHB_FENCED = 3,
 233         OPAL_EEH_SEV_PE_ER      = 4,
 234         OPAL_EEH_SEV_INF        = 5
 235 };
 236
 237 enum OpalErrinjectType {
 238         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 239         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 240 };
 241
 242 enum OpalErrinjectFunc {
 243         /* IOA bus specific errors */
 244         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 245         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 246         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 247         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 248         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 249         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 250         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 251         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 252         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 253         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 254         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 255         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 256         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 257         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 258         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 259         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 260         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 261         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 262         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 263         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 264 };
 265
 266 enum OpalMmioWindowType {
 267         OPAL_M32_WINDOW_TYPE = 1,
 268         OPAL_M64_WINDOW_TYPE = 2,
 269         OPAL_IO_WINDOW_TYPE  = 3
 270 };
 271
 272 enum OpalExceptionHandler {
 273         OPAL_MACHINE_CHECK_HANDLER          = 1,
 274         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 275         OPAL_SOFTPATCH_HANDLER              = 3
 276 };
 277
 278 enum OpalPendingState {
 279         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
 280         OPAL_EVENT_NVRAM           = 0x2,
 281         OPAL_EVENT_RTC             = 0x4,
 282         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
 283         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
 284         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 285         OPAL_EVENT_ERROR_LOG       = 0x40,
 286         OPAL_EVENT_EPOW            = 0x80,
 287         OPAL_EVENT_LED_STATUS      = 0x100,
 288         OPAL_EVENT_PCI_ERROR       = 0x200,
 289         OPAL_EVENT_DUMP_AVAIL      = 0x400,
 290         OPAL_EVENT_MSG_PENDING     = 0x800,
 291 };
 292
 293 enum OpalThreadStatus {
 294         OPAL_THREAD_INACTIVE = 0x0,
 295         OPAL_THREAD_STARTED = 0x1,
 296         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 297 };
 298
 299 enum OpalPciBusCompare {
 300         OpalPciBusAny   = 0,    /* Any bus number match */
 301         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 302         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 303         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 304         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 305         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 306         OpalPciBusAll   = 7,    /* Match bus number exactly */
 307 };
 308
 309 enum OpalDeviceCompare {
 310         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 311         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 312 };
 313
 314 enum OpalFuncCompare {
 315         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 316         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 317 };
 318
 319 enum OpalPeAction {
 320         OPAL_UNMAP_PE = 0,
 321         OPAL_MAP_PE = 1
 322 };
 323
 324 enum OpalPeltvAction {
 325         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 326         OPAL_ADD_PE_TO_DOMAIN = 1
 327 };
 328
 329 enum OpalMveEnableAction {
 330         OPAL_DISABLE_MVE = 0,
 331         OPAL_ENABLE_MVE = 1
 332 };
 333
 334 enum OpalM64Action {
 335         OPAL_DISABLE_M64 = 0,
 336         OPAL_ENABLE_M64_SPLIT = 1,
 337         OPAL_ENABLE_M64_NON_SPLIT = 2
 338 };
 339
 340 enum OpalPciResetScope {
 341         OPAL_RESET_PHB_COMPLETE         = 1,
 342         OPAL_RESET_PCI_LINK             = 2,
 343         OPAL_RESET_PHB_ERROR            = 3,
 344         OPAL_RESET_PCI_HOT              = 4,
 345         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 346         OPAL_RESET_PCI_IODA_TABLE       = 6
 347 };
 348
 349 enum OpalPciReinitScope {
 350         /*
 351          * Note: we chose values that do not overlap
 352          * OpalPciResetScope as OPAL v2 used the same
 353          * enum for both
 354          */
 355         OPAL_REINIT_PCI_DEV = 1000
 356 };
 357
 358 enum OpalPciResetState {
 359         OPAL_DEASSERT_RESET = 0,
 360         OPAL_ASSERT_RESET   = 1
 361 };
 362
 363 enum OpalPciSlotPresence {
 364         OPAL_PCI_SLOT_EMPTY     = 0,
 365         OPAL_PCI_SLOT_PRESENT   = 1
 366 };
 367
 368 enum OpalPciSlotPower {
 369         OPAL_PCI_SLOT_POWER_OFF = 0,
 370         OPAL_PCI_SLOT_POWER_ON  = 1,
 371         OPAL_PCI_SLOT_OFFLINE   = 2,
 372         OPAL_PCI_SLOT_ONLINE    = 3
 373 };
 374
 375 enum OpalSlotLedType {
 376         OPAL_SLOT_LED_TYPE_ID = 0,      /* IDENTIFY LED */
 377         OPAL_SLOT_LED_TYPE_FAULT = 1,   /* FAULT LED */
 378         OPAL_SLOT_LED_TYPE_ATTN = 2,    /* System Attention LED */
 379         OPAL_SLOT_LED_TYPE_MAX = 3
 380 };
 381
 382 enum OpalSlotLedState {
 383         OPAL_SLOT_LED_STATE_OFF = 0,    /* LED is OFF */
 384         OPAL_SLOT_LED_STATE_ON = 1      /* LED is ON */
 385 };
 386
 387 /*
 388  * Address cycle types for LPC accesses. These also correspond
 389  * to the content of the first cell of the "reg" property for
 390  * device nodes on the LPC bus
 391  */
 392 enum OpalLPCAddressType {
 393         OPAL_LPC_MEM    = 0,
 394         OPAL_LPC_IO     = 1,
 395         OPAL_LPC_FW     = 2,
 396 };
 397
 398 enum opal_msg_type {
 399         OPAL_MSG_ASYNC_COMP     = 0,    /* params[0] = token, params[1] = rc,
 400                                          * additional params function-specific
 401                                          */
 402         OPAL_MSG_MEM_ERR        = 1,
 403         OPAL_MSG_EPOW           = 2,
 404         OPAL_MSG_SHUTDOWN       = 3,    /* params[0] = 1 reboot, 0 shutdown */
 405         OPAL_MSG_HMI_EVT        = 4,
 406         OPAL_MSG_DPO            = 5,
 407         OPAL_MSG_PRD            = 6,
 408         OPAL_MSG_OCC            = 7,
 409         OPAL_MSG_TYPE_MAX,
 410 };
 411
 412 struct opal_msg {
 413         __be32 msg_type;
 414         __be32 reserved;
 415         __be64 params[8];
 416 };
 417
 418 /* System parameter permission */
 419 enum OpalSysparamPerm {
 420         OPAL_SYSPARAM_READ  = 0x1,
 421         OPAL_SYSPARAM_WRITE = 0x2,
 422         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 423 };
 424
 425 enum {
 426         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 427 };
 428
 429 struct opal_ipmi_msg {
 430         uint8_t version;
 431         uint8_t netfn;
 432         uint8_t cmd;
 433         uint8_t data[];
 434 };
 435
 436 /* FSP memory errors handling */
 437 enum OpalMemErr_Version {
 438         OpalMemErr_V1 = 1,
 439 };
 440
 441 enum OpalMemErrType {
 442         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 443         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 444 };
 445
 446 /* Memory Reilience error type */
 447 enum OpalMemErr_ResilErrType {
 448         OPAL_MEM_RESILIENCE_CE          = 0,
 449         OPAL_MEM_RESILIENCE_UE,
 450         OPAL_MEM_RESILIENCE_UE_SCRUB,
 451 };
 452
 453 /* Dynamic Memory Deallocation type */
 454 enum OpalMemErr_DynErrType {
 455         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 456 };
 457
 458 struct OpalMemoryErrorData {
 459         enum OpalMemErr_Version version:8;      /* 0x00 */
 460         enum OpalMemErrType     type:8;         /* 0x01 */
 461         __be16                  flags;          /* 0x02 */
 462         uint8_t                 reserved_1[4];  /* 0x04 */
 463
 464         union {
 465                 /* Memory Resilience corrected/uncorrected error info */
 466                 struct {
 467                         enum OpalMemErr_ResilErrType    resil_err_type:8;
 468                         uint8_t                         reserved_1[7];
 469                         __be64                          physical_address_start;
 470                         __be64                          physical_address_end;
 471                 } resilience;
 472                 /* Dynamic memory deallocation error info */
 473                 struct {
 474                         enum OpalMemErr_DynErrType      dyn_err_type:8;
 475                         uint8_t                         reserved_1[7];
 476                         __be64                          physical_address_start;
 477                         __be64                          physical_address_end;
 478                 } dyn_dealloc;
 479         } u;
 480 };
 481
 482 /* HMI interrupt event */
 483 enum OpalHMI_Version {
 484         OpalHMIEvt_V1 = 1,
 485         OpalHMIEvt_V2 = 2,
 486 };
 487
 488 enum OpalHMI_Severity {
 489         OpalHMI_SEV_NO_ERROR = 0,
 490         OpalHMI_SEV_WARNING = 1,
 491         OpalHMI_SEV_ERROR_SYNC = 2,
 492         OpalHMI_SEV_FATAL = 3,
 493 };
 494
 495 enum OpalHMI_Disposition {
 496         OpalHMI_DISPOSITION_RECOVERED = 0,
 497         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 498 };
 499
 500 enum OpalHMI_ErrType {
 501         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 502         OpalHMI_ERROR_PROC_RECOV_DONE,
 503         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 504         OpalHMI_ERROR_PROC_RECOV_MASKED,
 505         OpalHMI_ERROR_TFAC,
 506         OpalHMI_ERROR_TFMR_PARITY,
 507         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 508         OpalHMI_ERROR_XSCOM_FAIL,
 509         OpalHMI_ERROR_XSCOM_DONE,
 510         OpalHMI_ERROR_SCOM_FIR,
 511         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 512         OpalHMI_ERROR_HYP_RESOURCE,
 513         OpalHMI_ERROR_CAPP_RECOVERY,
 514 };
 515
 516 enum OpalHMI_XstopType {
 517         CHECKSTOP_TYPE_UNKNOWN  =       0,
 518         CHECKSTOP_TYPE_CORE     =       1,
 519         CHECKSTOP_TYPE_NX       =       2,
 520 };
 521
 522 enum OpalHMI_CoreXstopReason {
 523         CORE_CHECKSTOP_IFU_REGFILE              = 0x00000001,
 524         CORE_CHECKSTOP_IFU_LOGIC                = 0x00000002,
 525         CORE_CHECKSTOP_PC_DURING_RECOV          = 0x00000004,
 526         CORE_CHECKSTOP_ISU_REGFILE              = 0x00000008,
 527         CORE_CHECKSTOP_ISU_LOGIC                = 0x00000010,
 528         CORE_CHECKSTOP_FXU_LOGIC                = 0x00000020,
 529         CORE_CHECKSTOP_VSU_LOGIC                = 0x00000040,
 530         CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE   = 0x00000080,
 531         CORE_CHECKSTOP_LSU_REGFILE              = 0x00000100,
 532         CORE_CHECKSTOP_PC_FWD_PROGRESS          = 0x00000200,
 533         CORE_CHECKSTOP_LSU_LOGIC                = 0x00000400,
 534         CORE_CHECKSTOP_PC_LOGIC                 = 0x00000800,
 535         CORE_CHECKSTOP_PC_HYP_RESOURCE          = 0x00001000,
 536         CORE_CHECKSTOP_PC_HANG_RECOV_FAILED     = 0x00002000,
 537         CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED    = 0x00004000,
 538         CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ    = 0x00008000,
 539         CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ      = 0x00010000,
 540 };
 541
 542 enum OpalHMI_NestAccelXstopReason {
 543         NX_CHECKSTOP_SHM_INVAL_STATE_ERR        = 0x00000001,
 544         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1      = 0x00000002,
 545         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2      = 0x00000004,
 546         NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR    = 0x00000008,
 547         NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR    = 0x00000010,
 548         NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR    = 0x00000020,
 549         NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR    = 0x00000040,
 550         NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR    = 0x00000080,
 551         NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR    = 0x00000100,
 552         NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR    = 0x00000200,
 553         NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR    = 0x00000400,
 554         NX_CHECKSTOP_DMA_CRB_UE                 = 0x00000800,
 555         NX_CHECKSTOP_DMA_CRB_SUE                = 0x00001000,
 556         NX_CHECKSTOP_PBI_ISN_UE                 = 0x00002000,
 557 };
 558
 559 struct OpalHMIEvent {
 560         uint8_t         version;        /* 0x00 */
 561         uint8_t         severity;       /* 0x01 */
 562         uint8_t         type;           /* 0x02 */
 563         uint8_t         disposition;    /* 0x03 */
 564         uint8_t         reserved_1[4];  /* 0x04 */
 565
 566         __be64          hmer;
 567         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 568         __be64          tfmr;
 569
 570         /* version 2 and later */
 571         union {
 572                 /*
 573                  * checkstop info (Core/NX).
 574                  * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
 575                  */
 576                 struct {
 577                         uint8_t xstop_type;     /* enum OpalHMI_XstopType */
 578                         uint8_t reserved_1[3];
 579                         __be32  xstop_reason;
 580                         union {
 581                                 __be32 pir;     /* for CHECKSTOP_TYPE_CORE */
 582                                 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
 583                         } u;
 584                 } xstop_error;
 585         } u;
 586 };
 587
 588 enum {
 589         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 590         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 591         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 592         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 593         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 594         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 595         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 596 };
 597
 598 struct OpalIoP7IOCErrorData {
 599         __be16 type;
 600
 601         /* GEM */
 602         __be64 gemXfir;
 603         __be64 gemRfir;
 604         __be64 gemRirqfir;
 605         __be64 gemMask;
 606         __be64 gemRwof;
 607
 608         /* LEM */
 609         __be64 lemFir;
 610         __be64 lemErrMask;
 611         __be64 lemAction0;
 612         __be64 lemAction1;
 613         __be64 lemWof;
 614
 615         union {
 616                 struct OpalIoP7IOCRgcErrorData {
 617                         __be64 rgcStatus;       /* 3E1C10 */
 618                         __be64 rgcLdcp;         /* 3E1C18 */
 619                 }rgc;
 620                 struct OpalIoP7IOCBiErrorData {
 621                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 622                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 623                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 624                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 625
 626                         uint8_t biDownbound;    /* BI Downbound or Upbound */
 627                 }bi;
 628                 struct OpalIoP7IOCCiErrorData {
 629                         __be64 ciPortStatus;    /* 3Dn008 */
 630                         __be64 ciPortLdcp;      /* 3Dn010 */
 631
 632                         uint8_t ciPort;         /* Index of CI port: 0/1 */
 633                 }ci;
 634         };
 635 };
 636
 637 /**
 638  * This structure defines the overlay which will be used to store PHB error
 639  * data upon request.
 640  */
 641 enum {
 642         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 643 };
 644
 645 enum {
 646         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 647         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 648 };
 649
 650 enum {
 651         OPAL_P7IOC_NUM_PEST_REGS = 128,
 652         OPAL_PHB3_NUM_PEST_REGS = 256
 653 };
 654
 655 struct OpalIoPhbErrorCommon {
 656         __be32 version;
 657         __be32 ioType;
 658         __be32 len;
 659 };
 660
 661 struct OpalIoP7IOCPhbErrorData {
 662         struct OpalIoPhbErrorCommon common;
 663
 664         __be32 brdgCtl;
 665
 666         // P7IOC utl regs
 667         __be32 portStatusReg;
 668         __be32 rootCmplxStatus;
 669         __be32 busAgentStatus;
 670
 671         // P7IOC cfg regs
 672         __be32 deviceStatus;
 673         __be32 slotStatus;
 674         __be32 linkStatus;
 675         __be32 devCmdStatus;
 676         __be32 devSecStatus;
 677
 678         // cfg AER regs
 679         __be32 rootErrorStatus;
 680         __be32 uncorrErrorStatus;
 681         __be32 corrErrorStatus;
 682         __be32 tlpHdr1;
 683         __be32 tlpHdr2;
 684         __be32 tlpHdr3;
 685         __be32 tlpHdr4;
 686         __be32 sourceId;
 687
 688         __be32 rsv3;
 689
 690         // Record data about the call to allocate a buffer.
 691         __be64 errorClass;
 692         __be64 correlator;
 693
 694         //P7IOC MMIO Error Regs
 695         __be64 p7iocPlssr;                // n120
 696         __be64 p7iocCsr;                  // n110
 697         __be64 lemFir;                    // nC00
 698         __be64 lemErrorMask;              // nC18
 699         __be64 lemWOF;                    // nC40
 700         __be64 phbErrorStatus;            // nC80
 701         __be64 phbFirstErrorStatus;       // nC88
 702         __be64 phbErrorLog0;              // nCC0
 703         __be64 phbErrorLog1;              // nCC8
 704         __be64 mmioErrorStatus;           // nD00
 705         __be64 mmioFirstErrorStatus;      // nD08
 706         __be64 mmioErrorLog0;             // nD40
 707         __be64 mmioErrorLog1;             // nD48
 708         __be64 dma0ErrorStatus;           // nD80
 709         __be64 dma0FirstErrorStatus;      // nD88
 710         __be64 dma0ErrorLog0;             // nDC0
 711         __be64 dma0ErrorLog1;             // nDC8
 712         __be64 dma1ErrorStatus;           // nE00
 713         __be64 dma1FirstErrorStatus;      // nE08
 714         __be64 dma1ErrorLog0;             // nE40
 715         __be64 dma1ErrorLog1;             // nE48
 716         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 717         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 718 };
 719
 720 struct OpalIoPhb3ErrorData {
 721         struct OpalIoPhbErrorCommon common;
 722
 723         __be32 brdgCtl;
 724
 725         /* PHB3 UTL regs */
 726         __be32 portStatusReg;
 727         __be32 rootCmplxStatus;
 728         __be32 busAgentStatus;
 729
 730         /* PHB3 cfg regs */
 731         __be32 deviceStatus;
 732         __be32 slotStatus;
 733         __be32 linkStatus;
 734         __be32 devCmdStatus;
 735         __be32 devSecStatus;
 736
 737         /* cfg AER regs */
 738         __be32 rootErrorStatus;
 739         __be32 uncorrErrorStatus;
 740         __be32 corrErrorStatus;
 741         __be32 tlpHdr1;
 742         __be32 tlpHdr2;
 743         __be32 tlpHdr3;
 744         __be32 tlpHdr4;
 745         __be32 sourceId;
 746
 747         __be32 rsv3;
 748
 749         /* Record data about the call to allocate a buffer */
 750         __be64 errorClass;
 751         __be64 correlator;
 752
 753         /* PHB3 MMIO Error Regs */
 754         __be64 nFir;                    /* 000 */
 755         __be64 nFirMask;                /* 003 */
 756         __be64 nFirWOF;         /* 008 */
 757         __be64 phbPlssr;                /* 120 */
 758         __be64 phbCsr;          /* 110 */
 759         __be64 lemFir;          /* C00 */
 760         __be64 lemErrorMask;            /* C18 */
 761         __be64 lemWOF;          /* C40 */
 762         __be64 phbErrorStatus;  /* C80 */
 763         __be64 phbFirstErrorStatus;     /* C88 */
 764         __be64 phbErrorLog0;            /* CC0 */
 765         __be64 phbErrorLog1;            /* CC8 */
 766         __be64 mmioErrorStatus; /* D00 */
 767         __be64 mmioFirstErrorStatus;    /* D08 */
 768         __be64 mmioErrorLog0;           /* D40 */
 769         __be64 mmioErrorLog1;           /* D48 */
 770         __be64 dma0ErrorStatus; /* D80 */
 771         __be64 dma0FirstErrorStatus;    /* D88 */
 772         __be64 dma0ErrorLog0;           /* DC0 */
 773         __be64 dma0ErrorLog1;           /* DC8 */
 774         __be64 dma1ErrorStatus; /* E00 */
 775         __be64 dma1FirstErrorStatus;    /* E08 */
 776         __be64 dma1ErrorLog0;           /* E40 */
 777         __be64 dma1ErrorLog1;           /* E48 */
 778         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 779         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 780 };
 781
 782 enum {
 783         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 784         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 785 };
 786
 787 typedef struct oppanel_line {
 788         __be64 line;
 789         __be64 line_len;
 790 } oppanel_line_t;
 791
 792 enum opal_prd_msg_type {
 793         OPAL_PRD_MSG_TYPE_INIT = 0,     /* HBRT --> OPAL */
 794         OPAL_PRD_MSG_TYPE_FINI,         /* HBRT/kernel --> OPAL */
 795         OPAL_PRD_MSG_TYPE_ATTN,         /* HBRT <-- OPAL */
 796         OPAL_PRD_MSG_TYPE_ATTN_ACK,     /* HBRT --> OPAL */
 797         OPAL_PRD_MSG_TYPE_OCC_ERROR,    /* HBRT <-- OPAL */
 798         OPAL_PRD_MSG_TYPE_OCC_RESET,    /* HBRT <-- OPAL */
 799 };
 800
 801 struct opal_prd_msg_header {
 802         uint8_t         type;
 803         uint8_t         pad[1];
 804         __be16          size;
 805 };
 806
 807 struct opal_prd_msg;
 808
 809 #define OCC_RESET                       0
 810 #define OCC_LOAD                        1
 811 #define OCC_THROTTLE                    2
 812 #define OCC_MAX_THROTTLE_STATUS         5
 813
 814 struct opal_occ_msg {
 815         __be64 type;
 816         __be64 chip;
 817         __be64 throttle_status;
 818 };
 819
 820 /*
 821  * SG entries
 822  *
 823  * WARNING: The current implementation requires each entry
 824  * to represent a block that is 4k aligned *and* each block
 825  * size except the last one in the list to be as well.
 826  */
 827 struct opal_sg_entry {
 828         __be64 data;
 829         __be64 length;
 830 };
 831
 832 /*
 833  * Candidate image SG list.
 834  *
 835  * length = VER | length
 836  */
 837 struct opal_sg_list {
 838         __be64 length;
 839         __be64 next;
 840         struct opal_sg_entry entry[];
 841 };
 842
 843 /*
 844  * Dump region ID range usable by the OS
 845  */
 846 #define OPAL_DUMP_REGION_HOST_START             0x80
 847 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 848 #define OPAL_DUMP_REGION_HOST_END               0xFF
 849
 850 /* CAPI modes for PHB */
 851 enum {
 852         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 853         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 854         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 855         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 856         OPAL_PHB_CAPI_MODE_DMA          = 4,
 857 };
 858
 859 /* OPAL I2C request */
 860 struct opal_i2c_request {
 861         uint8_t type;
 862 #define OPAL_I2C_RAW_READ       0
 863 #define OPAL_I2C_RAW_WRITE      1
 864 #define OPAL_I2C_SM_READ        2
 865 #define OPAL_I2C_SM_WRITE       3
 866         uint8_t flags;
 867 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
 868         uint8_t subaddr_sz;             /* Max 4 */
 869         uint8_t reserved;
 870         __be16 addr;                    /* 7 or 10 bit address */
 871         __be16 reserved2;
 872         __be32 subaddr;         /* Sub-address if any */
 873         __be32 size;                    /* Data size */
 874         __be64 buffer_ra;               /* Buffer real address */
 875 };
 876
 877 /*
 878  * EPOW status sharing (OPAL and the host)
 879  *
 880  * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
 881  * with individual elements being 16 bits wide to fetch the system
 882  * wide EPOW status. Each element in the buffer will contain the
 883  * EPOW status in it's bit representation for a particular EPOW sub
 884  * class as defined here. So multiple detailed EPOW status bits
 885  * specific for any sub class can be represented in a single buffer
 886  * element as it's bit representation.
 887  */
 888
 889 /* System EPOW type */
 890 enum OpalSysEpow {
 891         OPAL_SYSEPOW_POWER      = 0,    /* Power EPOW */
 892         OPAL_SYSEPOW_TEMP       = 1,    /* Temperature EPOW */
 893         OPAL_SYSEPOW_COOLING    = 2,    /* Cooling EPOW */
 894         OPAL_SYSEPOW_MAX        = 3,    /* Max EPOW categories */
 895 };
 896
 897 /* Power EPOW */
 898 enum OpalSysPower {
 899         OPAL_SYSPOWER_UPS       = 0x0001, /* System on UPS power */
 900         OPAL_SYSPOWER_CHNG      = 0x0002, /* System power config change */
 901         OPAL_SYSPOWER_FAIL      = 0x0004, /* System impending power failure */
 902         OPAL_SYSPOWER_INCL      = 0x0008, /* System incomplete power */
 903 };
 904
 905 /* Temperature EPOW */
 906 enum OpalSysTemp {
 907         OPAL_SYSTEMP_AMB        = 0x0001, /* System over ambient temperature */
 908         OPAL_SYSTEMP_INT        = 0x0002, /* System over internal temperature */
 909         OPAL_SYSTEMP_HMD        = 0x0004, /* System over ambient humidity */
 910 };
 911
 912 /* Cooling EPOW */
 913 enum OpalSysCooling {
 914         OPAL_SYSCOOL_INSF       = 0x0001, /* System insufficient cooling */
 915 };
 916
 917 /* Argument to OPAL_CEC_REBOOT2() */
 918 enum {
 919         OPAL_REBOOT_NORMAL              = 0,
 920         OPAL_REBOOT_PLATFORM_ERROR      = 1,
 921 };
 922
 923 /* Argument to OPAL_PCI_TCE_KILL */
 924 enum {
 925         OPAL_PCI_TCE_KILL_PAGES,
 926         OPAL_PCI_TCE_KILL_PE,
 927         OPAL_PCI_TCE_KILL_ALL,
 928 };
 929
 930 #endif /* __ASSEMBLY__ */
 931
 932 #endif /* __OPAL_API_H */