arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 #ifndef __ASSEMBLY__
  16 /*
  17  * SG entry
  18  *
  19  * WARNING: The current implementation requires each entry
  20  * to represent a block that is 4k aligned *and* each block
  21  * size except the last one in the list to be as well.
  22  */
  23 struct opal_sg_entry {
  24         __be64 data;
  25         __be64 length;
  26 };
  27
  28 /* SG list */
  29 struct opal_sg_list {
  30         __be64 length;
  31         __be64 next;
  32         struct opal_sg_entry entry[];
  33 };
  34
  35 /* We calculate number of sg entries based on PAGE_SIZE */
  36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  37
  38 #endif /* __ASSEMBLY__ */
  39
  40 /****** OPAL APIs ******/
  41
  42 /* Return codes */
  43 #define OPAL_SUCCESS            0
  44 #define OPAL_PARAMETER          -1
  45 #define OPAL_BUSY               -2
  46 #define OPAL_PARTIAL            -3
  47 #define OPAL_CONSTRAINED        -4
  48 #define OPAL_CLOSED             -5
  49 #define OPAL_HARDWARE           -6
  50 #define OPAL_UNSUPPORTED        -7
  51 #define OPAL_PERMISSION         -8
  52 #define OPAL_NO_MEM             -9
  53 #define OPAL_RESOURCE           -10
  54 #define OPAL_INTERNAL_ERROR     -11
  55 #define OPAL_BUSY_EVENT         -12
  56 #define OPAL_HARDWARE_FROZEN    -13
  57 #define OPAL_WRONG_STATE        -14
  58 #define OPAL_ASYNC_COMPLETION   -15
  59
  60 /* API Tokens (in r0) */
  61 #define OPAL_INVALID_CALL                       -1
  62 #define OPAL_CONSOLE_WRITE                      1
  63 #define OPAL_CONSOLE_READ                       2
  64 #define OPAL_RTC_READ                           3
  65 #define OPAL_RTC_WRITE                          4
  66 #define OPAL_CEC_POWER_DOWN                     5
  67 #define OPAL_CEC_REBOOT                         6
  68 #define OPAL_READ_NVRAM                         7
  69 #define OPAL_WRITE_NVRAM                        8
  70 #define OPAL_HANDLE_INTERRUPT                   9
  71 #define OPAL_POLL_EVENTS                        10
  72 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  73 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  74 #define OPAL_PCI_CONFIG_READ_BYTE               13
  75 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  76 #define OPAL_PCI_CONFIG_READ_WORD               15
  77 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  79 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  80 #define OPAL_SET_XIVE                           19
  81 #define OPAL_GET_XIVE                           20
  82 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  84 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  85 #define OPAL_PCI_SHPC                           24
  86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  87 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  88 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  89 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  92 #define OPAL_PCI_SET_PE                         31
  93 #define OPAL_PCI_SET_PELTV                      32
  94 #define OPAL_PCI_SET_MVE                        33
  95 #define OPAL_PCI_SET_MVE_ENABLE                 34
  96 #define OPAL_PCI_GET_XIVE_REISSUE               35
  97 #define OPAL_PCI_SET_XIVE_REISSUE               36
  98 #define OPAL_PCI_SET_XIVE_PE                    37
  99 #define OPAL_GET_XIVE_SOURCE                    38
 100 #define OPAL_GET_MSI_32                         39
 101 #define OPAL_GET_MSI_64                         40
 102 #define OPAL_START_CPU                          41
 103 #define OPAL_QUERY_CPU_STATUS                   42
 104 #define OPAL_WRITE_OPPANEL                      43
 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 107 #define OPAL_PCI_RESET                          49
 108 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 109 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 110 #define OPAL_PCI_FENCE_PHB                      52
 111 #define OPAL_PCI_REINIT                         53
 112 #define OPAL_PCI_MASK_PE_ERROR                  54
 113 #define OPAL_SET_SLOT_LED_STATUS                55
 114 #define OPAL_GET_EPOW_STATUS                    56
 115 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 116 #define OPAL_RESERVED1                          58
 117 #define OPAL_RESERVED2                          59
 118 #define OPAL_PCI_NEXT_ERROR                     60
 119 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 120 #define OPAL_PCI_POLL                           62
 121 #define OPAL_PCI_MSI_EOI                        63
 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 123 #define OPAL_XSCOM_READ                         65
 124 #define OPAL_XSCOM_WRITE                        66
 125 #define OPAL_LPC_READ                           67
 126 #define OPAL_LPC_WRITE                          68
 127 #define OPAL_RETURN_CPU                         69
 128 #define OPAL_REINIT_CPUS                        70
 129 #define OPAL_ELOG_READ                          71
 130 #define OPAL_ELOG_WRITE                         72
 131 #define OPAL_ELOG_ACK                           73
 132 #define OPAL_ELOG_RESEND                        74
 133 #define OPAL_ELOG_SIZE                          75
 134 #define OPAL_FLASH_VALIDATE                     76
 135 #define OPAL_FLASH_MANAGE                       77
 136 #define OPAL_FLASH_UPDATE                       78
 137 #define OPAL_RESYNC_TIMEBASE                    79
 138 #define OPAL_CHECK_TOKEN                        80
 139 #define OPAL_DUMP_INIT                          81
 140 #define OPAL_DUMP_INFO                          82
 141 #define OPAL_DUMP_READ                          83
 142 #define OPAL_DUMP_ACK                           84
 143 #define OPAL_GET_MSG                            85
 144 #define OPAL_CHECK_ASYNC_COMPLETION             86
 145 #define OPAL_SYNC_HOST_REBOOT                   87
 146 #define OPAL_SENSOR_READ                        88
 147 #define OPAL_GET_PARAM                          89
 148 #define OPAL_SET_PARAM                          90
 149 #define OPAL_DUMP_RESEND                        91
 150 #define OPAL_PCI_SET_PHB_CXL_MODE               93
 151 #define OPAL_DUMP_INFO2                         94
 152 #define OPAL_PCI_ERR_INJECT                     96
 153 #define OPAL_PCI_EEH_FREEZE_SET                 97
 154 #define OPAL_HANDLE_HMI                         98
 155 #define OPAL_REGISTER_DUMP_REGION               101
 156 #define OPAL_UNREGISTER_DUMP_REGION             102
 157 #define OPAL_WRITE_TPO                          103
 158 #define OPAL_READ_TPO                           104
 159 #define OPAL_IPMI_SEND                          107
 160 #define OPAL_IPMI_RECV                          108
 161
 162 #ifndef __ASSEMBLY__
 163
 164 #include <linux/notifier.h>
 165
 166 /* Other enums */
 167 enum OpalVendorApiTokens {
 168         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 169 };
 170
 171 enum OpalFreezeState {
 172         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 173         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 174         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 175         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 176         OPAL_EEH_STOPPED_RESET = 4,
 177         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 178         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 179 };
 180
 181 enum OpalEehFreezeActionToken {
 182         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 183         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 184         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 185
 186         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 187         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 188         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 189 };
 190
 191 enum OpalPciStatusToken {
 192         OPAL_EEH_NO_ERROR       = 0,
 193         OPAL_EEH_IOC_ERROR      = 1,
 194         OPAL_EEH_PHB_ERROR      = 2,
 195         OPAL_EEH_PE_ERROR       = 3,
 196         OPAL_EEH_PE_MMIO_ERROR  = 4,
 197         OPAL_EEH_PE_DMA_ERROR   = 5
 198 };
 199
 200 enum OpalPciErrorSeverity {
 201         OPAL_EEH_SEV_NO_ERROR   = 0,
 202         OPAL_EEH_SEV_IOC_DEAD   = 1,
 203         OPAL_EEH_SEV_PHB_DEAD   = 2,
 204         OPAL_EEH_SEV_PHB_FENCED = 3,
 205         OPAL_EEH_SEV_PE_ER      = 4,
 206         OPAL_EEH_SEV_INF        = 5
 207 };
 208
 209 enum OpalErrinjectType {
 210         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 211         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 212 };
 213
 214 enum OpalErrinjectFunc {
 215         /* IOA bus specific errors */
 216         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 217         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 218         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 219         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 220         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 221         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 222         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 223         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 224         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 225         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 226         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 227         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 228         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 229         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 230         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 231         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 232         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 233         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 234         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 235         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 236 };
 237
 238 enum OpalShpcAction {
 239         OPAL_SHPC_GET_LINK_STATE = 0,
 240         OPAL_SHPC_GET_SLOT_STATE = 1
 241 };
 242
 243 enum OpalShpcLinkState {
 244         OPAL_SHPC_LINK_DOWN = 0,
 245         OPAL_SHPC_LINK_UP = 1
 246 };
 247
 248 enum OpalMmioWindowType {
 249         OPAL_M32_WINDOW_TYPE = 1,
 250         OPAL_M64_WINDOW_TYPE = 2,
 251         OPAL_IO_WINDOW_TYPE = 3
 252 };
 253
 254 enum OpalShpcSlotState {
 255         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 256         OPAL_SHPC_DEV_PRESENT = 1
 257 };
 258
 259 enum OpalExceptionHandler {
 260         OPAL_MACHINE_CHECK_HANDLER = 1,
 261         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 262         OPAL_SOFTPATCH_HANDLER = 3
 263 };
 264
 265 enum OpalPendingState {
 266         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 267         OPAL_EVENT_NVRAM                = 0x2,
 268         OPAL_EVENT_RTC                  = 0x4,
 269         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 270         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 271         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 272         OPAL_EVENT_ERROR_LOG            = 0x40,
 273         OPAL_EVENT_EPOW                 = 0x80,
 274         OPAL_EVENT_LED_STATUS           = 0x100,
 275         OPAL_EVENT_PCI_ERROR            = 0x200,
 276         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 277         OPAL_EVENT_MSG_PENDING          = 0x800,
 278 };
 279
 280 enum OpalMessageType {
 281         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 282                                          * additional params function-specific
 283                                          */
 284         OPAL_MSG_MEM_ERR,
 285         OPAL_MSG_EPOW,
 286         OPAL_MSG_SHUTDOWN,
 287         OPAL_MSG_HMI_EVT,
 288         OPAL_MSG_TYPE_MAX,
 289 };
 290
 291 enum OpalThreadStatus {
 292         OPAL_THREAD_INACTIVE = 0x0,
 293         OPAL_THREAD_STARTED = 0x1,
 294         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 295 };
 296
 297 enum OpalPciBusCompare {
 298         OpalPciBusAny   = 0,    /* Any bus number match */
 299         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 300         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 301         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 302         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 303         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 304         OpalPciBusAll   = 7,    /* Match bus number exactly */
 305 };
 306
 307 enum OpalDeviceCompare {
 308         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 309         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 310 };
 311
 312 enum OpalFuncCompare {
 313         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 314         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 315 };
 316
 317 enum OpalPeAction {
 318         OPAL_UNMAP_PE = 0,
 319         OPAL_MAP_PE = 1
 320 };
 321
 322 enum OpalPeltvAction {
 323         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 324         OPAL_ADD_PE_TO_DOMAIN = 1
 325 };
 326
 327 enum OpalMveEnableAction {
 328         OPAL_DISABLE_MVE = 0,
 329         OPAL_ENABLE_MVE = 1
 330 };
 331
 332 enum OpalM64EnableAction {
 333         OPAL_DISABLE_M64 = 0,
 334         OPAL_ENABLE_M64_SPLIT = 1,
 335         OPAL_ENABLE_M64_NON_SPLIT = 2
 336 };
 337
 338 enum OpalPciResetScope {
 339         OPAL_RESET_PHB_COMPLETE         = 1,
 340         OPAL_RESET_PCI_LINK             = 2,
 341         OPAL_RESET_PHB_ERROR            = 3,
 342         OPAL_RESET_PCI_HOT              = 4,
 343         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 344         OPAL_RESET_PCI_IODA_TABLE       = 6
 345 };
 346
 347 enum OpalPciReinitScope {
 348         OPAL_REINIT_PCI_DEV = 1000
 349 };
 350
 351 enum OpalPciResetState {
 352         OPAL_DEASSERT_RESET = 0,
 353         OPAL_ASSERT_RESET = 1
 354 };
 355
 356 enum OpalPciMaskAction {
 357         OPAL_UNMASK_ERROR_TYPE = 0,
 358         OPAL_MASK_ERROR_TYPE = 1
 359 };
 360
 361 enum OpalSlotLedType {
 362         OPAL_SLOT_LED_ID_TYPE = 0,
 363         OPAL_SLOT_LED_FAULT_TYPE = 1
 364 };
 365
 366 enum OpalLedAction {
 367         OPAL_TURN_OFF_LED = 0,
 368         OPAL_TURN_ON_LED = 1,
 369         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 370 };
 371
 372 enum OpalEpowStatus {
 373         OPAL_EPOW_NONE = 0,
 374         OPAL_EPOW_UPS = 1,
 375         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 376         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 377 };
 378
 379 /*
 380  * Address cycle types for LPC accesses. These also correspond
 381  * to the content of the first cell of the "reg" property for
 382  * device nodes on the LPC bus
 383  */
 384 enum OpalLPCAddressType {
 385         OPAL_LPC_MEM    = 0,
 386         OPAL_LPC_IO     = 1,
 387         OPAL_LPC_FW     = 2,
 388 };
 389
 390 /* System parameter permission */
 391 enum OpalSysparamPerm {
 392         OPAL_SYSPARAM_READ      = 0x1,
 393         OPAL_SYSPARAM_WRITE     = 0x2,
 394         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 395 };
 396
 397 struct opal_msg {
 398         __be32 msg_type;
 399         __be32 reserved;
 400         __be64 params[8];
 401 };
 402
 403 enum {
 404         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 405 };
 406
 407 struct opal_ipmi_msg {
 408         uint8_t         version;
 409         uint8_t         netfn;
 410         uint8_t         cmd;
 411         uint8_t         data[];
 412 };
 413
 414 /* FSP memory errors handling */
 415 enum OpalMemErr_Version {
 416         OpalMemErr_V1 = 1,
 417 };
 418
 419 enum OpalMemErrType {
 420         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 421         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 422         OPAL_MEM_ERR_TYPE_SCRUB,
 423 };
 424
 425 /* Memory Reilience error type */
 426 enum OpalMemErr_ResilErrType {
 427         OPAL_MEM_RESILIENCE_CE          = 0,
 428         OPAL_MEM_RESILIENCE_UE,
 429         OPAL_MEM_RESILIENCE_UE_SCRUB,
 430 };
 431
 432 /* Dynamic Memory Deallocation type */
 433 enum OpalMemErr_DynErrType {
 434         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 435 };
 436
 437 /* OpalMemoryErrorData->flags */
 438 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 439 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 440 #define OPAL_MEM_ACK_REQUIRED           0x8000
 441
 442 struct OpalMemoryErrorData {
 443         enum OpalMemErr_Version version:8;      /* 0x00 */
 444         enum OpalMemErrType     type:8;         /* 0x01 */
 445         __be16                  flags;          /* 0x02 */
 446         uint8_t                 reserved_1[4];  /* 0x04 */
 447
 448         union {
 449                 /* Memory Resilience corrected/uncorrected error info */
 450                 struct {
 451                         enum OpalMemErr_ResilErrType resil_err_type:8;
 452                         uint8_t         reserved_1[7];
 453                         __be64          physical_address_start;
 454                         __be64          physical_address_end;
 455                 } resilience;
 456                 /* Dynamic memory deallocation error info */
 457                 struct {
 458                         enum OpalMemErr_DynErrType dyn_err_type:8;
 459                         uint8_t         reserved_1[7];
 460                         __be64          physical_address_start;
 461                         __be64          physical_address_end;
 462                 } dyn_dealloc;
 463         } u;
 464 };
 465
 466 /* HMI interrupt event */
 467 enum OpalHMI_Version {
 468         OpalHMIEvt_V1 = 1,
 469 };
 470
 471 enum OpalHMI_Severity {
 472         OpalHMI_SEV_NO_ERROR = 0,
 473         OpalHMI_SEV_WARNING = 1,
 474         OpalHMI_SEV_ERROR_SYNC = 2,
 475         OpalHMI_SEV_FATAL = 3,
 476 };
 477
 478 enum OpalHMI_Disposition {
 479         OpalHMI_DISPOSITION_RECOVERED = 0,
 480         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 481 };
 482
 483 enum OpalHMI_ErrType {
 484         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 485         OpalHMI_ERROR_PROC_RECOV_DONE,
 486         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 487         OpalHMI_ERROR_PROC_RECOV_MASKED,
 488         OpalHMI_ERROR_TFAC,
 489         OpalHMI_ERROR_TFMR_PARITY,
 490         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 491         OpalHMI_ERROR_XSCOM_FAIL,
 492         OpalHMI_ERROR_XSCOM_DONE,
 493         OpalHMI_ERROR_SCOM_FIR,
 494         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 495         OpalHMI_ERROR_HYP_RESOURCE,
 496 };
 497
 498 struct OpalHMIEvent {
 499         uint8_t         version;        /* 0x00 */
 500         uint8_t         severity;       /* 0x01 */
 501         uint8_t         type;           /* 0x02 */
 502         uint8_t         disposition;    /* 0x03 */
 503         uint8_t         reserved_1[4];  /* 0x04 */
 504
 505         __be64          hmer;
 506         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 507         __be64          tfmr;
 508 };
 509
 510 enum {
 511         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 512         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 513         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 514         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 515         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 516         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 517         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 518 };
 519
 520 struct OpalIoP7IOCErrorData {
 521         __be16 type;
 522
 523         /* GEM */
 524         __be64 gemXfir;
 525         __be64 gemRfir;
 526         __be64 gemRirqfir;
 527         __be64 gemMask;
 528         __be64 gemRwof;
 529
 530         /* LEM */
 531         __be64 lemFir;
 532         __be64 lemErrMask;
 533         __be64 lemAction0;
 534         __be64 lemAction1;
 535         __be64 lemWof;
 536
 537         union {
 538                 struct OpalIoP7IOCRgcErrorData {
 539                         __be64 rgcStatus;       /* 3E1C10 */
 540                         __be64 rgcLdcp;         /* 3E1C18 */
 541                 }rgc;
 542                 struct OpalIoP7IOCBiErrorData {
 543                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 544                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 545                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 546                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 547
 548                             u8 biDownbound;     /* BI Downbound or Upbound */
 549                 }bi;
 550                 struct OpalIoP7IOCCiErrorData {
 551                         __be64 ciPortStatus;    /* 3Dn008 */
 552                         __be64 ciPortLdcp;      /* 3Dn010 */
 553
 554                             u8 ciPort;          /* Index of CI port: 0/1 */
 555                 }ci;
 556         };
 557 };
 558
 559 /**
 560  * This structure defines the overlay which will be used to store PHB error
 561  * data upon request.
 562  */
 563 enum {
 564         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 565 };
 566
 567 enum {
 568         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 569         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 570 };
 571
 572 enum {
 573         OPAL_P7IOC_NUM_PEST_REGS = 128,
 574         OPAL_PHB3_NUM_PEST_REGS = 256
 575 };
 576
 577 struct OpalIoPhbErrorCommon {
 578         __be32 version;
 579         __be32 ioType;
 580         __be32 len;
 581 };
 582
 583 struct OpalIoP7IOCPhbErrorData {
 584         struct OpalIoPhbErrorCommon common;
 585
 586         __be32 brdgCtl;
 587
 588         // P7IOC utl regs
 589         __be32 portStatusReg;
 590         __be32 rootCmplxStatus;
 591         __be32 busAgentStatus;
 592
 593         // P7IOC cfg regs
 594         __be32 deviceStatus;
 595         __be32 slotStatus;
 596         __be32 linkStatus;
 597         __be32 devCmdStatus;
 598         __be32 devSecStatus;
 599
 600         // cfg AER regs
 601         __be32 rootErrorStatus;
 602         __be32 uncorrErrorStatus;
 603         __be32 corrErrorStatus;
 604         __be32 tlpHdr1;
 605         __be32 tlpHdr2;
 606         __be32 tlpHdr3;
 607         __be32 tlpHdr4;
 608         __be32 sourceId;
 609
 610         __be32 rsv3;
 611
 612         // Record data about the call to allocate a buffer.
 613         __be64 errorClass;
 614         __be64 correlator;
 615
 616         //P7IOC MMIO Error Regs
 617         __be64 p7iocPlssr;                // n120
 618         __be64 p7iocCsr;                  // n110
 619         __be64 lemFir;                    // nC00
 620         __be64 lemErrorMask;              // nC18
 621         __be64 lemWOF;                    // nC40
 622         __be64 phbErrorStatus;            // nC80
 623         __be64 phbFirstErrorStatus;       // nC88
 624         __be64 phbErrorLog0;              // nCC0
 625         __be64 phbErrorLog1;              // nCC8
 626         __be64 mmioErrorStatus;           // nD00
 627         __be64 mmioFirstErrorStatus;      // nD08
 628         __be64 mmioErrorLog0;             // nD40
 629         __be64 mmioErrorLog1;             // nD48
 630         __be64 dma0ErrorStatus;           // nD80
 631         __be64 dma0FirstErrorStatus;      // nD88
 632         __be64 dma0ErrorLog0;             // nDC0
 633         __be64 dma0ErrorLog1;             // nDC8
 634         __be64 dma1ErrorStatus;           // nE00
 635         __be64 dma1FirstErrorStatus;      // nE08
 636         __be64 dma1ErrorLog0;             // nE40
 637         __be64 dma1ErrorLog1;             // nE48
 638         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 639         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 640 };
 641
 642 struct OpalIoPhb3ErrorData {
 643         struct OpalIoPhbErrorCommon common;
 644
 645         __be32 brdgCtl;
 646
 647         /* PHB3 UTL regs */
 648         __be32 portStatusReg;
 649         __be32 rootCmplxStatus;
 650         __be32 busAgentStatus;
 651
 652         /* PHB3 cfg regs */
 653         __be32 deviceStatus;
 654         __be32 slotStatus;
 655         __be32 linkStatus;
 656         __be32 devCmdStatus;
 657         __be32 devSecStatus;
 658
 659         /* cfg AER regs */
 660         __be32 rootErrorStatus;
 661         __be32 uncorrErrorStatus;
 662         __be32 corrErrorStatus;
 663         __be32 tlpHdr1;
 664         __be32 tlpHdr2;
 665         __be32 tlpHdr3;
 666         __be32 tlpHdr4;
 667         __be32 sourceId;
 668
 669         __be32 rsv3;
 670
 671         /* Record data about the call to allocate a buffer */
 672         __be64 errorClass;
 673         __be64 correlator;
 674
 675         __be64 nFir;                    /* 000 */
 676         __be64 nFirMask;                /* 003 */
 677         __be64 nFirWOF;         /* 008 */
 678
 679         /* PHB3 MMIO Error Regs */
 680         __be64 phbPlssr;                /* 120 */
 681         __be64 phbCsr;          /* 110 */
 682         __be64 lemFir;          /* C00 */
 683         __be64 lemErrorMask;            /* C18 */
 684         __be64 lemWOF;          /* C40 */
 685         __be64 phbErrorStatus;  /* C80 */
 686         __be64 phbFirstErrorStatus;     /* C88 */
 687         __be64 phbErrorLog0;            /* CC0 */
 688         __be64 phbErrorLog1;            /* CC8 */
 689         __be64 mmioErrorStatus; /* D00 */
 690         __be64 mmioFirstErrorStatus;    /* D08 */
 691         __be64 mmioErrorLog0;           /* D40 */
 692         __be64 mmioErrorLog1;           /* D48 */
 693         __be64 dma0ErrorStatus; /* D80 */
 694         __be64 dma0FirstErrorStatus;    /* D88 */
 695         __be64 dma0ErrorLog0;           /* DC0 */
 696         __be64 dma0ErrorLog1;           /* DC8 */
 697         __be64 dma1ErrorStatus; /* E00 */
 698         __be64 dma1FirstErrorStatus;    /* E08 */
 699         __be64 dma1ErrorLog0;           /* E40 */
 700         __be64 dma1ErrorLog1;           /* E48 */
 701         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 702         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 703 };
 704
 705 enum {
 706         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 707         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 708 };
 709
 710 typedef struct oppanel_line {
 711         const char *    line;
 712         uint64_t        line_len;
 713 } oppanel_line_t;
 714
 715 /* /sys/firmware/opal */
 716 extern struct kobject *opal_kobj;
 717
 718 /* /ibm,opal */
 719 extern struct device_node *opal_node;
 720
 721 /* API functions */
 722 int64_t opal_invalid_call(void);
 723 int64_t opal_console_write(int64_t term_number, __be64 *length,
 724                            const uint8_t *buffer);
 725 int64_t opal_console_read(int64_t term_number, __be64 *length,
 726                           uint8_t *buffer);
 727 int64_t opal_console_write_buffer_space(int64_t term_number,
 728                                         __be64 *length);
 729 int64_t opal_rtc_read(__be32 *year_month_day,
 730                       __be64 *hour_minute_second_millisecond);
 731 int64_t opal_rtc_write(uint32_t year_month_day,
 732                        uint64_t hour_minute_second_millisecond);
 733 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
 734 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
 735                        uint32_t hour_min);
 736 int64_t opal_cec_power_down(uint64_t request);
 737 int64_t opal_cec_reboot(void);
 738 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 739 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 740 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 741 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 742 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 743                                     uint64_t tce_mem_size);
 744 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 745                                     uint64_t tce_mem_size);
 746 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 747                                   uint64_t offset, uint8_t *data);
 748 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 749                                        uint64_t offset, __be16 *data);
 750 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 751                                   uint64_t offset, __be32 *data);
 752 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 753                                    uint64_t offset, uint8_t data);
 754 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 755                                         uint64_t offset, uint16_t data);
 756 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 757                                    uint64_t offset, uint32_t data);
 758 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 759 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 760 int64_t opal_register_exception_handler(uint64_t opal_exception,
 761                                         uint64_t handler_address,
 762                                         uint64_t glue_cache_line);
 763 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 764                                    uint8_t *freeze_state,
 765                                    __be16 *pci_error_type,
 766                                    __be64 *phb_status);
 767 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 768                                   uint64_t eeh_action_token);
 769 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
 770                                 uint64_t eeh_action_token);
 771 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
 772                             uint32_t func, uint64_t addr, uint64_t mask);
 773 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 774
 775
 776
 777 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 778                                  uint16_t window_num, uint16_t enable);
 779 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 780                                     uint16_t window_num,
 781                                     uint64_t starting_real_address,
 782                                     uint64_t starting_pci_address,
 783                                     uint64_t size);
 784 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 785                                     uint16_t window_type, uint16_t window_num,
 786                                     uint16_t segment_num);
 787 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 788                                       uint64_t ivt_addr, uint64_t ivt_len,
 789                                       uint64_t reject_array_addr,
 790                                       uint64_t peltv_addr);
 791 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 792                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 793                         uint8_t pe_action);
 794 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 795                            uint8_t state);
 796 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 797 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 798                                 uint32_t state);
 799 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 800                                   uint8_t *p_bit, uint8_t *q_bit);
 801 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 802                                   uint8_t p_bit, uint8_t q_bit);
 803 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 804 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 805                              uint32_t xive_num);
 806 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 807                              __be32 *interrupt_source_number);
 808 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 809                         uint8_t msi_range, __be32 *msi_address,
 810                         __be32 *message_data);
 811 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 812                         uint32_t xive_num, uint8_t msi_range,
 813                         __be64 *msi_address, __be32 *message_data);
 814 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 815 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 816 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 817 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 818                                    uint16_t tce_levels, uint64_t tce_table_addr,
 819                                    uint64_t tce_table_size, uint64_t tce_page_size);
 820 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 821                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 822                                         uint64_t pci_mem_size);
 823 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 824
 825 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 826                                    uint64_t diag_buffer_len);
 827 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 828                                    uint64_t diag_buffer_len);
 829 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 830                                     uint64_t diag_buffer_len);
 831 int64_t opal_pci_fence_phb(uint64_t phb_id);
 832 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 833 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 834 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 835 int64_t opal_get_epow_status(__be64 *status);
 836 int64_t opal_set_system_attention_led(uint8_t led_action);
 837 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 838                             __be16 *pci_error_type, __be16 *severity);
 839 int64_t opal_pci_poll(uint64_t phb_id);
 840 int64_t opal_return_cpu(void);
 841 int64_t opal_check_token(uint64_t token);
 842 int64_t opal_reinit_cpus(uint64_t flags);
 843
 844 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 845 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 846
 847 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 848                        uint32_t addr, uint32_t data, uint32_t sz);
 849 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 850                       uint32_t addr, __be32 *data, uint32_t sz);
 851
 852 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
 853 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
 854 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 855 int64_t opal_send_ack_elog(uint64_t log_id);
 856 void opal_resend_pending_logs(void);
 857
 858 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 859 int64_t opal_manage_flash(uint8_t op);
 860 int64_t opal_update_flash(uint64_t blk_list);
 861 int64_t opal_dump_init(uint8_t dump_type);
 862 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
 863 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
 864 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 865 int64_t opal_dump_ack(uint32_t dump_id);
 866 int64_t opal_dump_resend_notification(void);
 867
 868 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
 869 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
 870 int64_t opal_sync_host_reboot(void);
 871 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 872                 uint64_t length);
 873 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 874                 uint64_t length);
 875 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 876 int64_t opal_handle_hmi(void);
 877 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 878 int64_t opal_unregister_dump_region(uint32_t id);
 879 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
 880 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
 881                 uint64_t msg_len);
 882 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
 883                 uint64_t *msg_len);
 884
 885 /* Internal functions */
 886 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 887                                    int depth, void *data);
 888 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 889                                  const char *uname, int depth, void *data);
 890
 891 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 892 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 893
 894 extern void hvc_opal_init_early(void);
 895
 896 extern int opal_notifier_register(struct notifier_block *nb);
 897 extern int opal_notifier_unregister(struct notifier_block *nb);
 898
 899 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 900                                                 struct notifier_block *nb);
 901 extern void opal_notifier_enable(void);
 902 extern void opal_notifier_disable(void);
 903 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 904
 905 extern int __opal_async_get_token(void);
 906 extern int opal_async_get_token_interruptible(void);
 907 extern int __opal_async_release_token(int token);
 908 extern int opal_async_release_token(int token);
 909 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 910 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 911
 912 struct rtc_time;
 913 extern unsigned long opal_get_boot_time(void);
 914 extern void opal_nvram_init(void);
 915 extern void opal_flash_init(void);
 916 extern void opal_flash_term_callback(void);
 917 extern int opal_elog_init(void);
 918 extern void opal_platform_dump_init(void);
 919 extern void opal_sys_param_init(void);
 920 extern void opal_msglog_init(void);
 921
 922 extern int opal_machine_check(struct pt_regs *regs);
 923 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 924 extern int opal_hmi_exception_early(struct pt_regs *regs);
 925 extern int opal_handle_hmi_exception(struct pt_regs *regs);
 926
 927 extern void opal_shutdown(void);
 928 extern int opal_resync_timebase(void);
 929
 930 extern void opal_lpc_init(void);
 931
 932 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
 933                                              unsigned long vmalloc_size);
 934 void opal_free_sg_list(struct opal_sg_list *sg);
 935
 936 /*
 937  * Dump region ID range usable by the OS
 938  */
 939 #define OPAL_DUMP_REGION_HOST_START             0x80
 940 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 941 #define OPAL_DUMP_REGION_HOST_END               0xFF
 942
 943 #endif /* __ASSEMBLY__ */
 944
 945 #endif /* __OPAL_H */