3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ftrace.h>
35 #include <asm/ptrace.h>
38 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
40 #if MSR_KERNEL >= 0x10000
41 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
43 #define LOAD_MSR_KERNEL(r, x) li r,(x)
47 .globl mcheck_transfer_to_handler
48 mcheck_transfer_to_handler:
55 .globl debug_transfer_to_handler
56 debug_transfer_to_handler:
63 .globl crit_transfer_to_handler
64 crit_transfer_to_handler:
65 #ifdef CONFIG_PPC_BOOK3E_MMU
76 #ifdef CONFIG_PHYS_64BIT
79 #endif /* CONFIG_PHYS_64BIT */
80 #endif /* CONFIG_PPC_BOOK3E_MMU */
90 /* set the stack limit to the current stack
91 * and set the limit to protect the thread_info
94 mfspr r8,SPRN_SPRG_THREAD
96 stw r0,SAVED_KSP_LIMIT(r11)
97 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
103 .globl crit_transfer_to_handler
104 crit_transfer_to_handler:
110 stw r0,crit_srr0@l(0)
112 stw r0,crit_srr1@l(0)
114 /* set the stack limit to the current stack
115 * and set the limit to protect the thread_info
118 mfspr r8,SPRN_SPRG_THREAD
120 stw r0,saved_ksp_limit@l(0)
121 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
127 * This code finishes saving the registers to the exception frame
128 * and jumps to the appropriate handler for the exception, turning
129 * on address translation.
130 * Note that we rely on the caller having set cr0.eq iff the exception
131 * occurred in kernel mode (i.e. MSR:PR = 0).
133 .globl transfer_to_handler_full
134 transfer_to_handler_full:
138 .globl transfer_to_handler
148 mfspr r12,SPRN_SPRG_THREAD
150 tovirt(r2,r2) /* set r2 to current */
151 beq 2f /* if from user, fix up THREAD.regs */
152 addi r11,r1,STACK_FRAME_OVERHEAD
154 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
155 /* Check to see if the dbcr0 register is set up to debug. Use the
156 internal debug mode bit to do this. */
157 lwz r12,THREAD_DBCR0(r12)
158 andis. r12,r12,DBCR0_IDM@h
160 /* From user and task is ptraced - load up global dbcr0 */
161 li r12,-1 /* clear all pending debug events */
163 lis r11,global_dbcr0@ha
165 addi r11,r11,global_dbcr0@l
167 CURRENT_THREAD_INFO(r9, r1)
178 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
179 CURRENT_THREAD_INFO(r9, r1)
181 ACCOUNT_CPU_USER_ENTRY(r9, r11, r12)
186 2: /* if from kernel, check interrupted DOZE/NAP mode and
187 * check for stack overflow
189 lwz r9,KSP_LIMIT(r12)
190 cmplw r1,r9 /* if r1 <= ksp_limit */
191 ble- stack_ovf /* then the kernel stack overflowed */
193 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
194 CURRENT_THREAD_INFO(r9, r1)
195 tophys(r9,r9) /* check local flags */
196 lwz r12,TI_LOCAL_FLAGS(r9)
198 bt- 31-TLF_NAPPING,4f
199 bt- 31-TLF_SLEEPING,7f
200 #endif /* CONFIG_6xx || CONFIG_E500 */
201 .globl transfer_to_handler_cont
202 transfer_to_handler_cont:
205 lwz r11,0(r9) /* virtual address of handler */
206 lwz r9,4(r9) /* where to go when done */
207 #ifdef CONFIG_TRACE_IRQFLAGS
208 lis r12,reenable_mmu@h
209 ori r12,r12,reenable_mmu@l
214 reenable_mmu: /* re-enable mmu so we can */
218 andi. r10,r10,MSR_EE /* Did EE change? */
222 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
223 * If from user mode there is only one stack frame on the stack, and
224 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
225 * stack frame to make trace_hardirqs_off happy.
227 * This is handy because we also need to save a bunch of GPRs,
228 * r3 can be different from GPR3(r1) at this point, r9 and r11
229 * contains the old MSR and handler address respectively,
230 * r4 & r5 can contain page fault arguments that need to be passed
231 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
232 * they aren't useful past this point (aren't syscall arguments),
233 * the rest is restored from the exception frame.
241 bl trace_hardirqs_off
254 bctr /* jump to handler */
255 #else /* CONFIG_TRACE_IRQFLAGS */
260 RFI /* jump to handler, enable MMU */
261 #endif /* CONFIG_TRACE_IRQFLAGS */
263 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
264 4: rlwinm r12,r12,0,~_TLF_NAPPING
265 stw r12,TI_LOCAL_FLAGS(r9)
266 b power_save_ppc32_restore
268 7: rlwinm r12,r12,0,~_TLF_SLEEPING
269 stw r12,TI_LOCAL_FLAGS(r9)
270 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
271 rlwinm r9,r9,0,~MSR_EE
272 lwz r12,_LINK(r11) /* and return to address in LR */
273 b fast_exception_return
277 * On kernel stack overflow, load up an initial stack pointer
278 * and call StackOverflow(regs), which should not return.
281 /* sometimes we use a statically-allocated stack, which is OK. */
285 ble 5b /* r1 <= &_end is OK */
287 addi r3,r1,STACK_FRAME_OVERHEAD
288 lis r1,init_thread_union@ha
289 addi r1,r1,init_thread_union@l
290 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
291 lis r9,StackOverflow@ha
292 addi r9,r9,StackOverflow@l
293 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
301 * Handle a system call.
303 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
304 .stabs "entry_32.S",N_SO,0,0,0f
311 lwz r11,_CCR(r1) /* Clear SO bit in CR */
314 #ifdef CONFIG_TRACE_IRQFLAGS
315 /* Return from syscalls can (and generally will) hard enable
316 * interrupts. You aren't supposed to call a syscall with
317 * interrupts disabled in the first place. However, to ensure
318 * that we get it right vs. lockdep if it happens, we force
319 * that hard enable here with appropriate tracing if we see
320 * that we have been called with interrupts off
325 /* We came in with interrupts disabled, we enable them now */
338 #endif /* CONFIG_TRACE_IRQFLAGS */
339 CURRENT_THREAD_INFO(r10, r1)
340 lwz r11,TI_FLAGS(r10)
341 andi. r11,r11,_TIF_SYSCALL_DOTRACE
343 syscall_dotrace_cont:
344 cmplwi 0,r0,NR_syscalls
345 lis r10,sys_call_table@h
346 ori r10,r10,sys_call_table@l
349 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
351 addi r9,r1,STACK_FRAME_OVERHEAD
353 blrl /* Call handler */
354 .globl ret_from_syscall
357 CURRENT_THREAD_INFO(r12, r1)
358 /* disable interrupts so current_thread_info()->flags can't change */
359 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
360 /* Note: We don't bother telling lockdep about it */
365 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
366 bne- syscall_exit_work
368 blt+ syscall_exit_cont
369 lwz r11,_CCR(r1) /* Load CR */
371 oris r11,r11,0x1000 /* Set SO bit in CR */
375 #ifdef CONFIG_TRACE_IRQFLAGS
376 /* If we are going to return from the syscall with interrupts
377 * off, we trace that here. It shouldn't happen though but we
378 * want to catch the bugger if it does right ?
383 bl trace_hardirqs_off
386 #endif /* CONFIG_TRACE_IRQFLAGS */
387 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
388 /* If the process has its own DBCR0 value, load it up. The internal
389 debug mode bit tells us that dbcr0 should be loaded. */
390 lwz r0,THREAD+THREAD_DBCR0(r2)
391 andis. r10,r0,DBCR0_IDM@h
395 BEGIN_MMU_FTR_SECTION
396 lis r4,icache_44x_need_flush@ha
397 lwz r5,icache_44x_need_flush@l(r4)
401 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
402 #endif /* CONFIG_44x */
405 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
406 stwcx. r0,0,r1 /* to clear the reservation */
407 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
410 CURRENT_THREAD_INFO(r4, r1)
411 ACCOUNT_CPU_USER_EXIT(r4, r5, r7)
429 stw r7,icache_44x_need_flush@l(r4)
431 #endif /* CONFIG_44x */
443 .globl ret_from_kernel_thread
444 ret_from_kernel_thread:
454 /* Traced system call support */
459 addi r3,r1,STACK_FRAME_OVERHEAD
460 bl do_syscall_trace_enter
462 * Restore argument registers possibly just changed.
463 * We use the return value of do_syscall_trace_enter
464 * for call number to look up in the table (r0).
475 cmplwi r0,NR_syscalls
476 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
477 bge- ret_from_syscall
478 b syscall_dotrace_cont
481 andi. r0,r9,_TIF_RESTOREALL
487 andi. r0,r9,_TIF_NOERROR
489 lwz r11,_CCR(r1) /* Load CR */
491 oris r11,r11,0x1000 /* Set SO bit in CR */
494 1: stw r6,RESULT(r1) /* Save result */
495 stw r3,GPR3(r1) /* Update return value */
496 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
499 /* Clear per-syscall TIF flags if any are set. */
501 li r11,_TIF_PERSYSCALL_MASK
502 addi r12,r12,TI_FLAGS
505 #ifdef CONFIG_IBM405_ERR77
510 subi r12,r12,TI_FLAGS
512 4: /* Anything which requires enabling interrupts? */
513 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
516 /* Re-enable interrupts. There is no need to trace that with
517 * lockdep as we are supposed to have IRQs on at this point
523 /* Save NVGPRS if they're not saved already */
531 addi r3,r1,STACK_FRAME_OVERHEAD
532 bl do_syscall_trace_leave
533 b ret_from_except_full
536 * The fork/clone functions need to copy the full register set into
537 * the child process. Therefore we need to save all the nonvolatile
538 * registers (r13 - r31) before calling the C code.
544 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
545 stw r0,_TRAP(r1) /* register set saved */
552 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
553 stw r0,_TRAP(r1) /* register set saved */
560 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
561 stw r0,_TRAP(r1) /* register set saved */
564 .globl ppc_swapcontext
568 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
569 stw r0,_TRAP(r1) /* register set saved */
573 * Top-level page fault handling.
574 * This is in assembler because if do_page_fault tells us that
575 * it is a bad kernel page fault, we want to save the non-volatile
576 * registers before calling bad_page_fault.
578 .globl handle_page_fault
581 addi r3,r1,STACK_FRAME_OVERHEAD
590 addi r3,r1,STACK_FRAME_OVERHEAD
593 b ret_from_except_full
596 * This routine switches between two different tasks. The process
597 * state of one is saved on its kernel stack. Then the state
598 * of the other is restored from its kernel stack. The memory
599 * management hardware is updated to the second process's state.
600 * Finally, we can return to the second process.
601 * On entry, r3 points to the THREAD for the current task, r4
602 * points to the THREAD for the new task.
604 * This routine is always called with interrupts disabled.
606 * Note: there are two ways to get to the "going out" portion
607 * of this code; either by coming in via the entry (_switch)
608 * or via "fork" which must set up an environment equivalent
609 * to the "_switch" path. If you change this , you'll have to
610 * change the fork code also.
612 * The code which creates the new task context is in 'copy_thread'
613 * in arch/ppc/kernel/process.c
616 stwu r1,-INT_FRAME_SIZE(r1)
618 stw r0,INT_FRAME_SIZE+4(r1)
619 /* r3-r12 are caller saved -- Cort */
621 stw r0,_NIP(r1) /* Return to switch caller */
623 li r0,MSR_FP /* Disable floating-point */
624 #ifdef CONFIG_ALTIVEC
626 oris r0,r0,MSR_VEC@h /* Disable altivec */
627 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
628 stw r12,THREAD+THREAD_VRSAVE(r2)
629 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
630 #endif /* CONFIG_ALTIVEC */
633 oris r0,r0,MSR_SPE@h /* Disable SPE */
634 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
635 stw r12,THREAD+THREAD_SPEFSCR(r2)
636 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
637 #endif /* CONFIG_SPE */
638 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
646 stw r1,KSP(r3) /* Set old stack pointer */
649 /* We need a sync somewhere here to make sure that if the
650 * previous task gets rescheduled on another CPU, it sees all
651 * stores it has performed on this one.
654 #endif /* CONFIG_SMP */
657 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
658 lwz r1,KSP(r4) /* Load new stack pointer */
660 /* save the old current 'last' for return value */
662 addi r2,r4,-THREAD /* Update current */
664 #ifdef CONFIG_ALTIVEC
666 lwz r0,THREAD+THREAD_VRSAVE(r2)
667 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
668 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
669 #endif /* CONFIG_ALTIVEC */
672 lwz r0,THREAD+THREAD_SPEFSCR(r2)
673 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
674 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
675 #endif /* CONFIG_SPE */
679 /* r3-r12 are destroyed -- Cort */
682 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
684 addi r1,r1,INT_FRAME_SIZE
687 .globl fast_exception_return
688 fast_exception_return:
689 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
690 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
691 beq 1f /* if not, we've got problems */
694 2: REST_4GPRS(3, r11)
709 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
710 /* check if the exception happened in a restartable section */
711 1: lis r3,exc_exit_restart_end@ha
712 addi r3,r3,exc_exit_restart_end@l
715 lis r4,exc_exit_restart@ha
716 addi r4,r4,exc_exit_restart@l
719 lis r3,fee_restarts@ha
721 lwz r5,fee_restarts@l(r3)
723 stw r5,fee_restarts@l(r3)
724 mr r12,r4 /* restart at exc_exit_restart */
733 /* aargh, a nonrecoverable interrupt, panic */
734 /* aargh, we don't know which trap this is */
735 /* but the 601 doesn't implement the RI bit, so assume it's OK */
739 END_FTR_SECTION_IFSET(CPU_FTR_601)
742 addi r3,r1,STACK_FRAME_OVERHEAD
744 ori r10,r10,MSR_KERNEL@l
745 bl transfer_to_handler_full
746 .long nonrecoverable_exception
747 .long ret_from_except
750 .globl ret_from_except_full
751 ret_from_except_full:
755 .globl ret_from_except
757 /* Hard-disable interrupts so that current_thread_info()->flags
758 * can't change between when we test it and when we return
759 * from the interrupt. */
760 /* Note: We don't bother telling lockdep about it */
761 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
762 SYNC /* Some chip revs have problems here... */
763 MTMSRD(r10) /* disable interrupts */
765 lwz r3,_MSR(r1) /* Returning to user mode? */
769 user_exc_return: /* r10 contains MSR_KERNEL here */
770 /* Check current_thread_info()->flags */
771 CURRENT_THREAD_INFO(r9, r1)
773 andi. r0,r9,_TIF_USER_WORK_MASK
777 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
778 /* Check whether this process has its own DBCR0 value. The internal
779 debug mode bit tells us that dbcr0 should be loaded. */
780 lwz r0,THREAD+THREAD_DBCR0(r2)
781 andis. r10,r0,DBCR0_IDM@h
784 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
785 CURRENT_THREAD_INFO(r9, r1)
786 ACCOUNT_CPU_USER_EXIT(r9, r10, r11)
791 /* N.B. the only way to get here is from the beq following ret_from_except. */
793 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
794 CURRENT_THREAD_INFO(r9, r1)
796 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
799 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
802 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
803 mr r4,r1 /* src: current exception frame */
804 mr r1,r3 /* Reroute the trampoline frame to r1 */
806 /* Copy from the original to the trampoline. */
807 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
808 li r6,0 /* start offset: 0 */
815 /* Do real store operation to complete stwu */
819 /* Clear _TIF_EMULATE_STACK_STORE flag */
820 lis r11,_TIF_EMULATE_STACK_STORE@h
824 #ifdef CONFIG_IBM405_ERR77
831 #ifdef CONFIG_PREEMPT
832 /* check current_thread_info->preempt_count */
833 lwz r0,TI_PREEMPT(r9)
834 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
836 andi. r8,r8,_TIF_NEED_RESCHED
839 andi. r0,r3,MSR_EE /* interrupts off? */
840 beq restore /* don't schedule if so */
841 #ifdef CONFIG_TRACE_IRQFLAGS
842 /* Lockdep thinks irqs are enabled, we need to call
843 * preempt_schedule_irq with IRQs off, so we inform lockdep
844 * now that we -did- turn them off already
846 bl trace_hardirqs_off
848 1: bl preempt_schedule_irq
849 CURRENT_THREAD_INFO(r9, r1)
851 andi. r0,r3,_TIF_NEED_RESCHED
853 #ifdef CONFIG_TRACE_IRQFLAGS
854 /* And now, to properly rebalance the above, we tell lockdep they
855 * are being turned back on, which will happen when we return
859 #endif /* CONFIG_PREEMPT */
861 /* interrupts are hard-disabled at this point */
864 BEGIN_MMU_FTR_SECTION
866 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
867 lis r4,icache_44x_need_flush@ha
868 lwz r5,icache_44x_need_flush@l(r4)
873 stw r6,icache_44x_need_flush@l(r4)
875 #endif /* CONFIG_44x */
878 #ifdef CONFIG_TRACE_IRQFLAGS
879 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
880 * off in this assembly code while peeking at TI_FLAGS() and such. However
881 * we need to inform it if the exception turned interrupts off, and we
882 * are about to trun them back on.
884 * The problem here sadly is that we don't know whether the exceptions was
885 * one that turned interrupts off or not. So we always tell lockdep about
886 * turning them on here when we go back to wherever we came from with EE
887 * on, even if that may meen some redudant calls being tracked. Maybe later
888 * we could encode what the exception did somewhere or test the exception
889 * type in the pt_regs but that sounds overkill
894 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
895 * which is the stack frame here, we need to force a stack frame
896 * in case we came from user space.
907 #endif /* CONFIG_TRACE_IRQFLAGS */
922 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
923 stwcx. r0,0,r1 /* to clear the reservation */
925 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
926 andi. r10,r9,MSR_RI /* check if this exception occurred */
927 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
935 * Once we put values in SRR0 and SRR1, we are in a state
936 * where exceptions are not recoverable, since taking an
937 * exception will trash SRR0 and SRR1. Therefore we clear the
938 * MSR:RI bit to indicate this. If we do take an exception,
939 * we can't return to the point of the exception but we
940 * can restart the exception exit path at the label
941 * exc_exit_restart below. -- paulus
943 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
945 MTMSRD(r10) /* clear the RI bit */
946 .globl exc_exit_restart
954 .globl exc_exit_restart_end
955 exc_exit_restart_end:
959 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
961 * This is a bit different on 4xx/Book-E because it doesn't have
962 * the RI bit in the MSR.
963 * The TLB miss handler checks if we have interrupted
964 * the exception exit path and restarts it if so
965 * (well maybe one day it will... :).
972 .globl exc_exit_restart
981 .globl exc_exit_restart_end
982 exc_exit_restart_end:
985 b . /* prevent prefetch past rfi */
988 * Returning from a critical interrupt in user mode doesn't need
989 * to be any different from a normal exception. For a critical
990 * interrupt in the kernel, we just return (without checking for
991 * preemption) since the interrupt may have happened at some crucial
992 * place (e.g. inside the TLB miss handler), and because we will be
993 * running with r1 pointing into critical_stack, not the current
994 * process's kernel stack (and therefore current_thread_info() will
995 * give the wrong answer).
996 * We have to restore various SPRs that may have been in use at the
997 * time of the critical interrupt.
1001 #define PPC_40x_TURN_OFF_MSR_DR \
1002 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1003 * assume the instructions here are mapped by a pinned TLB entry */ \
1009 #define PPC_40x_TURN_OFF_MSR_DR
1012 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1015 andi. r3,r3,MSR_PR; \
1016 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1017 bne user_exc_return; \
1020 REST_4GPRS(3, r1); \
1021 REST_2GPRS(7, r1); \
1024 mtspr SPRN_XER,r10; \
1026 PPC405_ERR77(0,r1); \
1027 stwcx. r0,0,r1; /* to clear the reservation */ \
1028 lwz r11,_LINK(r1); \
1032 PPC_40x_TURN_OFF_MSR_DR; \
1035 mtspr SPRN_DEAR,r9; \
1036 mtspr SPRN_ESR,r10; \
1039 mtspr exc_lvl_srr0,r11; \
1040 mtspr exc_lvl_srr1,r12; \
1042 lwz r12,GPR12(r1); \
1043 lwz r10,GPR10(r1); \
1044 lwz r11,GPR11(r1); \
1046 PPC405_ERR77_SYNC; \
1048 b .; /* prevent prefetch past exc_lvl_rfi */
1050 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1051 lwz r9,_##exc_lvl_srr0(r1); \
1052 lwz r10,_##exc_lvl_srr1(r1); \
1053 mtspr SPRN_##exc_lvl_srr0,r9; \
1054 mtspr SPRN_##exc_lvl_srr1,r10;
1056 #if defined(CONFIG_PPC_BOOK3E_MMU)
1057 #ifdef CONFIG_PHYS_64BIT
1058 #define RESTORE_MAS7 \
1060 mtspr SPRN_MAS7,r11;
1062 #define RESTORE_MAS7
1063 #endif /* CONFIG_PHYS_64BIT */
1064 #define RESTORE_MMU_REGS \
1068 mtspr SPRN_MAS0,r9; \
1070 mtspr SPRN_MAS1,r10; \
1072 mtspr SPRN_MAS2,r11; \
1073 mtspr SPRN_MAS3,r9; \
1074 mtspr SPRN_MAS6,r10; \
1076 #elif defined(CONFIG_44x)
1077 #define RESTORE_MMU_REGS \
1079 mtspr SPRN_MMUCR,r9;
1081 #define RESTORE_MMU_REGS
1085 .globl ret_from_crit_exc
1087 mfspr r9,SPRN_SPRG_THREAD
1088 lis r10,saved_ksp_limit@ha;
1089 lwz r10,saved_ksp_limit@l(r10);
1091 stw r10,KSP_LIMIT(r9)
1092 lis r9,crit_srr0@ha;
1093 lwz r9,crit_srr0@l(r9);
1094 lis r10,crit_srr1@ha;
1095 lwz r10,crit_srr1@l(r10);
1097 mtspr SPRN_SRR1,r10;
1098 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1099 #endif /* CONFIG_40x */
1102 .globl ret_from_crit_exc
1104 mfspr r9,SPRN_SPRG_THREAD
1105 lwz r10,SAVED_KSP_LIMIT(r1)
1106 stw r10,KSP_LIMIT(r9)
1107 RESTORE_xSRR(SRR0,SRR1);
1109 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1111 .globl ret_from_debug_exc
1113 mfspr r9,SPRN_SPRG_THREAD
1114 lwz r10,SAVED_KSP_LIMIT(r1)
1115 stw r10,KSP_LIMIT(r9)
1116 lwz r9,THREAD_INFO-THREAD(r9)
1117 CURRENT_THREAD_INFO(r10, r1)
1118 lwz r10,TI_PREEMPT(r10)
1119 stw r10,TI_PREEMPT(r9)
1120 RESTORE_xSRR(SRR0,SRR1);
1121 RESTORE_xSRR(CSRR0,CSRR1);
1123 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1125 .globl ret_from_mcheck_exc
1126 ret_from_mcheck_exc:
1127 mfspr r9,SPRN_SPRG_THREAD
1128 lwz r10,SAVED_KSP_LIMIT(r1)
1129 stw r10,KSP_LIMIT(r9)
1130 RESTORE_xSRR(SRR0,SRR1);
1131 RESTORE_xSRR(CSRR0,CSRR1);
1132 RESTORE_xSRR(DSRR0,DSRR1);
1134 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1135 #endif /* CONFIG_BOOKE */
1138 * Load the DBCR0 value for a task that is being ptraced,
1139 * having first saved away the global DBCR0. Note that r0
1140 * has the dbcr0 value to set upon entry to this.
1143 mfmsr r10 /* first disable debug exceptions */
1144 rlwinm r10,r10,0,~MSR_DE
1147 mfspr r10,SPRN_DBCR0
1148 lis r11,global_dbcr0@ha
1149 addi r11,r11,global_dbcr0@l
1151 CURRENT_THREAD_INFO(r9, r1)
1162 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1170 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1172 do_work: /* r10 contains MSR_KERNEL here */
1173 andi. r0,r9,_TIF_NEED_RESCHED
1176 do_resched: /* r10 contains MSR_KERNEL here */
1177 /* Note: We don't need to inform lockdep that we are enabling
1178 * interrupts here. As far as it knows, they are already enabled
1182 MTMSRD(r10) /* hard-enable interrupts */
1185 /* Note: And we don't tell it we are disabling them again
1186 * neither. Those disable/enable cycles used to peek at
1187 * TI_FLAGS aren't advertised.
1189 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1191 MTMSRD(r10) /* disable interrupts */
1192 CURRENT_THREAD_INFO(r9, r1)
1194 andi. r0,r9,_TIF_NEED_RESCHED
1196 andi. r0,r9,_TIF_USER_WORK_MASK
1198 do_user_signal: /* r10 contains MSR_KERNEL here */
1201 MTMSRD(r10) /* hard-enable interrupts */
1202 /* save r13-r31 in the exception frame, if not already done */
1209 2: addi r3,r1,STACK_FRAME_OVERHEAD
1216 * We come here when we are at the end of handling an exception
1217 * that occurred at a place where taking an exception will lose
1218 * state information, such as the contents of SRR0 and SRR1.
1221 lis r10,exc_exit_restart_end@ha
1222 addi r10,r10,exc_exit_restart_end@l
1225 lis r11,exc_exit_restart@ha
1226 addi r11,r11,exc_exit_restart@l
1229 lis r10,ee_restarts@ha
1230 lwz r12,ee_restarts@l(r10)
1232 stw r12,ee_restarts@l(r10)
1233 mr r12,r11 /* restart at exc_exit_restart */
1235 3: /* OK, we can't recover, kill this process */
1236 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1239 END_FTR_SECTION_IFSET(CPU_FTR_601)
1246 4: addi r3,r1,STACK_FRAME_OVERHEAD
1247 bl nonrecoverable_exception
1248 /* shouldn't return */
1258 * PROM code for specific machines follows. Put it
1259 * here so it's easy to add arch-specific sections later.
1262 #ifdef CONFIG_PPC_RTAS
1264 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1265 * called with the MMU off.
1268 stwu r1,-INT_FRAME_SIZE(r1)
1270 stw r0,INT_FRAME_SIZE+4(r1)
1271 LOAD_REG_ADDR(r4, rtas)
1272 lis r6,1f@ha /* physical return address for rtas */
1276 lwz r8,RTASENTRY(r4)
1280 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1281 SYNC /* disable interrupts so SRR0/1 */
1282 MTMSRD(r0) /* don't get trashed */
1283 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1285 mtspr SPRN_SPRG_RTAS,r7
1290 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1291 lwz r9,8(r9) /* original msr value */
1293 addi r1,r1,INT_FRAME_SIZE
1295 mtspr SPRN_SPRG_RTAS,r0
1298 RFI /* return to caller */
1300 .globl machine_check_in_rtas
1301 machine_check_in_rtas:
1303 /* XXX load up BATs and panic */
1305 #endif /* CONFIG_PPC_RTAS */
1307 #ifdef CONFIG_FUNCTION_TRACER
1308 #ifdef CONFIG_DYNAMIC_FTRACE
1312 * It is required that _mcount on PPC32 must preserve the
1313 * link register. But we have r0 to play with. We use r0
1314 * to push the return address back to the caller of mcount
1315 * into the ctr register, restore the link register and
1316 * then jump back using the ctr register.
1324 _GLOBAL(ftrace_caller)
1326 /* r3 ends up with link register */
1327 subi r3, r3, MCOUNT_INSN_SIZE
1332 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1333 .globl ftrace_graph_call
1336 _GLOBAL(ftrace_graph_stub)
1338 MCOUNT_RESTORE_FRAME
1339 /* old link register ends up in ctr reg */
1347 subi r3, r3, MCOUNT_INSN_SIZE
1348 LOAD_REG_ADDR(r5, ftrace_trace_function)
1355 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1356 b ftrace_graph_caller
1358 MCOUNT_RESTORE_FRAME
1362 _GLOBAL(ftrace_stub)
1365 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1366 _GLOBAL(ftrace_graph_caller)
1367 /* load r4 with local address */
1369 subi r4, r4, MCOUNT_INSN_SIZE
1371 /* Grab the LR out of the caller stack frame */
1374 bl prepare_ftrace_return
1378 * prepare_ftrace_return gives us the address we divert to.
1379 * Change the LR in the callers stack frame to this.
1383 MCOUNT_RESTORE_FRAME
1384 /* old link register ends up in ctr reg */
1387 _GLOBAL(return_to_handler)
1388 /* need to save return values */
1395 bl ftrace_return_to_handler
1398 /* return value has real return address */
1406 /* Jump back to real return address */
1408 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1410 #endif /* CONFIG_FUNCTION_TRACER */