arch/powerpc/kernel/fpu.S

   1 /*
   2  *  FPU support code, moved here from head.S so that it can be used
   3  *  by chips which use other head-whatever.S files.
   4  *
   5  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *    Copyright (C) 1996 Paul Mackerras.
   8  *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
   9  *
  10  *  This program is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU General Public License
  12  *  as published by the Free Software Foundation; either version
  13  *  2 of the License, or (at your option) any later version.
  14  *
  15  */
  16
  17 #include <asm/reg.h>
  18 #include <asm/page.h>
  19 #include <asm/mmu.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/cputable.h>
  22 #include <asm/cache.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/ppc_asm.h>
  25 #include <asm/asm-offsets.h>
  26 #include <asm/ptrace.h>
  27
  28 #ifdef CONFIG_VSX
  29 #define __REST_32FPVSRS(n,c,base)                                       \
  30 BEGIN_FTR_SECTION                                                       \
  31         b       2f;                                                     \
  32 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  33         REST_32FPRS(n,base);                                            \
  34         b       3f;                                                     \
  35 2:      REST_32VSRS(n,c,base);                                          \
  36 3:
  37
  38 #define __SAVE_32FPVSRS(n,c,base)                                       \
  39 BEGIN_FTR_SECTION                                                       \
  40         b       2f;                                                     \
  41 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
  42         SAVE_32FPRS(n,base);                                            \
  43         b       3f;                                                     \
  44 2:      SAVE_32VSRS(n,c,base);                                          \
  45 3:
  46 #else
  47 #define __REST_32FPVSRS(n,b,base)       REST_32FPRS(n, base)
  48 #define __SAVE_32FPVSRS(n,b,base)       SAVE_32FPRS(n, base)
  49 #endif
  50 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
  51 #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
  52
  53 /*
  54  * Load state from memory into FP registers including FPSCR.
  55  * Assumes the caller has enabled FP in the MSR.
  56  */
  57 _GLOBAL(load_fp_state)
  58         lfd     fr0,FPSTATE_FPSCR(r3)
  59         MTFSF_L(fr0)
  60         REST_32FPVSRS(0, R4, R3)
  61         blr
  62
  63 /*
  64  * Store FP state into memory, including FPSCR
  65  * Assumes the caller has enabled FP in the MSR.
  66  */
  67 _GLOBAL(store_fp_state)
  68         SAVE_32FPVSRS(0, R4, R3)
  69         mffs    fr0
  70         stfd    fr0,FPSTATE_FPSCR(r3)
  71         blr
  72
  73 /*
  74  * This task wants to use the FPU now.
  75  * On UP, disable FP for the task which had the FPU previously,
  76  * and save its floating-point registers in its thread_struct.
  77  * Load up this task's FP registers from its thread_struct,
  78  * enable the FPU for the current task and return to the task.
  79  * Note that on 32-bit this can only use registers that will be
  80  * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
  81  */
  82 _GLOBAL(load_up_fpu)
  83         mfmsr   r5
  84         ori     r5,r5,MSR_FP
  85 #ifdef CONFIG_VSX
  86 BEGIN_FTR_SECTION
  87         oris    r5,r5,MSR_VSX@h
  88 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  89 #endif
  90         SYNC
  91         MTMSRD(r5)                      /* enable use of fpu now */
  92         isync
  93         /* enable use of FP after return */
  94 #ifdef CONFIG_PPC32
  95         mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
  96         lwz     r4,THREAD_FPEXC_MODE(r5)
  97         ori     r9,r9,MSR_FP            /* enable FP for current */
  98         or      r9,r9,r4
  99 #else
 100         ld      r4,PACACURRENT(r13)
 101         addi    r5,r4,THREAD            /* Get THREAD */
 102         lwz     r4,THREAD_FPEXC_MODE(r5)
 103         ori     r12,r12,MSR_FP
 104         or      r12,r12,r4
 105         std     r12,_MSR(r1)
 106 #endif
 107         /* Don't care if r4 overflows, this is desired behaviour */
 108         lbz     r4,THREAD_LOAD_FP(r5)
 109         addi    r4,r4,1
 110         stb     r4,THREAD_LOAD_FP(r5)
 111         addi    r10,r5,THREAD_FPSTATE
 112         lfd     fr0,FPSTATE_FPSCR(r10)
 113         MTFSF_L(fr0)
 114         REST_32FPVSRS(0, R4, R10)
 115         /* restore registers and return */
 116         /* we haven't used ctr or xer or lr */
 117         blr
 118
 119 /*
 120  * save_fpu(tsk)
 121  * Save the floating-point registers in its thread_struct.
 122  * Enables the FPU for use in the kernel on return.
 123  */
 124 _GLOBAL(save_fpu)
 125         addi    r3,r3,THREAD            /* want THREAD of task */
 126         PPC_LL  r6,THREAD_FPSAVEAREA(r3)
 127         PPC_LL  r5,PT_REGS(r3)
 128         PPC_LCMPI       0,r6,0
 129         bne     2f
 130         addi    r6,r3,THREAD_FPSTATE
 131 2:      SAVE_32FPVSRS(0, R4, R6)
 132         mffs    fr0
 133         stfd    fr0,FPSTATE_FPSCR(r6)
 134         blr
 135
 136 /*
 137  * These are used in the alignment trap handler when emulating
 138  * single-precision loads and stores.
 139  */
 140
 141 _GLOBAL(cvt_fd)
 142         lfs     0,0(r3)
 143         stfd    0,0(r4)
 144         blr
 145
 146 _GLOBAL(cvt_df)
 147         lfd     0,0(r3)
 148         stfs    0,0(r4)
 149         blr