3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
24 #include <linux/init.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
34 #include <asm/ptrace.h>
36 #include <asm/kvm_book3s_asm.h>
37 #include <asm/export.h>
39 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
40 #define LOAD_BAT(n, reg, RA, RB) \
41 /* see the comment for clear_bats() -- Cort */ \
43 mtspr SPRN_IBAT##n##U,RA; \
44 mtspr SPRN_DBAT##n##U,RA; \
45 lwz RA,(n*16)+0(reg); \
46 lwz RB,(n*16)+4(reg); \
47 mtspr SPRN_IBAT##n##U,RA; \
48 mtspr SPRN_IBAT##n##L,RB; \
50 lwz RA,(n*16)+8(reg); \
51 lwz RB,(n*16)+12(reg); \
52 mtspr SPRN_DBAT##n##U,RA; \
53 mtspr SPRN_DBAT##n##L,RB; \
57 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
58 .stabs "head_32.S",N_SO,0,0,0f
63 * _start is defined this way because the XCOFF loader in the OpenFirmware
64 * on the powermac expects the entry point to be a procedure descriptor.
68 * These are here for legacy reasons, the kernel used to
69 * need to look like a coff function entry for the pmac
70 * but we're always started by some kind of bootloader now.
73 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
74 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
78 * Enter here with the kernel text, data and bss loaded starting at
79 * 0, running with virtual == physical mapping.
80 * r5 points to the prom entry point (the client interface handler
81 * address). Address translation is turned on, with the prom
82 * managing the hash table. Interrupts are disabled. The stack
83 * pointer (r1) points to just below the end of the half-meg region
84 * from 0x380000 - 0x400000, which is mapped in already.
86 * If we are booted from MacOS via BootX, we enter with the kernel
87 * image loaded somewhere, and the following values in registers:
88 * r3: 'BooX' (0x426f6f58)
89 * r4: virtual address of boot_infos_t
93 * This is jumped to on prep systems right after the kernel is relocated
94 * to its proper place in memory by the boot loader. The expected layout
96 * r3: ptr to residual data
97 * r4: initrd_start or if no initrd then 0
98 * r5: initrd_end - unused if r4 is 0
99 * r6: Start of command line string
100 * r7: End of command line string
102 * This just gets a minimal mmu environment setup so we can call
103 * start_here() to do the real work.
110 * We have to do any OF calls before we map ourselves to KERNELBASE,
111 * because OF may have I/O devices mapped into that area
112 * (particularly on CHRP).
117 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
118 /* find out where we are now */
120 0: mflr r8 /* r8 = runtime addr here */
121 addis r8,r8,(_stext - 0b)@ha
122 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
124 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
126 /* We never return. We also hit that trap if trying to boot
127 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
131 * Check for BootX signature when supporting PowerMac and branch to
132 * appropriate trampoline if it's present
134 #ifdef CONFIG_PPC_PMAC
141 #endif /* CONFIG_PPC_PMAC */
143 1: mr r31,r3 /* save device tree ptr */
147 * early_init() does the early machine identification and does
148 * the necessary low-level setup and clears the BSS
149 * -- Cort <cort@fsmlabs.com>
153 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
154 * the physical address we are running at, returned by early_init()
162 #if defined(CONFIG_BOOTX_TEXT)
165 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
168 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
169 bl setup_usbgecko_bat
173 * Call setup_cpu for CPU 0 and initialize 6xx Idle
177 bl call_setup_cpu /* Call setup_cpu for this CPU */
181 #endif /* CONFIG_6xx */
185 * We need to run with _start at physical address 0.
186 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
187 * the exception vectors at 0 (and therefore this copy
188 * overwrites OF's exception vectors with our own).
189 * The MMU is off at this point.
193 addis r4,r3,KERNELBASE@h /* current address of _start */
194 lis r5,PHYSICAL_START@h
195 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
198 * we now have the 1st 16M of ram mapped with the bats.
199 * prep needs the mmu to be turned on here, but pmac already has it on.
200 * this shouldn't bother the pmac since it just gets turned on again
201 * as we jump to our code at KERNELBASE. -- Cort
202 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
203 * off, and in other cases, we now turn it off before changing BATs above.
207 ori r0,r0,MSR_DR|MSR_IR
210 ori r0,r0,start_here@l
213 RFI /* enables MMU */
216 * We need __secondary_hold as a place to hold the other cpus on
217 * an SMP machine, even when we are running a UP kernel.
219 . = 0xc0 /* for prep bootloader */
220 li r3,1 /* MTX only has 1 cpu */
221 .globl __secondary_hold
223 /* tell the master we're here */
224 stw r3,__secondary_hold_acknowledge@l(0)
227 /* wait until we're told to start */
230 /* our cpu # was at addr 0 - go */
231 mr r24,r3 /* cpu # */
235 #endif /* CONFIG_SMP */
237 .globl __secondary_hold_spinloop
238 __secondary_hold_spinloop:
240 .globl __secondary_hold_acknowledge
241 __secondary_hold_acknowledge:
245 * Exception entry code. This code runs with address translation
246 * turned off, i.e. using physical addresses.
247 * We assume sprg3 has the physical address of the current
248 * task's thread_struct.
250 #define EXCEPTION_PROLOG \
251 mtspr SPRN_SPRG_SCRATCH0,r10; \
252 mtspr SPRN_SPRG_SCRATCH1,r11; \
254 EXCEPTION_PROLOG_1; \
257 #define EXCEPTION_PROLOG_1 \
258 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
259 andi. r11,r11,MSR_PR; \
260 tophys(r11,r1); /* use tophys(r1) if kernel */ \
262 mfspr r11,SPRN_SPRG_THREAD; \
263 lwz r11,THREAD_INFO-THREAD(r11); \
264 addi r11,r11,THREAD_SIZE; \
266 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
269 #define EXCEPTION_PROLOG_2 \
271 stw r10,_CCR(r11); /* save registers */ \
272 stw r12,GPR12(r11); \
274 mfspr r10,SPRN_SPRG_SCRATCH0; \
275 stw r10,GPR10(r11); \
276 mfspr r12,SPRN_SPRG_SCRATCH1; \
277 stw r12,GPR11(r11); \
279 stw r10,_LINK(r11); \
280 mfspr r12,SPRN_SRR0; \
281 mfspr r9,SPRN_SRR1; \
284 tovirt(r1,r11); /* set new kernel sp */ \
285 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
286 MTMSRD(r10); /* (except for mach check in rtas) */ \
288 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
289 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
291 SAVE_4GPRS(3, r11); \
295 * Note: code which follows this uses cr0.eq (set if from kernel),
296 * r11, r12 (SRR0), and r9 (SRR1).
298 * Note2: once we have set r1 we are in a position to take exceptions
299 * again, and we could thus set MSR:RI at that point.
305 #define EXCEPTION(n, label, hdlr, xfer) \
310 addi r3,r1,STACK_FRAME_OVERHEAD; \
313 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
315 stw r10,_TRAP(r11); \
323 #define COPY_EE(d, s) rlwimi d,s,0,16,16
326 #define EXC_XFER_STD(n, hdlr) \
327 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
328 ret_from_except_full)
330 #define EXC_XFER_LITE(n, hdlr) \
331 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
334 #define EXC_XFER_EE(n, hdlr) \
335 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
336 ret_from_except_full)
338 #define EXC_XFER_EE_LITE(n, hdlr) \
339 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
343 /* core99 pmac starts the seconary here by changing the vector, and
344 putting it back to what it was (unknown_exception) when done. */
345 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
349 * On CHRP, this is complicated by the fact that we could get a
350 * machine check inside RTAS, and we have no guarantee that certain
351 * critical registers will have the values we expect. The set of
352 * registers that might have bad values includes all the GPRs
353 * and all the BATs. We indicate that we are in RTAS by putting
354 * a non-zero value, the address of the exception frame to use,
355 * in SPRG2. The machine check handler checks SPRG2 and uses its
356 * value if it is non-zero. If we ever needed to free up SPRG2,
357 * we could use a field in the thread_info or thread_struct instead.
358 * (Other exception handlers assume that r1 is a valid kernel stack
359 * pointer when we take an exception from supervisor mode.)
364 mtspr SPRN_SPRG_SCRATCH0,r10
365 mtspr SPRN_SPRG_SCRATCH1,r11
367 #ifdef CONFIG_PPC_CHRP
368 mfspr r11,SPRN_SPRG_RTAS
371 #endif /* CONFIG_PPC_CHRP */
373 7: EXCEPTION_PROLOG_2
374 addi r3,r1,STACK_FRAME_OVERHEAD
375 #ifdef CONFIG_PPC_CHRP
376 mfspr r4,SPRN_SPRG_RTAS
380 EXC_XFER_STD(0x200, machine_check_exception)
381 #ifdef CONFIG_PPC_CHRP
382 1: b machine_check_in_rtas
385 /* Data access exception. */
392 andis. r0,r10,0xa470 /* weird error? */
393 bne 1f /* if not, try to put a PTE */
394 mfspr r4,SPRN_DAR /* into the hash table */
395 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
397 1: lwz r5,_DSISR(r11) /* get DSISR value */
399 EXC_XFER_LITE(0x300, handle_page_fault)
402 /* Instruction access exception. */
407 andis. r0,r9,0x4000 /* no pte found? */
408 beq 1f /* if so, try to put a PTE */
409 li r3,0 /* into the hash table */
410 mr r4,r12 /* SRR0 is fault address */
414 EXC_XFER_LITE(0x400, handle_page_fault)
416 /* External interrupt */
417 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
419 /* Alignment exception */
428 addi r3,r1,STACK_FRAME_OVERHEAD
429 EXC_XFER_EE(0x600, alignment_exception)
431 /* Program check exception */
432 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
434 /* Floating-point unavailable */
440 * Certain Freescale cores don't have a FPU and treat fp instructions
441 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
444 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
447 bl load_up_fpu /* if from user, just load it up */
448 b fast_exception_return
449 1: addi r3,r1,STACK_FRAME_OVERHEAD
450 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
453 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
455 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
456 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
463 EXC_XFER_EE_LITE(0xc00, DoSyscall)
465 /* Single step - not used on 601 */
466 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
467 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
470 * The Altivec unavailable trap is at 0x0f20. Foo.
471 * We effectively remap it to 0x3000.
472 * We include an altivec unavailable exception vector even if
473 * not configured for Altivec, so that you can't panic a
474 * non-altivec kernel running on a machine with altivec just
475 * by executing an altivec instruction.
486 * Handle TLB miss for instruction on 603/603e.
487 * Note: we get an alternate set of r0 - r3 to use automatically.
493 * r1: linux style pte ( later becomes ppc hardware pte )
494 * r2: ptr to linux-style pte
497 /* Get PTE (linux-style) and check access */
499 lis r1,PAGE_OFFSET@h /* check if kernel address */
501 mfspr r2,SPRN_SPRG_THREAD
502 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
505 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
506 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
507 lis r2,swapper_pg_dir@ha /* if kernel address, use */
508 addi r2,r2,swapper_pg_dir@l /* kernel page table */
510 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
511 lwz r2,0(r2) /* get pmd entry */
512 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
513 beq- InstructionAddressInvalid /* return if no mapping */
514 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
515 lwz r0,0(r2) /* get linux-style pte */
516 andc. r1,r1,r0 /* check access & ~permission */
517 bne- InstructionAddressInvalid /* return if access not permitted */
518 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
520 * NOTE! We are assuming this is not an SMP system, otherwise
521 * we would need to update the pte atomically with lwarx/stwcx.
523 stw r0,0(r2) /* update PTE (accessed bit) */
524 /* Convert linux-style PTE to low word of PPC-style PTE */
525 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
526 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
527 and r1,r1,r2 /* writable if _RW and _DIRTY */
528 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
529 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
530 ori r1,r1,0xe04 /* clear out reserved bits */
531 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
533 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
534 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
537 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
540 InstructionAddressInvalid:
542 rlwinm r1,r3,9,6,6 /* Get load/store bit */
545 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
546 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
549 mfspr r1,SPRN_IMISS /* Get failing address */
550 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
551 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
553 mtspr SPRN_DAR,r1 /* Set fault address */
554 mfmsr r0 /* Restore "normal" registers */
555 xoris r0,r0,MSR_TGPR>>16
556 mtcrf 0x80,r3 /* Restore CR0 */
561 * Handle TLB miss for DATA Load operation on 603/603e
567 * r1: linux style pte ( later becomes ppc hardware pte )
568 * r2: ptr to linux-style pte
571 /* Get PTE (linux-style) and check access */
573 lis r1,PAGE_OFFSET@h /* check if kernel address */
575 mfspr r2,SPRN_SPRG_THREAD
576 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
579 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
580 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
581 lis r2,swapper_pg_dir@ha /* if kernel address, use */
582 addi r2,r2,swapper_pg_dir@l /* kernel page table */
584 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
585 lwz r2,0(r2) /* get pmd entry */
586 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
587 beq- DataAddressInvalid /* return if no mapping */
588 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
589 lwz r0,0(r2) /* get linux-style pte */
590 andc. r1,r1,r0 /* check access & ~permission */
591 bne- DataAddressInvalid /* return if access not permitted */
592 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
594 * NOTE! We are assuming this is not an SMP system, otherwise
595 * we would need to update the pte atomically with lwarx/stwcx.
597 stw r0,0(r2) /* update PTE (accessed bit) */
598 /* Convert linux-style PTE to low word of PPC-style PTE */
599 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
600 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
601 and r1,r1,r2 /* writable if _RW and _DIRTY */
602 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
603 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
604 ori r1,r1,0xe04 /* clear out reserved bits */
605 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
607 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
608 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
610 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
612 BEGIN_MMU_FTR_SECTION
614 mfspr r1,SPRN_SPRG_603_LRU
615 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
619 mtspr SPRN_SPRG_603_LRU,r1
621 rlwimi r2,r0,31-14,14,14
623 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
628 rlwinm r1,r3,9,6,6 /* Get load/store bit */
631 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
633 mfspr r1,SPRN_DMISS /* Get failing address */
634 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
635 beq 20f /* Jump if big endian */
637 20: mtspr SPRN_DAR,r1 /* Set fault address */
638 mfmsr r0 /* Restore "normal" registers */
639 xoris r0,r0,MSR_TGPR>>16
640 mtcrf 0x80,r3 /* Restore CR0 */
645 * Handle TLB miss for DATA Store on 603/603e
651 * r1: linux style pte ( later becomes ppc hardware pte )
652 * r2: ptr to linux-style pte
655 /* Get PTE (linux-style) and check access */
657 lis r1,PAGE_OFFSET@h /* check if kernel address */
659 mfspr r2,SPRN_SPRG_THREAD
660 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
663 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
664 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
665 lis r2,swapper_pg_dir@ha /* if kernel address, use */
666 addi r2,r2,swapper_pg_dir@l /* kernel page table */
668 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
669 lwz r2,0(r2) /* get pmd entry */
670 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
671 beq- DataAddressInvalid /* return if no mapping */
672 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
673 lwz r0,0(r2) /* get linux-style pte */
674 andc. r1,r1,r0 /* check access & ~permission */
675 bne- DataAddressInvalid /* return if access not permitted */
676 ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
678 * NOTE! We are assuming this is not an SMP system, otherwise
679 * we would need to update the pte atomically with lwarx/stwcx.
681 stw r0,0(r2) /* update PTE (accessed/dirty bits) */
682 /* Convert linux-style PTE to low word of PPC-style PTE */
683 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
684 li r1,0xe05 /* clear out reserved bits & PP lsb */
685 andc r1,r0,r1 /* PP = user? 2: 0 */
687 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
688 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
690 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
692 BEGIN_MMU_FTR_SECTION
694 mfspr r1,SPRN_SPRG_603_LRU
695 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
699 mtspr SPRN_SPRG_603_LRU,r1
701 rlwimi r2,r0,31-14,14,14
703 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
707 #ifndef CONFIG_ALTIVEC
708 #define altivec_assist_exception unknown_exception
711 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
712 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
713 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
714 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
715 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
716 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
717 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
718 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
719 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
720 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
721 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
722 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
723 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
724 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
725 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
726 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
727 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
728 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
729 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
730 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
731 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
732 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
733 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
734 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
735 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
736 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
737 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
738 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
739 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
741 .globl mol_trampoline
742 .set mol_trampoline, i0x2f00
743 EXPORT_SYMBOL(mol_trampoline)
749 #ifdef CONFIG_ALTIVEC
751 bl load_up_altivec /* if from user, just load it up */
752 b fast_exception_return
753 #endif /* CONFIG_ALTIVEC */
754 1: addi r3,r1,STACK_FRAME_OVERHEAD
755 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
759 addi r3,r1,STACK_FRAME_OVERHEAD
760 EXC_XFER_STD(0xf00, performance_monitor_exception)
764 * This code is jumped to from the startup code to copy
765 * the kernel image to physical address PHYSICAL_START.
768 addis r9,r26,klimit@ha /* fetch klimit */
770 addis r25,r25,-KERNELBASE@h
771 lis r3,PHYSICAL_START@h /* Destination base address */
772 li r6,0 /* Destination offset */
773 li r5,0x4000 /* # bytes of memory to copy */
774 bl copy_and_flush /* copy the first 0x4000 bytes */
775 addi r0,r3,4f@l /* jump to the address of 4f */
776 mtctr r0 /* in copy and do the rest. */
777 bctr /* jump to the copy */
779 bl copy_and_flush /* copy the rest */
783 * Copy routine used to copy the kernel to start at physical address 0
784 * and flush and invalidate the caches as needed.
785 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
786 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
788 _ENTRY(copy_and_flush)
791 4: li r0,L1_CACHE_BYTES/4
793 3: addi r6,r6,4 /* copy a cache line */
797 dcbst r6,r3 /* write it to memory */
799 icbi r6,r3 /* flush the icache line */
802 sync /* additional sync needed on g4 */
809 .globl __secondary_start_mpc86xx
810 __secondary_start_mpc86xx:
812 stw r3, __secondary_hold_acknowledge@l(0)
813 mr r24, r3 /* cpu # */
816 .globl __secondary_start_pmac_0
817 __secondary_start_pmac_0:
818 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
827 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
828 set to map the 0xf0000000 - 0xffffffff region */
830 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
835 .globl __secondary_start
837 /* Copy some CPU settings from CPU 0 */
838 bl __restore_cpu_setup
842 bl call_setup_cpu /* Call setup_cpu for this CPU */
846 #endif /* CONFIG_6xx */
848 /* get current_thread_info and current */
849 lis r1,secondary_ti@ha
851 lwz r1,secondary_ti@l(r1)
856 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
861 /* load up the MMU */
864 /* ptr to phys current thread */
866 addi r4,r4,THREAD /* phys address of our thread_struct */
868 mtspr SPRN_SPRG_THREAD,r4
870 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
872 /* enable MMU and jump to start_secondary */
875 lis r3,start_secondary@h
876 ori r3,r3,start_secondary@l
881 #endif /* CONFIG_SMP */
883 #ifdef CONFIG_KVM_BOOK3S_HANDLER
884 #include "../kvm/book3s_rmhandlers.S"
888 * Those generic dummy functions are kept for CPUs not
889 * included in CONFIG_6xx
891 #if !defined(CONFIG_6xx)
892 _ENTRY(__save_cpu_setup)
894 _ENTRY(__restore_cpu_setup)
896 #endif /* !defined(CONFIG_6xx) */
900 * Load stuff into the MMU. Intended to be called with
904 sync /* Force all PTE updates to finish */
906 tlbia /* Clear all TLB entries */
907 sync /* wait for tlbia/tlbie to finish */
908 TLBSYNC /* ... on all CPUs */
909 /* Load the SDR1 register (hash table base & size) */
914 li r0,16 /* load up segment register values */
915 mtctr r0 /* for context 0 */
916 lis r3,0x2000 /* Ku = 1, VSID = 0 */
919 addi r3,r3,0x111 /* increment VSID */
920 addis r4,r4,0x1000 /* address of next segment */
923 /* Load the BAT registers with the values set up by MMU_init.
924 MMU_init takes care of whether we're on a 601 or not. */
935 BEGIN_MMU_FTR_SECTION
940 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
944 * This is where the main kernel code starts.
949 ori r2,r2,init_task@l
950 /* Set up for using our exception vectors */
951 /* ptr to phys current thread */
953 addi r4,r4,THREAD /* init task's THREAD */
955 mtspr SPRN_SPRG_THREAD,r4
957 mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
960 lis r1,init_thread_union@ha
961 addi r1,r1,init_thread_union@l
963 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
965 * Do early platform-specific initialization,
966 * and set up the MMU.
975 * Go back to running unmapped so we can load up new values
976 * for SDR1 (hash table pointer) and the segment registers
977 * and change to using our exception vectors.
982 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
988 /* Load up the kernel context */
991 #ifdef CONFIG_BDI_SWITCH
992 /* Add helper information for the Abatron bdiGDB debugger.
993 * We do this here because we know the mmu is disabled, and
994 * will be enabled for real in just a few instructions.
996 lis r5, abatron_pteptrs@h
997 ori r5, r5, abatron_pteptrs@l
998 stw r5, 0xf0(r0) /* This much match your Abatron config */
999 lis r6, swapper_pg_dir@h
1000 ori r6, r6, swapper_pg_dir@l
1003 #endif /* CONFIG_BDI_SWITCH */
1005 /* Now turn on the MMU for real! */
1008 lis r3,start_kernel@h
1009 ori r3,r3,start_kernel@l
1016 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1018 * Set up the segment registers for a new context.
1020 _ENTRY(switch_mmu_context)
1021 lwz r3,MMCONTEXTID(r4)
1024 mulli r3,r3,897 /* multiply context by skew factor */
1025 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1026 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1027 li r0,NUM_USER_SEGMENTS
1030 #ifdef CONFIG_BDI_SWITCH
1031 /* Context switch the PTE pointer for the Abatron BDI2000.
1032 * The PGDIR is passed as second argument.
1035 lis r5, KERNELBASE@h
1043 addi r3,r3,0x111 /* next VSID */
1044 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1045 addis r4,r4,0x1000 /* address of next segment */
1051 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1053 EXPORT_SYMBOL(switch_mmu_context)
1056 * An undocumented "feature" of 604e requires that the v bit
1057 * be cleared before changing BAT values.
1059 * Also, newer IBM firmware does not clear bat3 and 4 so
1060 * this makes sure it's done.
1066 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1070 mtspr SPRN_DBAT0U,r10
1071 mtspr SPRN_DBAT0L,r10
1072 mtspr SPRN_DBAT1U,r10
1073 mtspr SPRN_DBAT1L,r10
1074 mtspr SPRN_DBAT2U,r10
1075 mtspr SPRN_DBAT2L,r10
1076 mtspr SPRN_DBAT3U,r10
1077 mtspr SPRN_DBAT3L,r10
1079 mtspr SPRN_IBAT0U,r10
1080 mtspr SPRN_IBAT0L,r10
1081 mtspr SPRN_IBAT1U,r10
1082 mtspr SPRN_IBAT1L,r10
1083 mtspr SPRN_IBAT2U,r10
1084 mtspr SPRN_IBAT2L,r10
1085 mtspr SPRN_IBAT3U,r10
1086 mtspr SPRN_IBAT3L,r10
1087 BEGIN_MMU_FTR_SECTION
1088 /* Here's a tweak: at this point, CPU setup have
1089 * not been called yet, so HIGH_BAT_EN may not be
1090 * set in HID0 for the 745x processors. However, it
1091 * seems that doesn't affect our ability to actually
1092 * write to these SPRs.
1094 mtspr SPRN_DBAT4U,r10
1095 mtspr SPRN_DBAT4L,r10
1096 mtspr SPRN_DBAT5U,r10
1097 mtspr SPRN_DBAT5L,r10
1098 mtspr SPRN_DBAT6U,r10
1099 mtspr SPRN_DBAT6L,r10
1100 mtspr SPRN_DBAT7U,r10
1101 mtspr SPRN_DBAT7L,r10
1102 mtspr SPRN_IBAT4U,r10
1103 mtspr SPRN_IBAT4L,r10
1104 mtspr SPRN_IBAT5U,r10
1105 mtspr SPRN_IBAT5L,r10
1106 mtspr SPRN_IBAT6U,r10
1107 mtspr SPRN_IBAT6L,r10
1108 mtspr SPRN_IBAT7U,r10
1109 mtspr SPRN_IBAT7L,r10
1110 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1115 1: addic. r10, r10, -0x1000
1122 addi r4, r3, __after_mmu_off - _start
1124 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1133 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1134 * (we keep one for debugging) and on others, we use one 256M BAT.
1137 lis r11,PAGE_OFFSET@h
1139 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1142 ori r11,r11,4 /* set up BAT registers for 601 */
1143 li r8,0x7f /* valid, block length = 8MB */
1144 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1145 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1146 addis r11,r11,0x800000@h
1147 addis r8,r8,0x800000@h
1148 mtspr SPRN_IBAT1U,r11
1149 mtspr SPRN_IBAT1L,r8
1150 addis r11,r11,0x800000@h
1151 addis r8,r8,0x800000@h
1152 mtspr SPRN_IBAT2U,r11
1153 mtspr SPRN_IBAT2L,r8
1159 ori r8,r8,0x12 /* R/W access, M=1 */
1161 ori r8,r8,2 /* R/W access */
1162 #endif /* CONFIG_SMP */
1163 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1165 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1166 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1167 mtspr SPRN_IBAT0L,r8
1168 mtspr SPRN_IBAT0U,r11
1173 #ifdef CONFIG_BOOTX_TEXT
1176 * setup the display bat prepared for us in prom.c
1181 addis r8,r3,disp_BAT@ha
1182 addi r8,r8,disp_BAT@l
1188 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1191 mtspr SPRN_DBAT3L,r8
1192 mtspr SPRN_DBAT3U,r11
1194 1: mtspr SPRN_IBAT3L,r8
1195 mtspr SPRN_IBAT3U,r11
1197 #endif /* CONFIG_BOOTX_TEXT */
1199 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1203 mtspr SPRN_DBAT1L, r8
1206 ori r11, r11, (BL_1M << 2) | 2
1207 mtspr SPRN_DBAT1U, r11
1212 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1214 /* prepare a BAT for early io */
1215 #if defined(CONFIG_GAMECUBE)
1217 #elif defined(CONFIG_WII)
1220 #error Invalid platform for USB Gecko based early debugging.
1223 * The virtual address used must match the virtual address
1224 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1226 lis r11, 0xfffe /* top 128K */
1227 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1228 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1229 mtspr SPRN_DBAT1L, r8
1230 mtspr SPRN_DBAT1U, r11
1235 /* Jump into the system reset for the rom.
1236 * We first disable the MMU, and then jump to the ROM reset address.
1238 * r3 is the board info structure, r4 is the location for starting.
1239 * I use this for building a small kernel that can load other kernels,
1240 * rather than trying to write or rely on a rom monitor that can tftp load.
1245 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1249 mfspr r11, SPRN_HID0
1251 ori r10,r10,HID0_ICE|HID0_DCE
1253 mtspr SPRN_HID0, r11
1255 li r5, MSR_ME|MSR_RI
1257 addis r6,r6,-KERNELBASE@h
1271 * We put a few things here that have to be page-aligned.
1272 * This stuff goes at the beginning of the data segment,
1273 * which is page-aligned.
1278 .globl empty_zero_page
1281 EXPORT_SYMBOL(empty_zero_page)
1283 .globl swapper_pg_dir
1285 .space PGD_TABLE_SIZE
1287 .globl intercept_table
1289 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1290 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1291 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1292 .long 0, 0, 0, 0, 0, 0, 0, 0
1293 .long 0, 0, 0, 0, 0, 0, 0, 0
1294 .long 0, 0, 0, 0, 0, 0, 0, 0
1295 EXPORT_SYMBOL(intercept_table)
1297 /* Room for two PTE pointers, usually the kernel and current user pointers
1298 * to their respective root page table.