2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/book3s/64/mmu-hash.h>
29 * Use unused space in the interrupt stack to save and restore
30 * registers for winkle support.
43 #define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
44 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
50 * Used by threads before entering deep idle states. Saves SPRs
51 * in interrupt stack frame
55 * Note all register i.e per-core, per-subcore or per-thread is saved
56 * here since any thread in the core might wake up first
62 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
68 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * Used by threads when the lock bit of core_idle_state is set.
90 * Threads will spin in HMT_LOW until the lock bit is cleared.
91 * r14 - pointer to core_idle_state
92 * r15 - used to load contents of core_idle_state
98 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
105 * Pass requested state in r3:
106 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
107 * - Requested STOP state in POWER9
109 * To check IRQ_HAPPENED in r4
113 * Address to 'rfid' to in r5
115 _GLOBAL(pnv_powersave_common)
116 /* Use r3 to pass state nap/sleep/winkle */
117 /* NAP is a state loss, we create a regs frame on the
118 * stack, fill it up with the state we care about and
119 * stick a pointer to it in PACAR1. We really only
120 * need to save PC, some CR bits and the NV GPRs,
121 * but for now an interrupt frame will do.
125 stdu r1,-INT_FRAME_SIZE(r1)
129 /* Hard disable interrupts */
133 mtmsrd r9,1 /* hard-disable interrupts */
135 /* Check if something happened while soft-disabled */
136 lbz r0,PACAIRQHAPPENED(r13)
137 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
141 addi r1,r1,INT_FRAME_SIZE
143 li r3,0 /* Return 0 (no nap) */
147 1: /* We mark irqs hard disabled as this is the state we'll
148 * be in when returning and we need to tell arch_local_irq_restore()
151 li r0,PACA_IRQ_HARD_DIS
152 stb r0,PACAIRQHAPPENED(r13)
154 /* We haven't lost state ... yet */
156 stb r0,PACA_NAPSTATELOST(r13)
158 /* Continue saving state */
167 * Go to real mode to do the nap, as required by the architecture.
168 * Also, we need to be in real mode before setting hwthread_state,
169 * because as soon as we do that, another thread can switch
170 * the MMU context to the guest.
172 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
175 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
180 .globl pnv_enter_arch207_idle_mode
181 pnv_enter_arch207_idle_mode:
182 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
183 /* Tell KVM we're entering idle */
184 li r4,KVM_HWTHREAD_IN_IDLE
185 /******************************************************/
186 /* N O T E W E L L ! ! ! N O T E W E L L */
187 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
188 /* MUST occur in real mode, i.e. with the MMU off, */
189 /* and the MMU must stay off until we clear this flag */
190 /* and test HSTATE_HWTHREAD_REQ(r13) in the system */
191 /* reset interrupt vector in exceptions-64s.S. */
192 /* The reason is that another thread can switch the */
193 /* MMU to a guest context whenever this flag is set */
194 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
195 /* that would potentially cause this thread to start */
196 /* executing instructions from guest memory in */
197 /* hypervisor mode, leading to a host crash or data */
198 /* corruption, or worse. */
199 /******************************************************/
200 stb r4,HSTATE_HWTHREAD_STATE(r13)
202 stb r3,PACA_THREAD_IDLE_STATE(r13)
203 cmpwi cr3,r3,PNV_THREAD_SLEEP
205 IDLE_STATE_ENTER_SEQ(PPC_NAP)
208 /* Sleep or winkle */
209 lbz r7,PACA_THREAD_MASK(r13)
210 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
214 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
215 bnel core_idle_lock_held
217 andc r15,r15,r7 /* Clear thread bit */
219 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
222 * If cr0 = 0, then current thread is the last thread of the core entering
223 * sleep. Last thread needs to execute the hardware bug workaround code if
224 * required by the platform.
225 * Make the workaround call unconditionally here. The below branch call is
226 * patched out when the idle states are discovered if the platform does not
229 .global pnv_fastsleep_workaround_at_entry
230 pnv_fastsleep_workaround_at_entry:
231 beq fastsleep_workaround_at_entry
237 common_enter: /* common code for all the threads entering sleep or winkle */
239 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
241 fastsleep_workaround_at_entry:
242 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
247 /* Fast sleep workaround */
250 bl opal_rm_config_cpu_idle_state
259 bl save_sprs_to_stack
261 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
264 * r3 - requested stop state
267 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
268 /* Tell KVM we're entering idle */
269 li r4,KVM_HWTHREAD_IN_IDLE
270 /* DO THIS IN REAL MODE! See comment above. */
271 stb r4,HSTATE_HWTHREAD_STATE(r13)
274 * Check if the requested state is a deep idle state.
276 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
277 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
280 IDLE_STATE_ENTER_SEQ(PPC_STOP)
283 * Entering deep idle state.
284 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
285 * stack and enter stop
287 lbz r7,PACA_THREAD_MASK(r13)
288 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
292 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
293 bnel core_idle_lock_held
294 andc r15,r15,r7 /* Clear thread bit */
300 bl save_sprs_to_stack
302 IDLE_STATE_ENTER_SEQ(PPC_STOP)
305 /* Now check if user or arch enabled NAP mode */
306 LOAD_REG_ADDRBASE(r3,powersave_nap)
307 lwz r4,ADDROFF(powersave_nap)(r3)
316 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
317 b pnv_powersave_common
320 _GLOBAL(power7_sleep)
321 li r3,PNV_THREAD_SLEEP
323 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
324 b pnv_powersave_common
327 _GLOBAL(power7_winkle)
328 li r3,PNV_THREAD_WINKLE
330 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
331 b pnv_powersave_common
334 #define CHECK_HMI_INTERRUPT \
335 mfspr r0,SPRN_SRR1; \
336 BEGIN_FTR_SECTION_NESTED(66); \
337 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
338 FTR_SECTION_ELSE_NESTED(66); \
339 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
340 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
341 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
343 /* Invoke opal call to handle hmi */ \
344 ld r2,PACATOC(r13); \
346 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
347 li r3,0; /* NULL argument */ \
348 bl hmi_exception_realmode; \
350 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
355 * r3 - requested stop state
357 _GLOBAL(power9_idle_stop)
358 LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
362 LOAD_REG_ADDR(r5,power_enter_stop)
363 b pnv_powersave_common
366 * Called from reset vector. Check whether we have woken up with
367 * hypervisor state loss. If yes, restore hypervisor state and return
368 * back to reset vector.
370 * r13 - Contents of HSPRG0
371 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
373 _GLOBAL(pnv_restore_hyp_resource)
377 * POWER ISA 3. Use PSSCR to determine if we
378 * are waking up from deep idle state
380 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
381 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
385 * 0-3 bits correspond to Power-Saving Level Status
386 * which indicates the idle state we are waking up from
390 bge cr4,pnv_wakeup_tb_loss
392 * Waking up without hypervisor state loss. Return to
397 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
400 * POWER ISA 2.07 or less.
401 * Check if last bit of HSPGR0 is set. This indicates whether we are
402 * waking up from winkle.
407 /* Now that we are sure r13 is corrected, load TOC */
410 mtspr SPRN_HSPRG0,r13
412 lbz r0,PACA_THREAD_IDLE_STATE(r13)
413 cmpwi cr2,r0,PNV_THREAD_NAP
414 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
417 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
418 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
419 * indicates we are waking with hypervisor state loss from nap.
423 blr /* Return back to System Reset vector from where
424 pnv_restore_hyp_resource was invoked */
427 * Called if waking up from idle state which can cause either partial or
428 * complete hyp state loss.
429 * In POWER8, called if waking up from fastsleep or winkle
430 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
433 * cr3 - gt if waking up with partial/complete hypervisor state loss
434 * cr4 - gt or eq if waking up from complete hypervisor state loss.
436 _GLOBAL(pnv_wakeup_tb_loss)
439 * Before entering any idle state, the NVGPRs are saved in the stack
440 * and they are restored before switching to the process context. Hence
441 * until they are restored, they are free to be used.
443 * Save SRR1 and LR in NVGPRs as they might be clobbered in
444 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
445 * to determine the wakeup reason if we branch to kvm_start_guest. LR
446 * is required to return back to reset vector after hypervisor state
447 * restore is complete.
453 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
455 lbz r7,PACA_THREAD_MASK(r13)
456 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
459 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
461 * Lock bit is set in one of the 2 cases-
462 * a. In the sleep/winkle enter path, the last thread is executing
463 * fastsleep workaround code.
464 * b. In the wake up path, another thread is executing fastsleep
465 * workaround undo code or resyncing timebase or restoring context
466 * In either case loop until the lock bit is cleared.
468 bnel core_idle_lock_held
474 * cr2 - eq if first thread to wakeup in core
475 * cr3- gt if waking up with partial/complete hypervisor state loss
476 * cr4 - gt or eq if waking up from complete hypervisor state loss.
479 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
485 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
487 cmpwi r4,0 /* Check if first in subcore */
489 or r15,r15,r7 /* Set thread bit */
490 beq first_thread_in_subcore
491 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
493 or r15,r15,r7 /* Set thread bit */
494 beq cr2,first_thread_in_core
496 /* Not first thread in core or subcore to wake up */
499 first_thread_in_subcore:
501 * If waking up from sleep, subcore state is not lost. Hence
502 * skip subcore state restore
504 blt cr4,subcore_state_restored
506 /* Restore per-subcore state */
515 subcore_state_restored:
517 * Check if the thread is also the first thread in the core. If not,
518 * skip to clear_lock.
522 first_thread_in_core:
525 * First thread in the core waking up from any state which can cause
526 * partial or complete hypervisor state loss. It needs to
527 * call the fastsleep workaround code if the platform requires it.
528 * Call it unconditionally here. The below branch instruction will
529 * be patched out if the platform does not have fastsleep or does not
530 * require the workaround. Patching will be performed during the
531 * discovery of idle-states.
533 .global pnv_fastsleep_workaround_at_exit
534 pnv_fastsleep_workaround_at_exit:
535 b fastsleep_workaround_at_exit
539 * Use cr3 which indicates that we are waking up with atleast partial
540 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
543 /* Time base re-sync */
544 bl opal_rm_resync_timebase;
546 * If waking up from sleep, per core state is not lost, skip to
552 * First thread in the core to wake up and its waking up with
553 * complete hypervisor state loss. Restore per core hypervisor
561 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
569 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
575 * Common to all threads.
577 * If waking up from sleep, hypervisor state is not lost. Hence
578 * skip hypervisor state restore.
580 blt cr4,hypervisor_state_restored
582 /* Waking up from winkle */
584 BEGIN_MMU_FTR_SECTION
586 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
587 /* Restore SLB from PACA */
588 ld r8,PACA_SLBSHADOWPTR(r13)
591 li r3, SLBSHADOW_SAVEAREA
595 andis. r7,r5,SLB_ESID_V@h
602 /* Restore per thread state */
613 /* Call cur_cpu_spec->cpu_restore() */
614 LOAD_REG_ADDR(r4, cur_cpu_spec)
616 ld r12,CPU_SPEC_RESTORE(r4)
617 #ifdef PPC64_ELF_ABI_v1
623 hypervisor_state_restored:
627 blr /* Return back to System Reset vector from where
628 pnv_restore_hyp_resource was invoked */
630 fastsleep_workaround_at_exit:
633 bl opal_rm_config_cpu_idle_state
637 * R3 here contains the value that will be returned to the caller
640 _GLOBAL(pnv_wakeup_loss)
644 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
650 addi r1,r1,INT_FRAME_SIZE
657 * R3 here contains the value that will be returned to the caller
660 _GLOBAL(pnv_wakeup_noloss)
661 lbz r0,PACA_NAPSTATELOST(r13)
666 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
671 addi r1,r1,INT_FRAME_SIZE