2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/sys.h>
18 #include <asm/unistd.h>
19 #include <asm/errno.h>
20 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/cputable.h>
26 #include <asm/thread_info.h>
27 #include <asm/kexec.h>
28 #include <asm/ptrace.h>
30 #include <asm/export.h>
34 _GLOBAL(call_do_softirq)
37 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
48 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
58 .tc ppc64_caches[TC],ppc64_caches
62 * Write any modified data cache blocks out to memory
63 * and invalidate the corresponding instruction cache blocks.
65 * flush_icache_range(unsigned long start, unsigned long stop)
67 * flush all bytes from start through stop-1 inclusive
70 _KPROBE(flush_icache_range)
74 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
76 * Flush the data cache to memory
78 * Different systems have different cache line sizes
79 * and in some cases i-cache and d-cache line sizes differ from
82 ld r10,PPC64_CACHES@toc(r2)
83 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
85 andc r6,r3,r5 /* round low to line bdy */
86 subf r8,r6,r4 /* compute length */
87 add r8,r8,r5 /* ensure we get enough */
88 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
89 srw. r8,r8,r9 /* compute line count */
90 beqlr /* nothing to do? */
97 /* Now invalidate the instruction cache */
99 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
101 andc r6,r3,r5 /* round low to line bdy */
102 subf r8,r6,r4 /* compute length */
104 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
105 srw. r8,r8,r9 /* compute line count */
106 beqlr /* nothing to do? */
114 EXPORT_SYMBOL(flush_icache_range)
116 * Like above, but only do the D-cache.
118 * flush_dcache_range(unsigned long start, unsigned long stop)
120 * flush all bytes from start to stop-1 inclusive
122 _GLOBAL(flush_dcache_range)
125 * Flush the data cache to memory
127 * Different systems have different cache line sizes
129 ld r10,PPC64_CACHES@toc(r2)
130 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
132 andc r6,r3,r5 /* round low to line bdy */
133 subf r8,r6,r4 /* compute length */
134 add r8,r8,r5 /* ensure we get enough */
135 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
136 srw. r8,r8,r9 /* compute line count */
137 beqlr /* nothing to do? */
144 EXPORT_SYMBOL(flush_dcache_range)
147 * Like above, but works on non-mapped physical addresses.
148 * Use only for non-LPAR setups ! It also assumes real mode
149 * is cacheable. Used for flushing out the DART before using
150 * it as uncacheable memory
152 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
154 * flush all bytes from start to stop-1 inclusive
156 _GLOBAL(flush_dcache_phys_range)
157 ld r10,PPC64_CACHES@toc(r2)
158 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
160 andc r6,r3,r5 /* round low to line bdy */
161 subf r8,r6,r4 /* compute length */
162 add r8,r8,r5 /* ensure we get enough */
163 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
164 srw. r8,r8,r9 /* compute line count */
165 beqlr /* nothing to do? */
166 mfmsr r5 /* Disable MMU Data Relocation */
179 mtmsr r5 /* Re-enable MMU Data Relocation */
184 _GLOBAL(flush_inval_dcache_range)
185 ld r10,PPC64_CACHES@toc(r2)
186 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
188 andc r6,r3,r5 /* round low to line bdy */
189 subf r8,r6,r4 /* compute length */
190 add r8,r8,r5 /* ensure we get enough */
191 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
192 srw. r8,r8,r9 /* compute line count */
193 beqlr /* nothing to do? */
206 * Flush a particular page from the data cache to RAM.
207 * Note: this is necessary because the instruction cache does *not*
208 * snoop from the data cache.
210 * void __flush_dcache_icache(void *page)
212 _GLOBAL(__flush_dcache_icache)
214 * Flush the data cache to memory
216 * Different systems have different cache line sizes
222 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
224 /* Flush the dcache */
225 ld r7,PPC64_CACHES@toc(r2)
226 clrrdi r3,r3,PAGE_SHIFT /* Page align */
227 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
228 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
236 /* Now invalidate the icache */
238 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
239 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
248 EXPORT_SYMBOL(__bswapdi2)
250 rlwinm r7,r3,8,0xffffffff
252 rlwinm r9,r8,8,0xffffffff
253 rlwimi r7,r3,24,16,23
255 rlwimi r9,r8,24,16,23
261 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
291 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
293 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
296 * Do an IO access in real mode
327 * Do an IO access in real mode
356 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
358 #ifdef CONFIG_PPC_PASEMI
360 _GLOBAL(real_205_readb)
375 _GLOBAL(real_205_writeb)
390 #endif /* CONFIG_PPC_PASEMI */
393 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
395 * SCOM access functions for 970 (FX only for now)
397 * unsigned long scom970_read(unsigned int address);
398 * void scom970_write(unsigned int address, unsigned long value);
400 * The address passed in is the 24 bits register address. This code
401 * is 970 specific and will not check the status bits, so you should
402 * know what you are doing.
404 _GLOBAL(scom970_read)
411 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
412 * (including parity). On current CPUs they must be 0'd,
413 * and finally or in RW bit
418 /* do the actual scom read */
427 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
428 * that's the best we can do). Not implemented yet as we don't use
429 * the scom on any of the bogus CPUs yet, but may have to be done
433 /* restore interrupts */
438 _GLOBAL(scom970_write)
445 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
446 * (including parity). On current CPUs they must be 0'd.
452 mtspr SPRN_SCOMD,r4 /* write data */
454 mtspr SPRN_SCOMC,r3 /* write command */
459 /* restore interrupts */
462 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
464 /* kexec_wait(phys_cpu)
466 * wait for the flag to change, indicating this kernel is going away but
467 * the slave code for the next one is at addresses 0 to 100.
469 * This is used by all slaves, even those that did not find a matching
470 * paca in the secondary startup code.
472 * Physical (hardware) cpu id should be in r3.
477 addi r5,r5,kexec_flag-1b
480 #ifdef CONFIG_KEXEC /* use no memory without kexec */
484 #ifdef CONFIG_PPC_BOOK3S_64
487 clrrdi r11,r11,1 /* Clear MSR_LE */
492 /* Create TLB entry in book3e_secondary_core_init */
498 /* this can be in text because we won't change it until we are
499 * running in real anyways
506 #ifdef CONFIG_PPC_BOOK3E
508 * BOOK3E has no real MMU mode, so we have to setup the initial TLB
509 * for a core to identity map v:0 to p:0. This current implementation
510 * assumes that 1G is enough for kexec.
514 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
515 * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
521 mfspr r10,SPRN_TLB1CFG
522 andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
523 subi r10,r10,1 /* Last entry: no conflict with kernel text */
524 lis r9,MAS0_TLBSEL(1)@h
525 rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
527 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
528 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
529 #define M_IF_NEEDED MAS2_M
531 #define M_IF_NEEDED 0
535 lis r9,(MAS1_VALID|MAS1_IPROT)@h
536 ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
539 LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
542 LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
552 /* kexec_smp_wait(void)
554 * call with interrupts off
555 * note: this is a terminal routine, it does not save lr
557 * get phys id from paca
558 * switch to real mode
559 * mark the paca as no longer used
560 * join other cpus in kexec_wait(phys_id)
562 _GLOBAL(kexec_smp_wait)
563 lhz r3,PACAHWCPUID(r13)
566 li r4,KEXEC_STATE_REAL_MODE
567 stb r4,PACAKEXECSTATE(r13)
573 * switch to real mode (turn mmu off)
574 * we use the early kernel trick that the hardware ignores bits
575 * 0 and 1 (big endian) of the effective address in real mode
577 * don't overwrite r3 here, it is live for kexec_wait above.
579 real_mode: /* assume normal blr return */
580 #ifdef CONFIG_PPC_BOOK3E
581 /* Create an identity mapping. */
586 mflr r11 /* return address to SRR0 */
598 * kexec_sequence(newstack, start, image, control, clear_all())
600 * does the grungy work with stack switching and real mode switches
601 * also does simple calls to other code
604 _GLOBAL(kexec_sequence)
608 /* switch stacks to newstack -- &kexec_stack.stack */
609 stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
615 /* save regs for local vars on new stack.
616 * yes, we won't go back, but ...
626 stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
628 /* save args into preserved regs */
629 mr r31,r3 /* newstack (both) */
630 mr r30,r4 /* start (real) */
631 mr r29,r5 /* image (virt) */
632 mr r28,r6 /* control, unused */
633 mr r27,r7 /* clear_all() fn desc */
634 mr r26,r8 /* spare */
635 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
637 /* disable interrupts, we are overwriting kernel data next */
638 #ifdef CONFIG_PPC_BOOK3E
646 /* copy dest pages, flush whole dest image */
648 bl kexec_copy_flush /* (image) */
653 /* copy 0x100 bytes starting at start to 0 */
655 mr r4,r30 /* start, aka phys mem offset */
658 bl copy_and_flush /* (dest, src, copy limit, start offset) */
659 1: /* assume normal blr return */
661 /* release other cpus to the new kernel secondary start at 0x60 */
664 stw r6,kexec_flag-1b(5)
666 #ifndef CONFIG_PPC_BOOK3E
667 /* clear out hardware hash page table and tlb */
668 #ifdef PPC64_ELF_ABI_v1
669 ld r12,0(r27) /* deref function descriptor */
674 bctrl /* mmu_hash_ops.hpte_clear_all(void); */
675 #endif /* !CONFIG_PPC_BOOK3E */
678 * kexec image calling is:
679 * the first 0x100 bytes of the entry point are copied to 0
681 * all slaves branch to slave = 0x60 (absolute)
682 * slave(phys_cpu_id);
684 * master goes to start = entry point
685 * start(phys_cpu_id, start, 0);
688 * a wrapper is needed to call existing kernels, here is an approximate
689 * description of one method:
692 * start will be near the boot_block (maybe 0x100 bytes before it?)
693 * it will have a 0x60, which will b to boot_block, where it will wait
694 * and 0 will store phys into struct boot-block and load r3 from there,
695 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
698 * boot block will have all cpus scanning device tree to see if they
699 * are the boot cpu ?????
700 * other device tree differences (prop sizes, va vs pa, etc)...
702 mr r3,r25 # my phys cpu
703 mr r4,r30 # start, aka phys mem offset
706 blr /* image->start(physid, image->start, 0); */
707 #endif /* CONFIG_KEXEC */