arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 unsigned long msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128
 129         return newmsr;
 130 }
 131
 132 void __msr_check_and_clear(unsigned long bits)
 133 {
 134         unsigned long oldmsr = mfmsr();
 135         unsigned long newmsr;
 136
 137         newmsr = oldmsr & ~bits;
 138
 139 #ifdef CONFIG_VSX
 140         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 141                 newmsr &= ~MSR_VSX;
 142 #endif
 143
 144         if (oldmsr != newmsr)
 145                 mtmsr_isync(newmsr);
 146 }
 147 EXPORT_SYMBOL(__msr_check_and_clear);
 148
 149 #ifdef CONFIG_PPC_FPU
 150 void __giveup_fpu(struct task_struct *tsk)
 151 {
 152         unsigned long msr;
 153
 154         save_fpu(tsk);
 155         msr = tsk->thread.regs->msr;
 156         msr &= ~MSR_FP;
 157 #ifdef CONFIG_VSX
 158         if (cpu_has_feature(CPU_FTR_VSX))
 159                 msr &= ~MSR_VSX;
 160 #endif
 161         tsk->thread.regs->msr = msr;
 162 }
 163
 164 void giveup_fpu(struct task_struct *tsk)
 165 {
 166         check_if_tm_restore_required(tsk);
 167
 168         msr_check_and_set(MSR_FP);
 169         __giveup_fpu(tsk);
 170         msr_check_and_clear(MSR_FP);
 171 }
 172 EXPORT_SYMBOL(giveup_fpu);
 173
 174 /*
 175  * Make sure the floating-point register state in the
 176  * the thread_struct is up to date for task tsk.
 177  */
 178 void flush_fp_to_thread(struct task_struct *tsk)
 179 {
 180         if (tsk->thread.regs) {
 181                 /*
 182                  * We need to disable preemption here because if we didn't,
 183                  * another process could get scheduled after the regs->msr
 184                  * test but before we have finished saving the FP registers
 185                  * to the thread_struct.  That process could take over the
 186                  * FPU, and then when we get scheduled again we would store
 187                  * bogus values for the remaining FP registers.
 188                  */
 189                 preempt_disable();
 190                 if (tsk->thread.regs->msr & MSR_FP) {
 191                         /*
 192                          * This should only ever be called for current or
 193                          * for a stopped child process.  Since we save away
 194                          * the FP register state on context switch,
 195                          * there is something wrong if a stopped child appears
 196                          * to still have its FP state in the CPU registers.
 197                          */
 198                         BUG_ON(tsk != current);
 199                         giveup_fpu(tsk);
 200                 }
 201                 preempt_enable();
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 205
 206 void enable_kernel_fp(void)
 207 {
 208         WARN_ON(preemptible());
 209
 210         msr_check_and_set(MSR_FP);
 211
 212         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 213                 check_if_tm_restore_required(current);
 214                 __giveup_fpu(current);
 215         }
 216 }
 217 EXPORT_SYMBOL(enable_kernel_fp);
 218
 219 static int restore_fp(struct task_struct *tsk) {
 220         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 221                 load_fp_state(&current->thread.fp_state);
 222                 current->thread.load_fp++;
 223                 return 1;
 224         }
 225         return 0;
 226 }
 227 #else
 228 static int restore_fp(struct task_struct *tsk) { return 0; }
 229 #endif /* CONFIG_PPC_FPU */
 230
 231 #ifdef CONFIG_ALTIVEC
 232 #define loadvec(thr) ((thr).load_vec)
 233
 234 static void __giveup_altivec(struct task_struct *tsk)
 235 {
 236         unsigned long msr;
 237
 238         save_altivec(tsk);
 239         msr = tsk->thread.regs->msr;
 240         msr &= ~MSR_VEC;
 241 #ifdef CONFIG_VSX
 242         if (cpu_has_feature(CPU_FTR_VSX))
 243                 msr &= ~MSR_VSX;
 244 #endif
 245         tsk->thread.regs->msr = msr;
 246 }
 247
 248 void giveup_altivec(struct task_struct *tsk)
 249 {
 250         check_if_tm_restore_required(tsk);
 251
 252         msr_check_and_set(MSR_VEC);
 253         __giveup_altivec(tsk);
 254         msr_check_and_clear(MSR_VEC);
 255 }
 256 EXPORT_SYMBOL(giveup_altivec);
 257
 258 void enable_kernel_altivec(void)
 259 {
 260         WARN_ON(preemptible());
 261
 262         msr_check_and_set(MSR_VEC);
 263
 264         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 265                 check_if_tm_restore_required(current);
 266                 __giveup_altivec(current);
 267         }
 268 }
 269 EXPORT_SYMBOL(enable_kernel_altivec);
 270
 271 /*
 272  * Make sure the VMX/Altivec register state in the
 273  * the thread_struct is up to date for task tsk.
 274  */
 275 void flush_altivec_to_thread(struct task_struct *tsk)
 276 {
 277         if (tsk->thread.regs) {
 278                 preempt_disable();
 279                 if (tsk->thread.regs->msr & MSR_VEC) {
 280                         BUG_ON(tsk != current);
 281                         giveup_altivec(tsk);
 282                 }
 283                 preempt_enable();
 284         }
 285 }
 286 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 287
 288 static int restore_altivec(struct task_struct *tsk)
 289 {
 290         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 291                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 292                 load_vr_state(&tsk->thread.vr_state);
 293                 tsk->thread.used_vr = 1;
 294                 tsk->thread.load_vec++;
 295
 296                 return 1;
 297         }
 298         return 0;
 299 }
 300 #else
 301 #define loadvec(thr) 0
 302 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 303 #endif /* CONFIG_ALTIVEC */
 304
 305 #ifdef CONFIG_VSX
 306 static void __giveup_vsx(struct task_struct *tsk)
 307 {
 308         if (tsk->thread.regs->msr & MSR_FP)
 309                 __giveup_fpu(tsk);
 310         if (tsk->thread.regs->msr & MSR_VEC)
 311                 __giveup_altivec(tsk);
 312         tsk->thread.regs->msr &= ~MSR_VSX;
 313 }
 314
 315 static void giveup_vsx(struct task_struct *tsk)
 316 {
 317         check_if_tm_restore_required(tsk);
 318
 319         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 320         __giveup_vsx(tsk);
 321         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 322 }
 323
 324 static void save_vsx(struct task_struct *tsk)
 325 {
 326         if (tsk->thread.regs->msr & MSR_FP)
 327                 save_fpu(tsk);
 328         if (tsk->thread.regs->msr & MSR_VEC)
 329                 save_altivec(tsk);
 330 }
 331
 332 void enable_kernel_vsx(void)
 333 {
 334         WARN_ON(preemptible());
 335
 336         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 337
 338         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 339                 check_if_tm_restore_required(current);
 340                 if (current->thread.regs->msr & MSR_FP)
 341                         __giveup_fpu(current);
 342                 if (current->thread.regs->msr & MSR_VEC)
 343                         __giveup_altivec(current);
 344                 __giveup_vsx(current);
 345         }
 346 }
 347 EXPORT_SYMBOL(enable_kernel_vsx);
 348
 349 void flush_vsx_to_thread(struct task_struct *tsk)
 350 {
 351         if (tsk->thread.regs) {
 352                 preempt_disable();
 353                 if (tsk->thread.regs->msr & MSR_VSX) {
 354                         BUG_ON(tsk != current);
 355                         giveup_vsx(tsk);
 356                 }
 357                 preempt_enable();
 358         }
 359 }
 360 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 361
 362 static int restore_vsx(struct task_struct *tsk)
 363 {
 364         if (cpu_has_feature(CPU_FTR_VSX)) {
 365                 tsk->thread.used_vsr = 1;
 366                 return 1;
 367         }
 368
 369         return 0;
 370 }
 371 #else
 372 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 373 static inline void save_vsx(struct task_struct *tsk) { }
 374 #endif /* CONFIG_VSX */
 375
 376 #ifdef CONFIG_SPE
 377 void giveup_spe(struct task_struct *tsk)
 378 {
 379         check_if_tm_restore_required(tsk);
 380
 381         msr_check_and_set(MSR_SPE);
 382         __giveup_spe(tsk);
 383         msr_check_and_clear(MSR_SPE);
 384 }
 385 EXPORT_SYMBOL(giveup_spe);
 386
 387 void enable_kernel_spe(void)
 388 {
 389         WARN_ON(preemptible());
 390
 391         msr_check_and_set(MSR_SPE);
 392
 393         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 394                 check_if_tm_restore_required(current);
 395                 __giveup_spe(current);
 396         }
 397 }
 398 EXPORT_SYMBOL(enable_kernel_spe);
 399
 400 void flush_spe_to_thread(struct task_struct *tsk)
 401 {
 402         if (tsk->thread.regs) {
 403                 preempt_disable();
 404                 if (tsk->thread.regs->msr & MSR_SPE) {
 405                         BUG_ON(tsk != current);
 406                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 407                         giveup_spe(tsk);
 408                 }
 409                 preempt_enable();
 410         }
 411 }
 412 #endif /* CONFIG_SPE */
 413
 414 static unsigned long msr_all_available;
 415
 416 static int __init init_msr_all_available(void)
 417 {
 418 #ifdef CONFIG_PPC_FPU
 419         msr_all_available |= MSR_FP;
 420 #endif
 421 #ifdef CONFIG_ALTIVEC
 422         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 423                 msr_all_available |= MSR_VEC;
 424 #endif
 425 #ifdef CONFIG_VSX
 426         if (cpu_has_feature(CPU_FTR_VSX))
 427                 msr_all_available |= MSR_VSX;
 428 #endif
 429 #ifdef CONFIG_SPE
 430         if (cpu_has_feature(CPU_FTR_SPE))
 431                 msr_all_available |= MSR_SPE;
 432 #endif
 433
 434         return 0;
 435 }
 436 early_initcall(init_msr_all_available);
 437
 438 void giveup_all(struct task_struct *tsk)
 439 {
 440         unsigned long usermsr;
 441
 442         if (!tsk->thread.regs)
 443                 return;
 444
 445         usermsr = tsk->thread.regs->msr;
 446
 447         if ((usermsr & msr_all_available) == 0)
 448                 return;
 449
 450         msr_check_and_set(msr_all_available);
 451         check_if_tm_restore_required(tsk);
 452
 453 #ifdef CONFIG_PPC_FPU
 454         if (usermsr & MSR_FP)
 455                 __giveup_fpu(tsk);
 456 #endif
 457 #ifdef CONFIG_ALTIVEC
 458         if (usermsr & MSR_VEC)
 459                 __giveup_altivec(tsk);
 460 #endif
 461 #ifdef CONFIG_VSX
 462         if (usermsr & MSR_VSX)
 463                 __giveup_vsx(tsk);
 464 #endif
 465 #ifdef CONFIG_SPE
 466         if (usermsr & MSR_SPE)
 467                 __giveup_spe(tsk);
 468 #endif
 469
 470         msr_check_and_clear(msr_all_available);
 471 }
 472 EXPORT_SYMBOL(giveup_all);
 473
 474 void restore_math(struct pt_regs *regs)
 475 {
 476         unsigned long msr;
 477
 478         if (!msr_tm_active(regs->msr) &&
 479                 !current->thread.load_fp && !loadvec(current->thread))
 480                 return;
 481
 482         msr = regs->msr;
 483         msr_check_and_set(msr_all_available);
 484
 485         /*
 486          * Only reload if the bit is not set in the user MSR, the bit BEING set
 487          * indicates that the registers are hot
 488          */
 489         if ((!(msr & MSR_FP)) && restore_fp(current))
 490                 msr |= MSR_FP | current->thread.fpexc_mode;
 491
 492         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 493                 msr |= MSR_VEC;
 494
 495         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 496                         restore_vsx(current)) {
 497                 msr |= MSR_VSX;
 498         }
 499
 500         msr_check_and_clear(msr_all_available);
 501
 502         regs->msr = msr;
 503 }
 504
 505 void save_all(struct task_struct *tsk)
 506 {
 507         unsigned long usermsr;
 508
 509         if (!tsk->thread.regs)
 510                 return;
 511
 512         usermsr = tsk->thread.regs->msr;
 513
 514         if ((usermsr & msr_all_available) == 0)
 515                 return;
 516
 517         msr_check_and_set(msr_all_available);
 518
 519         /*
 520          * Saving the way the register space is in hardware, save_vsx boils
 521          * down to a save_fpu() and save_altivec()
 522          */
 523         if (usermsr & MSR_VSX) {
 524                 save_vsx(tsk);
 525         } else {
 526                 if (usermsr & MSR_FP)
 527                         save_fpu(tsk);
 528
 529                 if (usermsr & MSR_VEC)
 530                         save_altivec(tsk);
 531         }
 532
 533         if (usermsr & MSR_SPE)
 534                 __giveup_spe(tsk);
 535
 536         msr_check_and_clear(msr_all_available);
 537 }
 538
 539 void flush_all_to_thread(struct task_struct *tsk)
 540 {
 541         if (tsk->thread.regs) {
 542                 preempt_disable();
 543                 BUG_ON(tsk != current);
 544                 save_all(tsk);
 545
 546 #ifdef CONFIG_SPE
 547                 if (tsk->thread.regs->msr & MSR_SPE)
 548                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 549 #endif
 550
 551                 preempt_enable();
 552         }
 553 }
 554 EXPORT_SYMBOL(flush_all_to_thread);
 555
 556 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 557 void do_send_trap(struct pt_regs *regs, unsigned long address,
 558                   unsigned long error_code, int signal_code, int breakpt)
 559 {
 560         siginfo_t info;
 561
 562         current->thread.trap_nr = signal_code;
 563         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 564                         11, SIGSEGV) == NOTIFY_STOP)
 565                 return;
 566
 567         /* Deliver the signal to userspace */
 568         info.si_signo = SIGTRAP;
 569         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 570         info.si_code = signal_code;
 571         info.si_addr = (void __user *)address;
 572         force_sig_info(SIGTRAP, &info, current);
 573 }
 574 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 575 void do_break (struct pt_regs *regs, unsigned long address,
 576                     unsigned long error_code)
 577 {
 578         siginfo_t info;
 579
 580         current->thread.trap_nr = TRAP_HWBKPT;
 581         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 582                         11, SIGSEGV) == NOTIFY_STOP)
 583                 return;
 584
 585         if (debugger_break_match(regs))
 586                 return;
 587
 588         /* Clear the breakpoint */
 589         hw_breakpoint_disable();
 590
 591         /* Deliver the signal to userspace */
 592         info.si_signo = SIGTRAP;
 593         info.si_errno = 0;
 594         info.si_code = TRAP_HWBKPT;
 595         info.si_addr = (void __user *)address;
 596         force_sig_info(SIGTRAP, &info, current);
 597 }
 598 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 599
 600 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 601
 602 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 603 /*
 604  * Set the debug registers back to their default "safe" values.
 605  */
 606 static void set_debug_reg_defaults(struct thread_struct *thread)
 607 {
 608         thread->debug.iac1 = thread->debug.iac2 = 0;
 609 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 610         thread->debug.iac3 = thread->debug.iac4 = 0;
 611 #endif
 612         thread->debug.dac1 = thread->debug.dac2 = 0;
 613 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 614         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 615 #endif
 616         thread->debug.dbcr0 = 0;
 617 #ifdef CONFIG_BOOKE
 618         /*
 619          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 620          */
 621         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 622                         DBCR1_IAC3US | DBCR1_IAC4US;
 623         /*
 624          * Force Data Address Compare User/Supervisor bits to be User-only
 625          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 626          */
 627         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 628 #else
 629         thread->debug.dbcr1 = 0;
 630 #endif
 631 }
 632
 633 static void prime_debug_regs(struct debug_reg *debug)
 634 {
 635         /*
 636          * We could have inherited MSR_DE from userspace, since
 637          * it doesn't get cleared on exception entry.  Make sure
 638          * MSR_DE is clear before we enable any debug events.
 639          */
 640         mtmsr(mfmsr() & ~MSR_DE);
 641
 642         mtspr(SPRN_IAC1, debug->iac1);
 643         mtspr(SPRN_IAC2, debug->iac2);
 644 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 645         mtspr(SPRN_IAC3, debug->iac3);
 646         mtspr(SPRN_IAC4, debug->iac4);
 647 #endif
 648         mtspr(SPRN_DAC1, debug->dac1);
 649         mtspr(SPRN_DAC2, debug->dac2);
 650 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 651         mtspr(SPRN_DVC1, debug->dvc1);
 652         mtspr(SPRN_DVC2, debug->dvc2);
 653 #endif
 654         mtspr(SPRN_DBCR0, debug->dbcr0);
 655         mtspr(SPRN_DBCR1, debug->dbcr1);
 656 #ifdef CONFIG_BOOKE
 657         mtspr(SPRN_DBCR2, debug->dbcr2);
 658 #endif
 659 }
 660 /*
 661  * Unless neither the old or new thread are making use of the
 662  * debug registers, set the debug registers from the values
 663  * stored in the new thread.
 664  */
 665 void switch_booke_debug_regs(struct debug_reg *new_debug)
 666 {
 667         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 668                 || (new_debug->dbcr0 & DBCR0_IDM))
 669                         prime_debug_regs(new_debug);
 670 }
 671 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 672 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 673 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 674 static void set_debug_reg_defaults(struct thread_struct *thread)
 675 {
 676         thread->hw_brk.address = 0;
 677         thread->hw_brk.type = 0;
 678         set_breakpoint(&thread->hw_brk);
 679 }
 680 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 681 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 682
 683 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 684 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 685 {
 686         mtspr(SPRN_DAC1, dabr);
 687 #ifdef CONFIG_PPC_47x
 688         isync();
 689 #endif
 690         return 0;
 691 }
 692 #elif defined(CONFIG_PPC_BOOK3S)
 693 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 694 {
 695         mtspr(SPRN_DABR, dabr);
 696         if (cpu_has_feature(CPU_FTR_DABRX))
 697                 mtspr(SPRN_DABRX, dabrx);
 698         return 0;
 699 }
 700 #else
 701 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 702 {
 703         return -EINVAL;
 704 }
 705 #endif
 706
 707 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 708 {
 709         unsigned long dabr, dabrx;
 710
 711         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 712         dabrx = ((brk->type >> 3) & 0x7);
 713
 714         if (ppc_md.set_dabr)
 715                 return ppc_md.set_dabr(dabr, dabrx);
 716
 717         return __set_dabr(dabr, dabrx);
 718 }
 719
 720 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 721 {
 722         unsigned long dawr, dawrx, mrd;
 723
 724         dawr = brk->address;
 725
 726         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 727                                    << (63 - 58); //* read/write bits */
 728         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 729                                    << (63 - 59); //* translate */
 730         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 731                                    >> 3; //* PRIM bits */
 732         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 733            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 734            0b111111=64DW.
 735            brk->len is in bytes.
 736            This aligns up to double word size, shifts and does the bias.
 737         */
 738         mrd = ((brk->len + 7) >> 3) - 1;
 739         dawrx |= (mrd & 0x3f) << (63 - 53);
 740
 741         if (ppc_md.set_dawr)
 742                 return ppc_md.set_dawr(dawr, dawrx);
 743         mtspr(SPRN_DAWR, dawr);
 744         mtspr(SPRN_DAWRX, dawrx);
 745         return 0;
 746 }
 747
 748 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 749 {
 750         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 751
 752         if (cpu_has_feature(CPU_FTR_DAWR))
 753                 set_dawr(brk);
 754         else
 755                 set_dabr(brk);
 756 }
 757
 758 void set_breakpoint(struct arch_hw_breakpoint *brk)
 759 {
 760         preempt_disable();
 761         __set_breakpoint(brk);
 762         preempt_enable();
 763 }
 764
 765 #ifdef CONFIG_PPC64
 766 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 767 #endif
 768
 769 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 770                               struct arch_hw_breakpoint *b)
 771 {
 772         if (a->address != b->address)
 773                 return false;
 774         if (a->type != b->type)
 775                 return false;
 776         if (a->len != b->len)
 777                 return false;
 778         return true;
 779 }
 780
 781 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 782 static void tm_reclaim_thread(struct thread_struct *thr,
 783                               struct thread_info *ti, uint8_t cause)
 784 {
 785         unsigned long msr_diff = 0;
 786
 787         /*
 788          * If FP/VSX registers have been already saved to the
 789          * thread_struct, move them to the transact_fp array.
 790          * We clear the TIF_RESTORE_TM bit since after the reclaim
 791          * the thread will no longer be transactional.
 792          */
 793         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 794                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 795                 if (msr_diff & MSR_FP)
 796                         memcpy(&thr->transact_fp, &thr->fp_state,
 797                                sizeof(struct thread_fp_state));
 798                 if (msr_diff & MSR_VEC)
 799                         memcpy(&thr->transact_vr, &thr->vr_state,
 800                                sizeof(struct thread_vr_state));
 801                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 802                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 803         }
 804
 805         /*
 806          * Use the current MSR TM suspended bit to track if we have
 807          * checkpointed state outstanding.
 808          * On signal delivery, we'd normally reclaim the checkpointed
 809          * state to obtain stack pointer (see:get_tm_stackpointer()).
 810          * This will then directly return to userspace without going
 811          * through __switch_to(). However, if the stack frame is bad,
 812          * we need to exit this thread which calls __switch_to() which
 813          * will again attempt to reclaim the already saved tm state.
 814          * Hence we need to check that we've not already reclaimed
 815          * this state.
 816          * We do this using the current MSR, rather tracking it in
 817          * some specific thread_struct bit, as it has the additional
 818          * benefit of checking for a potential TM bad thing exception.
 819          */
 820         if (!MSR_TM_SUSPENDED(mfmsr()))
 821                 return;
 822
 823         tm_reclaim(thr, thr->regs->msr, cause);
 824
 825         /* Having done the reclaim, we now have the checkpointed
 826          * FP/VSX values in the registers.  These might be valid
 827          * even if we have previously called enable_kernel_fp() or
 828          * flush_fp_to_thread(), so update thr->regs->msr to
 829          * indicate their current validity.
 830          */
 831         thr->regs->msr |= msr_diff;
 832 }
 833
 834 void tm_reclaim_current(uint8_t cause)
 835 {
 836         tm_enable();
 837         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 838 }
 839
 840 static inline void tm_reclaim_task(struct task_struct *tsk)
 841 {
 842         /* We have to work out if we're switching from/to a task that's in the
 843          * middle of a transaction.
 844          *
 845          * In switching we need to maintain a 2nd register state as
 846          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 847          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 848          * (current) FPRs into oldtask->thread.transact_fpr[].
 849          *
 850          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 851          */
 852         struct thread_struct *thr = &tsk->thread;
 853
 854         if (!thr->regs)
 855                 return;
 856
 857         if (!MSR_TM_ACTIVE(thr->regs->msr))
 858                 goto out_and_saveregs;
 859
 860         /* Stash the original thread MSR, as giveup_fpu et al will
 861          * modify it.  We hold onto it to see whether the task used
 862          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 863          * ckpt_regs.msr is already set.
 864          */
 865         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 866                 thr->ckpt_regs.msr = thr->regs->msr;
 867
 868         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 869                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 870                  tsk->pid, thr->regs->nip,
 871                  thr->regs->ccr, thr->regs->msr,
 872                  thr->regs->trap);
 873
 874         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 875
 876         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 877                  tsk->pid);
 878
 879 out_and_saveregs:
 880         /* Always save the regs here, even if a transaction's not active.
 881          * This context-switches a thread's TM info SPRs.  We do it here to
 882          * be consistent with the restore path (in recheckpoint) which
 883          * cannot happen later in _switch().
 884          */
 885         tm_save_sprs(thr);
 886 }
 887
 888 extern void __tm_recheckpoint(struct thread_struct *thread,
 889                               unsigned long orig_msr);
 890
 891 void tm_recheckpoint(struct thread_struct *thread,
 892                      unsigned long orig_msr)
 893 {
 894         unsigned long flags;
 895
 896         /* We really can't be interrupted here as the TEXASR registers can't
 897          * change and later in the trecheckpoint code, we have a userspace R1.
 898          * So let's hard disable over this region.
 899          */
 900         local_irq_save(flags);
 901         hard_irq_disable();
 902
 903         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 904          * before the trecheckpoint and no explosion occurs.
 905          */
 906         tm_restore_sprs(thread);
 907
 908         __tm_recheckpoint(thread, orig_msr);
 909
 910         local_irq_restore(flags);
 911 }
 912
 913 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 914 {
 915         unsigned long msr;
 916
 917         if (!cpu_has_feature(CPU_FTR_TM))
 918                 return;
 919
 920         /* Recheckpoint the registers of the thread we're about to switch to.
 921          *
 922          * If the task was using FP, we non-lazily reload both the original and
 923          * the speculative FP register states.  This is because the kernel
 924          * doesn't see if/when a TM rollback occurs, so if we take an FP
 925          * unavoidable later, we are unable to determine which set of FP regs
 926          * need to be restored.
 927          */
 928         if (!new->thread.regs)
 929                 return;
 930
 931         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 932                 tm_restore_sprs(&new->thread);
 933                 return;
 934         }
 935         msr = new->thread.ckpt_regs.msr;
 936         /* Recheckpoint to restore original checkpointed register state. */
 937         TM_DEBUG("*** tm_recheckpoint of pid %d "
 938                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 939                  new->pid, new->thread.regs->msr, msr);
 940
 941         /* This loads the checkpointed FP/VEC state, if used */
 942         tm_recheckpoint(&new->thread, msr);
 943
 944         /* This loads the speculative FP/VEC state, if used */
 945         if (msr & MSR_FP) {
 946                 do_load_up_transact_fpu(&new->thread);
 947                 new->thread.regs->msr |=
 948                         (MSR_FP | new->thread.fpexc_mode);
 949         }
 950 #ifdef CONFIG_ALTIVEC
 951         if (msr & MSR_VEC) {
 952                 do_load_up_transact_altivec(&new->thread);
 953                 new->thread.regs->msr |= MSR_VEC;
 954         }
 955 #endif
 956         /* We may as well turn on VSX too since all the state is restored now */
 957         if (msr & MSR_VSX)
 958                 new->thread.regs->msr |= MSR_VSX;
 959
 960         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 961                  "(kernel msr 0x%lx)\n",
 962                  new->pid, mfmsr());
 963 }
 964
 965 static inline void __switch_to_tm(struct task_struct *prev)
 966 {
 967         if (cpu_has_feature(CPU_FTR_TM)) {
 968                 tm_enable();
 969                 tm_reclaim_task(prev);
 970         }
 971 }
 972
 973 /*
 974  * This is called if we are on the way out to userspace and the
 975  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 976  * FP and/or vector state and does so if necessary.
 977  * If userspace is inside a transaction (whether active or
 978  * suspended) and FP/VMX/VSX instructions have ever been enabled
 979  * inside that transaction, then we have to keep them enabled
 980  * and keep the FP/VMX/VSX state loaded while ever the transaction
 981  * continues.  The reason is that if we didn't, and subsequently
 982  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 983  * we don't know whether it's the same transaction, and thus we
 984  * don't know which of the checkpointed state and the transactional
 985  * state to use.
 986  */
 987 void restore_tm_state(struct pt_regs *regs)
 988 {
 989         unsigned long msr_diff;
 990
 991         clear_thread_flag(TIF_RESTORE_TM);
 992         if (!MSR_TM_ACTIVE(regs->msr))
 993                 return;
 994
 995         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 996         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 997
 998         /* Ensure that restore_math() will restore */
 999         if (msr_diff & MSR_FP)
1000                 current->thread.load_fp = 1;
1001 #ifdef CONFIG_ALIVEC
1002         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1003                 current->thread.load_vec = 1;
1004 #endif
1005         restore_math(regs);
1006
1007         regs->msr |= msr_diff;
1008 }
1009
1010 #else
1011 #define tm_recheckpoint_new_task(new)
1012 #define __switch_to_tm(prev)
1013 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1014
1015 static inline void save_sprs(struct thread_struct *t)
1016 {
1017 #ifdef CONFIG_ALTIVEC
1018         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1019                 t->vrsave = mfspr(SPRN_VRSAVE);
1020 #endif
1021 #ifdef CONFIG_PPC_BOOK3S_64
1022         if (cpu_has_feature(CPU_FTR_DSCR))
1023                 t->dscr = mfspr(SPRN_DSCR);
1024
1025         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1026                 t->bescr = mfspr(SPRN_BESCR);
1027                 t->ebbhr = mfspr(SPRN_EBBHR);
1028                 t->ebbrr = mfspr(SPRN_EBBRR);
1029
1030                 t->fscr = mfspr(SPRN_FSCR);
1031
1032                 /*
1033                  * Note that the TAR is not available for use in the kernel.
1034                  * (To provide this, the TAR should be backed up/restored on
1035                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1036                  * this should be in pt_regs anyway (for debug).)
1037                  */
1038                 t->tar = mfspr(SPRN_TAR);
1039         }
1040
1041         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1042                 /* Conditionally save Load Monitor registers, if enabled */
1043                 if (t->fscr & FSCR_LM) {
1044                         t->lmrr = mfspr(SPRN_LMRR);
1045                         t->lmser = mfspr(SPRN_LMSER);
1046                 }
1047         }
1048 #endif
1049 }
1050
1051 static inline void restore_sprs(struct thread_struct *old_thread,
1052                                 struct thread_struct *new_thread)
1053 {
1054 #ifdef CONFIG_ALTIVEC
1055         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1056             old_thread->vrsave != new_thread->vrsave)
1057                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1058 #endif
1059 #ifdef CONFIG_PPC_BOOK3S_64
1060         if (cpu_has_feature(CPU_FTR_DSCR)) {
1061                 u64 dscr = get_paca()->dscr_default;
1062                 if (new_thread->dscr_inherit)
1063                         dscr = new_thread->dscr;
1064
1065                 if (old_thread->dscr != dscr)
1066                         mtspr(SPRN_DSCR, dscr);
1067         }
1068
1069         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1070                 if (old_thread->bescr != new_thread->bescr)
1071                         mtspr(SPRN_BESCR, new_thread->bescr);
1072                 if (old_thread->ebbhr != new_thread->ebbhr)
1073                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1074                 if (old_thread->ebbrr != new_thread->ebbrr)
1075                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1076
1077                 if (old_thread->fscr != new_thread->fscr)
1078                         mtspr(SPRN_FSCR, new_thread->fscr);
1079
1080                 if (old_thread->tar != new_thread->tar)
1081                         mtspr(SPRN_TAR, new_thread->tar);
1082         }
1083
1084         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1085                 /* Conditionally restore Load Monitor registers, if enabled */
1086                 if (new_thread->fscr & FSCR_LM) {
1087                         if (old_thread->lmrr != new_thread->lmrr)
1088                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1089                         if (old_thread->lmser != new_thread->lmser)
1090                                 mtspr(SPRN_LMSER, new_thread->lmser);
1091                 }
1092         }
1093 #endif
1094 }
1095
1096 struct task_struct *__switch_to(struct task_struct *prev,
1097         struct task_struct *new)
1098 {
1099         struct thread_struct *new_thread, *old_thread;
1100         struct task_struct *last;
1101 #ifdef CONFIG_PPC_BOOK3S_64
1102         struct ppc64_tlb_batch *batch;
1103 #endif
1104
1105         new_thread = &new->thread;
1106         old_thread = &current->thread;
1107
1108         WARN_ON(!irqs_disabled());
1109
1110 #ifdef CONFIG_PPC64
1111         /*
1112          * Collect processor utilization data per process
1113          */
1114         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1115                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1116                 long unsigned start_tb, current_tb;
1117                 start_tb = old_thread->start_tb;
1118                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1119                 old_thread->accum_tb += (current_tb - start_tb);
1120                 new_thread->start_tb = current_tb;
1121         }
1122 #endif /* CONFIG_PPC64 */
1123
1124 #ifdef CONFIG_PPC_STD_MMU_64
1125         batch = this_cpu_ptr(&ppc64_tlb_batch);
1126         if (batch->active) {
1127                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1128                 if (batch->index)
1129                         __flush_tlb_pending(batch);
1130                 batch->active = 0;
1131         }
1132 #endif /* CONFIG_PPC_STD_MMU_64 */
1133
1134 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1135         switch_booke_debug_regs(&new->thread.debug);
1136 #else
1137 /*
1138  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1139  * schedule DABR
1140  */
1141 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1142         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1143                 __set_breakpoint(&new->thread.hw_brk);
1144 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1145 #endif
1146
1147         /*
1148          * We need to save SPRs before treclaim/trecheckpoint as these will
1149          * change a number of them.
1150          */
1151         save_sprs(&prev->thread);
1152
1153         __switch_to_tm(prev);
1154
1155         /* Save FPU, Altivec, VSX and SPE state */
1156         giveup_all(prev);
1157
1158         /*
1159          * We can't take a PMU exception inside _switch() since there is a
1160          * window where the kernel stack SLB and the kernel stack are out
1161          * of sync. Hard disable here.
1162          */
1163         hard_irq_disable();
1164
1165         tm_recheckpoint_new_task(new);
1166
1167         /*
1168          * Call restore_sprs() before calling _switch(). If we move it after
1169          * _switch() then we miss out on calling it for new tasks. The reason
1170          * for this is we manually create a stack frame for new tasks that
1171          * directly returns through ret_from_fork() or
1172          * ret_from_kernel_thread(). See copy_thread() for details.
1173          */
1174         restore_sprs(old_thread, new_thread);
1175
1176         last = _switch(old_thread, new_thread);
1177
1178 #ifdef CONFIG_PPC_STD_MMU_64
1179         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1180                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1181                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1182                 batch->active = 1;
1183         }
1184
1185         if (current_thread_info()->task->thread.regs)
1186                 restore_math(current_thread_info()->task->thread.regs);
1187 #endif /* CONFIG_PPC_STD_MMU_64 */
1188
1189         return last;
1190 }
1191
1192 static int instructions_to_print = 16;
1193
1194 static void show_instructions(struct pt_regs *regs)
1195 {
1196         int i;
1197         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1198                         sizeof(int));
1199
1200         printk("Instruction dump:");
1201
1202         for (i = 0; i < instructions_to_print; i++) {
1203                 int instr;
1204
1205                 if (!(i % 8))
1206                         printk("\n");
1207
1208 #if !defined(CONFIG_BOOKE)
1209                 /* If executing with the IMMU off, adjust pc rather
1210                  * than print XXXXXXXX.
1211                  */
1212                 if (!(regs->msr & MSR_IR))
1213                         pc = (unsigned long)phys_to_virt(pc);
1214 #endif
1215
1216                 if (!__kernel_text_address(pc) ||
1217                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1218                         printk(KERN_CONT "XXXXXXXX ");
1219                 } else {
1220                         if (regs->nip == pc)
1221                                 printk(KERN_CONT "<%08x> ", instr);
1222                         else
1223                                 printk(KERN_CONT "%08x ", instr);
1224                 }
1225
1226                 pc += sizeof(int);
1227         }
1228
1229         printk("\n");
1230 }
1231
1232 struct regbit {
1233         unsigned long bit;
1234         const char *name;
1235 };
1236
1237 static struct regbit msr_bits[] = {
1238 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1239         {MSR_SF,        "SF"},
1240         {MSR_HV,        "HV"},
1241 #endif
1242         {MSR_VEC,       "VEC"},
1243         {MSR_VSX,       "VSX"},
1244 #ifdef CONFIG_BOOKE
1245         {MSR_CE,        "CE"},
1246 #endif
1247         {MSR_EE,        "EE"},
1248         {MSR_PR,        "PR"},
1249         {MSR_FP,        "FP"},
1250         {MSR_ME,        "ME"},
1251 #ifdef CONFIG_BOOKE
1252         {MSR_DE,        "DE"},
1253 #else
1254         {MSR_SE,        "SE"},
1255         {MSR_BE,        "BE"},
1256 #endif
1257         {MSR_IR,        "IR"},
1258         {MSR_DR,        "DR"},
1259         {MSR_PMM,       "PMM"},
1260 #ifndef CONFIG_BOOKE
1261         {MSR_RI,        "RI"},
1262         {MSR_LE,        "LE"},
1263 #endif
1264         {0,             NULL}
1265 };
1266
1267 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1268 {
1269         const char *s = "";
1270
1271         for (; bits->bit; ++bits)
1272                 if (val & bits->bit) {
1273                         printk("%s%s", s, bits->name);
1274                         s = sep;
1275                 }
1276 }
1277
1278 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1279 static struct regbit msr_tm_bits[] = {
1280         {MSR_TS_T,      "T"},
1281         {MSR_TS_S,      "S"},
1282         {MSR_TM,        "E"},
1283         {0,             NULL}
1284 };
1285
1286 static void print_tm_bits(unsigned long val)
1287 {
1288 /*
1289  * This only prints something if at least one of the TM bit is set.
1290  * Inside the TM[], the output means:
1291  *   E: Enabled         (bit 32)
1292  *   S: Suspended       (bit 33)
1293  *   T: Transactional   (bit 34)
1294  */
1295         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1296                 printk(",TM[");
1297                 print_bits(val, msr_tm_bits, "");
1298                 printk("]");
1299         }
1300 }
1301 #else
1302 static void print_tm_bits(unsigned long val) {}
1303 #endif
1304
1305 static void print_msr_bits(unsigned long val)
1306 {
1307         printk("<");
1308         print_bits(val, msr_bits, ",");
1309         print_tm_bits(val);
1310         printk(">");
1311 }
1312
1313 #ifdef CONFIG_PPC64
1314 #define REG             "%016lx"
1315 #define REGS_PER_LINE   4
1316 #define LAST_VOLATILE   13
1317 #else
1318 #define REG             "%08lx"
1319 #define REGS_PER_LINE   8
1320 #define LAST_VOLATILE   12
1321 #endif
1322
1323 void show_regs(struct pt_regs * regs)
1324 {
1325         int i, trap;
1326
1327         show_regs_print_info(KERN_DEFAULT);
1328
1329         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1330                regs->nip, regs->link, regs->ctr);
1331         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1332                regs, regs->trap, print_tainted(), init_utsname()->release);
1333         printk("MSR: "REG" ", regs->msr);
1334         print_msr_bits(regs->msr);
1335         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1336         trap = TRAP(regs);
1337         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1338                 printk("CFAR: "REG" ", regs->orig_gpr3);
1339         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1340 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1341                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1342 #else
1343                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1344 #endif
1345 #ifdef CONFIG_PPC64
1346         printk("SOFTE: %ld ", regs->softe);
1347 #endif
1348 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349         if (MSR_TM_ACTIVE(regs->msr))
1350                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1351 #endif
1352
1353         for (i = 0;  i < 32;  i++) {
1354                 if ((i % REGS_PER_LINE) == 0)
1355                         printk("\nGPR%02d: ", i);
1356                 printk(REG " ", regs->gpr[i]);
1357                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1358                         break;
1359         }
1360         printk("\n");
1361 #ifdef CONFIG_KALLSYMS
1362         /*
1363          * Lookup NIP late so we have the best change of getting the
1364          * above info out without failing
1365          */
1366         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1367         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1368 #endif
1369         show_stack(current, (unsigned long *) regs->gpr[1]);
1370         if (!user_mode(regs))
1371                 show_instructions(regs);
1372 }
1373
1374 void flush_thread(void)
1375 {
1376 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1377         flush_ptrace_hw_breakpoint(current);
1378 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1379         set_debug_reg_defaults(&current->thread);
1380 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1381 }
1382
1383 void
1384 release_thread(struct task_struct *t)
1385 {
1386 }
1387
1388 /*
1389  * this gets called so that we can store coprocessor state into memory and
1390  * copy the current task into the new thread.
1391  */
1392 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1393 {
1394         flush_all_to_thread(src);
1395         /*
1396          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1397          * flush but it removes the checkpointed state from the current CPU and
1398          * transitions the CPU out of TM mode.  Hence we need to call
1399          * tm_recheckpoint_new_task() (on the same task) to restore the
1400          * checkpointed state back and the TM mode.
1401          */
1402         __switch_to_tm(src);
1403         tm_recheckpoint_new_task(src);
1404
1405         *dst = *src;
1406
1407         clear_task_ebb(dst);
1408
1409         return 0;
1410 }
1411
1412 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1413 {
1414 #ifdef CONFIG_PPC_STD_MMU_64
1415         unsigned long sp_vsid;
1416         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1417
1418         if (radix_enabled())
1419                 return;
1420
1421         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1422                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1423                         << SLB_VSID_SHIFT_1T;
1424         else
1425                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1426                         << SLB_VSID_SHIFT;
1427         sp_vsid |= SLB_VSID_KERNEL | llp;
1428         p->thread.ksp_vsid = sp_vsid;
1429 #endif
1430 }
1431
1432 /*
1433  * Copy a thread..
1434  */
1435
1436 /*
1437  * Copy architecture-specific thread state
1438  */
1439 int copy_thread(unsigned long clone_flags, unsigned long usp,
1440                 unsigned long kthread_arg, struct task_struct *p)
1441 {
1442         struct pt_regs *childregs, *kregs;
1443         extern void ret_from_fork(void);
1444         extern void ret_from_kernel_thread(void);
1445         void (*f)(void);
1446         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1447         struct thread_info *ti = task_thread_info(p);
1448
1449         klp_init_thread_info(ti);
1450
1451         /* Copy registers */
1452         sp -= sizeof(struct pt_regs);
1453         childregs = (struct pt_regs *) sp;
1454         if (unlikely(p->flags & PF_KTHREAD)) {
1455                 /* kernel thread */
1456                 memset(childregs, 0, sizeof(struct pt_regs));
1457                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1458                 /* function */
1459                 if (usp)
1460                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1461 #ifdef CONFIG_PPC64
1462                 clear_tsk_thread_flag(p, TIF_32BIT);
1463                 childregs->softe = 1;
1464 #endif
1465                 childregs->gpr[15] = kthread_arg;
1466                 p->thread.regs = NULL;  /* no user register state */
1467                 ti->flags |= _TIF_RESTOREALL;
1468                 f = ret_from_kernel_thread;
1469         } else {
1470                 /* user thread */
1471                 struct pt_regs *regs = current_pt_regs();
1472                 CHECK_FULL_REGS(regs);
1473                 *childregs = *regs;
1474                 if (usp)
1475                         childregs->gpr[1] = usp;
1476                 p->thread.regs = childregs;
1477                 childregs->gpr[3] = 0;  /* Result from fork() */
1478                 if (clone_flags & CLONE_SETTLS) {
1479 #ifdef CONFIG_PPC64
1480                         if (!is_32bit_task())
1481                                 childregs->gpr[13] = childregs->gpr[6];
1482                         else
1483 #endif
1484                                 childregs->gpr[2] = childregs->gpr[6];
1485                 }
1486
1487                 f = ret_from_fork;
1488         }
1489         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1490         sp -= STACK_FRAME_OVERHEAD;
1491
1492         /*
1493          * The way this works is that at some point in the future
1494          * some task will call _switch to switch to the new task.
1495          * That will pop off the stack frame created below and start
1496          * the new task running at ret_from_fork.  The new task will
1497          * do some house keeping and then return from the fork or clone
1498          * system call, using the stack frame created above.
1499          */
1500         ((unsigned long *)sp)[0] = 0;
1501         sp -= sizeof(struct pt_regs);
1502         kregs = (struct pt_regs *) sp;
1503         sp -= STACK_FRAME_OVERHEAD;
1504         p->thread.ksp = sp;
1505 #ifdef CONFIG_PPC32
1506         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1507                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1508 #endif
1509 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1510         p->thread.ptrace_bps[0] = NULL;
1511 #endif
1512
1513         p->thread.fp_save_area = NULL;
1514 #ifdef CONFIG_ALTIVEC
1515         p->thread.vr_save_area = NULL;
1516 #endif
1517
1518         setup_ksp_vsid(p, sp);
1519
1520 #ifdef CONFIG_PPC64
1521         if (cpu_has_feature(CPU_FTR_DSCR)) {
1522                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1523                 p->thread.dscr = mfspr(SPRN_DSCR);
1524         }
1525         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1526                 p->thread.ppr = INIT_PPR;
1527 #endif
1528         kregs->nip = ppc_function_entry(f);
1529         return 0;
1530 }
1531
1532 /*
1533  * Set up a thread for executing a new program
1534  */
1535 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1536 {
1537 #ifdef CONFIG_PPC64
1538         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1539 #endif
1540
1541         /*
1542          * If we exec out of a kernel thread then thread.regs will not be
1543          * set.  Do it now.
1544          */
1545         if (!current->thread.regs) {
1546                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1547                 current->thread.regs = regs - 1;
1548         }
1549
1550 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1551         /*
1552          * Clear any transactional state, we're exec()ing. The cause is
1553          * not important as there will never be a recheckpoint so it's not
1554          * user visible.
1555          */
1556         if (MSR_TM_SUSPENDED(mfmsr()))
1557                 tm_reclaim_current(0);
1558 #endif
1559
1560         memset(regs->gpr, 0, sizeof(regs->gpr));
1561         regs->ctr = 0;
1562         regs->link = 0;
1563         regs->xer = 0;
1564         regs->ccr = 0;
1565         regs->gpr[1] = sp;
1566
1567         /*
1568          * We have just cleared all the nonvolatile GPRs, so make
1569          * FULL_REGS(regs) return true.  This is necessary to allow
1570          * ptrace to examine the thread immediately after exec.
1571          */
1572         regs->trap &= ~1UL;
1573
1574 #ifdef CONFIG_PPC32
1575         regs->mq = 0;
1576         regs->nip = start;
1577         regs->msr = MSR_USER;
1578 #else
1579         if (!is_32bit_task()) {
1580                 unsigned long entry;
1581
1582                 if (is_elf2_task()) {
1583                         /* Look ma, no function descriptors! */
1584                         entry = start;
1585
1586                         /*
1587                          * Ulrich says:
1588                          *   The latest iteration of the ABI requires that when
1589                          *   calling a function (at its global entry point),
1590                          *   the caller must ensure r12 holds the entry point
1591                          *   address (so that the function can quickly
1592                          *   establish addressability).
1593                          */
1594                         regs->gpr[12] = start;
1595                         /* Make sure that's restored on entry to userspace. */
1596                         set_thread_flag(TIF_RESTOREALL);
1597                 } else {
1598                         unsigned long toc;
1599
1600                         /* start is a relocated pointer to the function
1601                          * descriptor for the elf _start routine.  The first
1602                          * entry in the function descriptor is the entry
1603                          * address of _start and the second entry is the TOC
1604                          * value we need to use.
1605                          */
1606                         __get_user(entry, (unsigned long __user *)start);
1607                         __get_user(toc, (unsigned long __user *)start+1);
1608
1609                         /* Check whether the e_entry function descriptor entries
1610                          * need to be relocated before we can use them.
1611                          */
1612                         if (load_addr != 0) {
1613                                 entry += load_addr;
1614                                 toc   += load_addr;
1615                         }
1616                         regs->gpr[2] = toc;
1617                 }
1618                 regs->nip = entry;
1619                 regs->msr = MSR_USER64;
1620         } else {
1621                 regs->nip = start;
1622                 regs->gpr[2] = 0;
1623                 regs->msr = MSR_USER32;
1624         }
1625 #endif
1626 #ifdef CONFIG_VSX
1627         current->thread.used_vsr = 0;
1628 #endif
1629         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1630         current->thread.fp_save_area = NULL;
1631 #ifdef CONFIG_ALTIVEC
1632         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1633         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1634         current->thread.vr_save_area = NULL;
1635         current->thread.vrsave = 0;
1636         current->thread.used_vr = 0;
1637 #endif /* CONFIG_ALTIVEC */
1638 #ifdef CONFIG_SPE
1639         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1640         current->thread.acc = 0;
1641         current->thread.spefscr = 0;
1642         current->thread.used_spe = 0;
1643 #endif /* CONFIG_SPE */
1644 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1645         if (cpu_has_feature(CPU_FTR_TM))
1646                 regs->msr |= MSR_TM;
1647         current->thread.tm_tfhar = 0;
1648         current->thread.tm_texasr = 0;
1649         current->thread.tm_tfiar = 0;
1650 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1651 }
1652 EXPORT_SYMBOL(start_thread);
1653
1654 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1655                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1656
1657 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1658 {
1659         struct pt_regs *regs = tsk->thread.regs;
1660
1661         /* This is a bit hairy.  If we are an SPE enabled  processor
1662          * (have embedded fp) we store the IEEE exception enable flags in
1663          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1664          * mode (asyn, precise, disabled) for 'Classic' FP. */
1665         if (val & PR_FP_EXC_SW_ENABLE) {
1666 #ifdef CONFIG_SPE
1667                 if (cpu_has_feature(CPU_FTR_SPE)) {
1668                         /*
1669                          * When the sticky exception bits are set
1670                          * directly by userspace, it must call prctl
1671                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1672                          * in the existing prctl settings) or
1673                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1674                          * the bits being set).  <fenv.h> functions
1675                          * saving and restoring the whole
1676                          * floating-point environment need to do so
1677                          * anyway to restore the prctl settings from
1678                          * the saved environment.
1679                          */
1680                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1681                         tsk->thread.fpexc_mode = val &
1682                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1683                         return 0;
1684                 } else {
1685                         return -EINVAL;
1686                 }
1687 #else
1688                 return -EINVAL;
1689 #endif
1690         }
1691
1692         /* on a CONFIG_SPE this does not hurt us.  The bits that
1693          * __pack_fe01 use do not overlap with bits used for
1694          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1695          * on CONFIG_SPE implementations are reserved so writing to
1696          * them does not change anything */
1697         if (val > PR_FP_EXC_PRECISE)
1698                 return -EINVAL;
1699         tsk->thread.fpexc_mode = __pack_fe01(val);
1700         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1701                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1702                         | tsk->thread.fpexc_mode;
1703         return 0;
1704 }
1705
1706 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1707 {
1708         unsigned int val;
1709
1710         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1711 #ifdef CONFIG_SPE
1712                 if (cpu_has_feature(CPU_FTR_SPE)) {
1713                         /*
1714                          * When the sticky exception bits are set
1715                          * directly by userspace, it must call prctl
1716                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1717                          * in the existing prctl settings) or
1718                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1719                          * the bits being set).  <fenv.h> functions
1720                          * saving and restoring the whole
1721                          * floating-point environment need to do so
1722                          * anyway to restore the prctl settings from
1723                          * the saved environment.
1724                          */
1725                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1726                         val = tsk->thread.fpexc_mode;
1727                 } else
1728                         return -EINVAL;
1729 #else
1730                 return -EINVAL;
1731 #endif
1732         else
1733                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1734         return put_user(val, (unsigned int __user *) adr);
1735 }
1736
1737 int set_endian(struct task_struct *tsk, unsigned int val)
1738 {
1739         struct pt_regs *regs = tsk->thread.regs;
1740
1741         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1742             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1743                 return -EINVAL;
1744
1745         if (regs == NULL)
1746                 return -EINVAL;
1747
1748         if (val == PR_ENDIAN_BIG)
1749                 regs->msr &= ~MSR_LE;
1750         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1751                 regs->msr |= MSR_LE;
1752         else
1753                 return -EINVAL;
1754
1755         return 0;
1756 }
1757
1758 int get_endian(struct task_struct *tsk, unsigned long adr)
1759 {
1760         struct pt_regs *regs = tsk->thread.regs;
1761         unsigned int val;
1762
1763         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1764             !cpu_has_feature(CPU_FTR_REAL_LE))
1765                 return -EINVAL;
1766
1767         if (regs == NULL)
1768                 return -EINVAL;
1769
1770         if (regs->msr & MSR_LE) {
1771                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1772                         val = PR_ENDIAN_LITTLE;
1773                 else
1774                         val = PR_ENDIAN_PPC_LITTLE;
1775         } else
1776                 val = PR_ENDIAN_BIG;
1777
1778         return put_user(val, (unsigned int __user *)adr);
1779 }
1780
1781 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1782 {
1783         tsk->thread.align_ctl = val;
1784         return 0;
1785 }
1786
1787 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1788 {
1789         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1790 }
1791
1792 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1793                                   unsigned long nbytes)
1794 {
1795         unsigned long stack_page;
1796         unsigned long cpu = task_cpu(p);
1797
1798         /*
1799          * Avoid crashing if the stack has overflowed and corrupted
1800          * task_cpu(p), which is in the thread_info struct.
1801          */
1802         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1803                 stack_page = (unsigned long) hardirq_ctx[cpu];
1804                 if (sp >= stack_page + sizeof(struct thread_struct)
1805                     && sp <= stack_page + THREAD_SIZE - nbytes)
1806                         return 1;
1807
1808                 stack_page = (unsigned long) softirq_ctx[cpu];
1809                 if (sp >= stack_page + sizeof(struct thread_struct)
1810                     && sp <= stack_page + THREAD_SIZE - nbytes)
1811                         return 1;
1812         }
1813         return 0;
1814 }
1815
1816 int validate_sp(unsigned long sp, struct task_struct *p,
1817                        unsigned long nbytes)
1818 {
1819         unsigned long stack_page = (unsigned long)task_stack_page(p);
1820
1821         if (sp >= stack_page + sizeof(struct thread_struct)
1822             && sp <= stack_page + THREAD_SIZE - nbytes)
1823                 return 1;
1824
1825         return valid_irq_stack(sp, p, nbytes);
1826 }
1827
1828 EXPORT_SYMBOL(validate_sp);
1829
1830 unsigned long get_wchan(struct task_struct *p)
1831 {
1832         unsigned long ip, sp;
1833         int count = 0;
1834
1835         if (!p || p == current || p->state == TASK_RUNNING)
1836                 return 0;
1837
1838         sp = p->thread.ksp;
1839         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1840                 return 0;
1841
1842         do {
1843                 sp = *(unsigned long *)sp;
1844                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1845                         return 0;
1846                 if (count > 0) {
1847                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1848                         if (!in_sched_functions(ip))
1849                                 return ip;
1850                 }
1851         } while (count++ < 16);
1852         return 0;
1853 }
1854
1855 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1856
1857 void show_stack(struct task_struct *tsk, unsigned long *stack)
1858 {
1859         unsigned long sp, ip, lr, newsp;
1860         int count = 0;
1861         int firstframe = 1;
1862 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1863         int curr_frame = current->curr_ret_stack;
1864         extern void return_to_handler(void);
1865         unsigned long rth = (unsigned long)return_to_handler;
1866 #endif
1867
1868         sp = (unsigned long) stack;
1869         if (tsk == NULL)
1870                 tsk = current;
1871         if (sp == 0) {
1872                 if (tsk == current)
1873                         sp = current_stack_pointer();
1874                 else
1875                         sp = tsk->thread.ksp;
1876         }
1877
1878         lr = 0;
1879         printk("Call Trace:\n");
1880         do {
1881                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1882                         return;
1883
1884                 stack = (unsigned long *) sp;
1885                 newsp = stack[0];
1886                 ip = stack[STACK_FRAME_LR_SAVE];
1887                 if (!firstframe || ip != lr) {
1888                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1889 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1890                         if ((ip == rth) && curr_frame >= 0) {
1891                                 printk(" (%pS)",
1892                                        (void *)current->ret_stack[curr_frame].ret);
1893                                 curr_frame--;
1894                         }
1895 #endif
1896                         if (firstframe)
1897                                 printk(" (unreliable)");
1898                         printk("\n");
1899                 }
1900                 firstframe = 0;
1901
1902                 /*
1903                  * See if this is an exception frame.
1904                  * We look for the "regshere" marker in the current frame.
1905                  */
1906                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1907                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1908                         struct pt_regs *regs = (struct pt_regs *)
1909                                 (sp + STACK_FRAME_OVERHEAD);
1910                         lr = regs->link;
1911                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1912                                regs->trap, (void *)regs->nip, (void *)lr);
1913                         firstframe = 1;
1914                 }
1915
1916                 sp = newsp;
1917         } while (count++ < kstack_depth_to_print);
1918 }
1919
1920 #ifdef CONFIG_PPC64
1921 /* Called with hard IRQs off */
1922 void notrace __ppc64_runlatch_on(void)
1923 {
1924         struct thread_info *ti = current_thread_info();
1925         unsigned long ctrl;
1926
1927         ctrl = mfspr(SPRN_CTRLF);
1928         ctrl |= CTRL_RUNLATCH;
1929         mtspr(SPRN_CTRLT, ctrl);
1930
1931         ti->local_flags |= _TLF_RUNLATCH;
1932 }
1933
1934 /* Called with hard IRQs off */
1935 void notrace __ppc64_runlatch_off(void)
1936 {
1937         struct thread_info *ti = current_thread_info();
1938         unsigned long ctrl;
1939
1940         ti->local_flags &= ~_TLF_RUNLATCH;
1941
1942         ctrl = mfspr(SPRN_CTRLF);
1943         ctrl &= ~CTRL_RUNLATCH;
1944         mtspr(SPRN_CTRLT, ctrl);
1945 }
1946 #endif /* CONFIG_PPC64 */
1947
1948 unsigned long arch_align_stack(unsigned long sp)
1949 {
1950         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1951                 sp -= get_random_int() & ~PAGE_MASK;
1952         return sp & ~0xf;
1953 }
1954
1955 static inline unsigned long brk_rnd(void)
1956 {
1957         unsigned long rnd = 0;
1958
1959         /* 8MB for 32bit, 1GB for 64bit */
1960         if (is_32bit_task())
1961                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1962         else
1963                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1964
1965         return rnd << PAGE_SHIFT;
1966 }
1967
1968 unsigned long arch_randomize_brk(struct mm_struct *mm)
1969 {
1970         unsigned long base = mm->brk;
1971         unsigned long ret;
1972
1973 #ifdef CONFIG_PPC_STD_MMU_64
1974         /*
1975          * If we are using 1TB segments and we are allowed to randomise
1976          * the heap, we can put it above 1TB so it is backed by a 1TB
1977          * segment. Otherwise the heap will be in the bottom 1TB
1978          * which always uses 256MB segments and this may result in a
1979          * performance penalty. We don't need to worry about radix. For
1980          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1981          */
1982         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1983                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1984 #endif
1985
1986         ret = PAGE_ALIGN(base + brk_rnd());
1987
1988         if (ret < mm->brk)
1989                 return mm->brk;
1990
1991         return ret;
1992 }
1993