arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 void msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128 }
 129
 130 void __msr_check_and_clear(unsigned long bits)
 131 {
 132         unsigned long oldmsr = mfmsr();
 133         unsigned long newmsr;
 134
 135         newmsr = oldmsr & ~bits;
 136
 137 #ifdef CONFIG_VSX
 138         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 139                 newmsr &= ~MSR_VSX;
 140 #endif
 141
 142         if (oldmsr != newmsr)
 143                 mtmsr_isync(newmsr);
 144 }
 145 EXPORT_SYMBOL(__msr_check_and_clear);
 146
 147 #ifdef CONFIG_PPC_FPU
 148 void __giveup_fpu(struct task_struct *tsk)
 149 {
 150         unsigned long msr;
 151
 152         save_fpu(tsk);
 153         msr = tsk->thread.regs->msr;
 154         msr &= ~MSR_FP;
 155 #ifdef CONFIG_VSX
 156         if (cpu_has_feature(CPU_FTR_VSX))
 157                 msr &= ~MSR_VSX;
 158 #endif
 159         tsk->thread.regs->msr = msr;
 160 }
 161
 162 void giveup_fpu(struct task_struct *tsk)
 163 {
 164         check_if_tm_restore_required(tsk);
 165
 166         msr_check_and_set(MSR_FP);
 167         __giveup_fpu(tsk);
 168         msr_check_and_clear(MSR_FP);
 169 }
 170 EXPORT_SYMBOL(giveup_fpu);
 171
 172 /*
 173  * Make sure the floating-point register state in the
 174  * the thread_struct is up to date for task tsk.
 175  */
 176 void flush_fp_to_thread(struct task_struct *tsk)
 177 {
 178         if (tsk->thread.regs) {
 179                 /*
 180                  * We need to disable preemption here because if we didn't,
 181                  * another process could get scheduled after the regs->msr
 182                  * test but before we have finished saving the FP registers
 183                  * to the thread_struct.  That process could take over the
 184                  * FPU, and then when we get scheduled again we would store
 185                  * bogus values for the remaining FP registers.
 186                  */
 187                 preempt_disable();
 188                 if (tsk->thread.regs->msr & MSR_FP) {
 189                         /*
 190                          * This should only ever be called for current or
 191                          * for a stopped child process.  Since we save away
 192                          * the FP register state on context switch,
 193                          * there is something wrong if a stopped child appears
 194                          * to still have its FP state in the CPU registers.
 195                          */
 196                         BUG_ON(tsk != current);
 197                         giveup_fpu(tsk);
 198                 }
 199                 preempt_enable();
 200         }
 201 }
 202 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 203
 204 void enable_kernel_fp(void)
 205 {
 206         WARN_ON(preemptible());
 207
 208         msr_check_and_set(MSR_FP);
 209
 210         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 211                 check_if_tm_restore_required(current);
 212                 __giveup_fpu(current);
 213         }
 214 }
 215 EXPORT_SYMBOL(enable_kernel_fp);
 216
 217 static int restore_fp(struct task_struct *tsk) {
 218         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 219                 load_fp_state(&current->thread.fp_state);
 220                 current->thread.load_fp++;
 221                 return 1;
 222         }
 223         return 0;
 224 }
 225 #else
 226 static int restore_fp(struct task_struct *tsk) { return 0; }
 227 #endif /* CONFIG_PPC_FPU */
 228
 229 #ifdef CONFIG_ALTIVEC
 230 #define loadvec(thr) ((thr).load_vec)
 231
 232 static void __giveup_altivec(struct task_struct *tsk)
 233 {
 234         unsigned long msr;
 235
 236         save_altivec(tsk);
 237         msr = tsk->thread.regs->msr;
 238         msr &= ~MSR_VEC;
 239 #ifdef CONFIG_VSX
 240         if (cpu_has_feature(CPU_FTR_VSX))
 241                 msr &= ~MSR_VSX;
 242 #endif
 243         tsk->thread.regs->msr = msr;
 244 }
 245
 246 void giveup_altivec(struct task_struct *tsk)
 247 {
 248         check_if_tm_restore_required(tsk);
 249
 250         msr_check_and_set(MSR_VEC);
 251         __giveup_altivec(tsk);
 252         msr_check_and_clear(MSR_VEC);
 253 }
 254 EXPORT_SYMBOL(giveup_altivec);
 255
 256 void enable_kernel_altivec(void)
 257 {
 258         WARN_ON(preemptible());
 259
 260         msr_check_and_set(MSR_VEC);
 261
 262         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 263                 check_if_tm_restore_required(current);
 264                 __giveup_altivec(current);
 265         }
 266 }
 267 EXPORT_SYMBOL(enable_kernel_altivec);
 268
 269 /*
 270  * Make sure the VMX/Altivec register state in the
 271  * the thread_struct is up to date for task tsk.
 272  */
 273 void flush_altivec_to_thread(struct task_struct *tsk)
 274 {
 275         if (tsk->thread.regs) {
 276                 preempt_disable();
 277                 if (tsk->thread.regs->msr & MSR_VEC) {
 278                         BUG_ON(tsk != current);
 279                         giveup_altivec(tsk);
 280                 }
 281                 preempt_enable();
 282         }
 283 }
 284 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 285
 286 static int restore_altivec(struct task_struct *tsk)
 287 {
 288         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 289                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 290                 load_vr_state(&tsk->thread.vr_state);
 291                 tsk->thread.used_vr = 1;
 292                 tsk->thread.load_vec++;
 293
 294                 return 1;
 295         }
 296         return 0;
 297 }
 298 #else
 299 #define loadvec(thr) 0
 300 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 301 #endif /* CONFIG_ALTIVEC */
 302
 303 #ifdef CONFIG_VSX
 304 static void __giveup_vsx(struct task_struct *tsk)
 305 {
 306         if (tsk->thread.regs->msr & MSR_FP)
 307                 __giveup_fpu(tsk);
 308         if (tsk->thread.regs->msr & MSR_VEC)
 309                 __giveup_altivec(tsk);
 310         tsk->thread.regs->msr &= ~MSR_VSX;
 311 }
 312
 313 static void giveup_vsx(struct task_struct *tsk)
 314 {
 315         check_if_tm_restore_required(tsk);
 316
 317         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 318         __giveup_vsx(tsk);
 319         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 320 }
 321
 322 static void save_vsx(struct task_struct *tsk)
 323 {
 324         if (tsk->thread.regs->msr & MSR_FP)
 325                 save_fpu(tsk);
 326         if (tsk->thread.regs->msr & MSR_VEC)
 327                 save_altivec(tsk);
 328 }
 329
 330 void enable_kernel_vsx(void)
 331 {
 332         WARN_ON(preemptible());
 333
 334         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 335
 336         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 337                 check_if_tm_restore_required(current);
 338                 if (current->thread.regs->msr & MSR_FP)
 339                         __giveup_fpu(current);
 340                 if (current->thread.regs->msr & MSR_VEC)
 341                         __giveup_altivec(current);
 342                 __giveup_vsx(current);
 343         }
 344 }
 345 EXPORT_SYMBOL(enable_kernel_vsx);
 346
 347 void flush_vsx_to_thread(struct task_struct *tsk)
 348 {
 349         if (tsk->thread.regs) {
 350                 preempt_disable();
 351                 if (tsk->thread.regs->msr & MSR_VSX) {
 352                         BUG_ON(tsk != current);
 353                         giveup_vsx(tsk);
 354                 }
 355                 preempt_enable();
 356         }
 357 }
 358 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 359
 360 static int restore_vsx(struct task_struct *tsk)
 361 {
 362         if (cpu_has_feature(CPU_FTR_VSX)) {
 363                 tsk->thread.used_vsr = 1;
 364                 return 1;
 365         }
 366
 367         return 0;
 368 }
 369 #else
 370 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 371 static inline void save_vsx(struct task_struct *tsk) { }
 372 #endif /* CONFIG_VSX */
 373
 374 #ifdef CONFIG_SPE
 375 void giveup_spe(struct task_struct *tsk)
 376 {
 377         check_if_tm_restore_required(tsk);
 378
 379         msr_check_and_set(MSR_SPE);
 380         __giveup_spe(tsk);
 381         msr_check_and_clear(MSR_SPE);
 382 }
 383 EXPORT_SYMBOL(giveup_spe);
 384
 385 void enable_kernel_spe(void)
 386 {
 387         WARN_ON(preemptible());
 388
 389         msr_check_and_set(MSR_SPE);
 390
 391         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 392                 check_if_tm_restore_required(current);
 393                 __giveup_spe(current);
 394         }
 395 }
 396 EXPORT_SYMBOL(enable_kernel_spe);
 397
 398 void flush_spe_to_thread(struct task_struct *tsk)
 399 {
 400         if (tsk->thread.regs) {
 401                 preempt_disable();
 402                 if (tsk->thread.regs->msr & MSR_SPE) {
 403                         BUG_ON(tsk != current);
 404                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 405                         giveup_spe(tsk);
 406                 }
 407                 preempt_enable();
 408         }
 409 }
 410 #endif /* CONFIG_SPE */
 411
 412 static unsigned long msr_all_available;
 413
 414 static int __init init_msr_all_available(void)
 415 {
 416 #ifdef CONFIG_PPC_FPU
 417         msr_all_available |= MSR_FP;
 418 #endif
 419 #ifdef CONFIG_ALTIVEC
 420         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 421                 msr_all_available |= MSR_VEC;
 422 #endif
 423 #ifdef CONFIG_VSX
 424         if (cpu_has_feature(CPU_FTR_VSX))
 425                 msr_all_available |= MSR_VSX;
 426 #endif
 427 #ifdef CONFIG_SPE
 428         if (cpu_has_feature(CPU_FTR_SPE))
 429                 msr_all_available |= MSR_SPE;
 430 #endif
 431
 432         return 0;
 433 }
 434 early_initcall(init_msr_all_available);
 435
 436 void giveup_all(struct task_struct *tsk)
 437 {
 438         unsigned long usermsr;
 439
 440         if (!tsk->thread.regs)
 441                 return;
 442
 443         usermsr = tsk->thread.regs->msr;
 444
 445         if ((usermsr & msr_all_available) == 0)
 446                 return;
 447
 448         msr_check_and_set(msr_all_available);
 449
 450 #ifdef CONFIG_PPC_FPU
 451         if (usermsr & MSR_FP)
 452                 __giveup_fpu(tsk);
 453 #endif
 454 #ifdef CONFIG_ALTIVEC
 455         if (usermsr & MSR_VEC)
 456                 __giveup_altivec(tsk);
 457 #endif
 458 #ifdef CONFIG_VSX
 459         if (usermsr & MSR_VSX)
 460                 __giveup_vsx(tsk);
 461 #endif
 462 #ifdef CONFIG_SPE
 463         if (usermsr & MSR_SPE)
 464                 __giveup_spe(tsk);
 465 #endif
 466
 467         msr_check_and_clear(msr_all_available);
 468 }
 469 EXPORT_SYMBOL(giveup_all);
 470
 471 void restore_math(struct pt_regs *regs)
 472 {
 473         unsigned long msr;
 474
 475         if (!msr_tm_active(regs->msr) &&
 476                 !current->thread.load_fp && !loadvec(current->thread))
 477                 return;
 478
 479         msr = regs->msr;
 480         msr_check_and_set(msr_all_available);
 481
 482         /*
 483          * Only reload if the bit is not set in the user MSR, the bit BEING set
 484          * indicates that the registers are hot
 485          */
 486         if ((!(msr & MSR_FP)) && restore_fp(current))
 487                 msr |= MSR_FP | current->thread.fpexc_mode;
 488
 489         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 490                 msr |= MSR_VEC;
 491
 492         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 493                         restore_vsx(current)) {
 494                 msr |= MSR_VSX;
 495         }
 496
 497         msr_check_and_clear(msr_all_available);
 498
 499         regs->msr = msr;
 500 }
 501
 502 void save_all(struct task_struct *tsk)
 503 {
 504         unsigned long usermsr;
 505
 506         if (!tsk->thread.regs)
 507                 return;
 508
 509         usermsr = tsk->thread.regs->msr;
 510
 511         if ((usermsr & msr_all_available) == 0)
 512                 return;
 513
 514         msr_check_and_set(msr_all_available);
 515
 516         /*
 517          * Saving the way the register space is in hardware, save_vsx boils
 518          * down to a save_fpu() and save_altivec()
 519          */
 520         if (usermsr & MSR_VSX) {
 521                 save_vsx(tsk);
 522         } else {
 523                 if (usermsr & MSR_FP)
 524                         save_fpu(tsk);
 525
 526                 if (usermsr & MSR_VEC)
 527                         save_altivec(tsk);
 528         }
 529
 530         if (usermsr & MSR_SPE)
 531                 __giveup_spe(tsk);
 532
 533         msr_check_and_clear(msr_all_available);
 534 }
 535
 536 void flush_all_to_thread(struct task_struct *tsk)
 537 {
 538         if (tsk->thread.regs) {
 539                 preempt_disable();
 540                 BUG_ON(tsk != current);
 541                 save_all(tsk);
 542
 543 #ifdef CONFIG_SPE
 544                 if (tsk->thread.regs->msr & MSR_SPE)
 545                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 546 #endif
 547
 548                 preempt_enable();
 549         }
 550 }
 551 EXPORT_SYMBOL(flush_all_to_thread);
 552
 553 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 554 void do_send_trap(struct pt_regs *regs, unsigned long address,
 555                   unsigned long error_code, int signal_code, int breakpt)
 556 {
 557         siginfo_t info;
 558
 559         current->thread.trap_nr = signal_code;
 560         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 561                         11, SIGSEGV) == NOTIFY_STOP)
 562                 return;
 563
 564         /* Deliver the signal to userspace */
 565         info.si_signo = SIGTRAP;
 566         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 567         info.si_code = signal_code;
 568         info.si_addr = (void __user *)address;
 569         force_sig_info(SIGTRAP, &info, current);
 570 }
 571 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 572 void do_break (struct pt_regs *regs, unsigned long address,
 573                     unsigned long error_code)
 574 {
 575         siginfo_t info;
 576
 577         current->thread.trap_nr = TRAP_HWBKPT;
 578         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 579                         11, SIGSEGV) == NOTIFY_STOP)
 580                 return;
 581
 582         if (debugger_break_match(regs))
 583                 return;
 584
 585         /* Clear the breakpoint */
 586         hw_breakpoint_disable();
 587
 588         /* Deliver the signal to userspace */
 589         info.si_signo = SIGTRAP;
 590         info.si_errno = 0;
 591         info.si_code = TRAP_HWBKPT;
 592         info.si_addr = (void __user *)address;
 593         force_sig_info(SIGTRAP, &info, current);
 594 }
 595 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 596
 597 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 598
 599 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 600 /*
 601  * Set the debug registers back to their default "safe" values.
 602  */
 603 static void set_debug_reg_defaults(struct thread_struct *thread)
 604 {
 605         thread->debug.iac1 = thread->debug.iac2 = 0;
 606 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 607         thread->debug.iac3 = thread->debug.iac4 = 0;
 608 #endif
 609         thread->debug.dac1 = thread->debug.dac2 = 0;
 610 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 611         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 612 #endif
 613         thread->debug.dbcr0 = 0;
 614 #ifdef CONFIG_BOOKE
 615         /*
 616          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 617          */
 618         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 619                         DBCR1_IAC3US | DBCR1_IAC4US;
 620         /*
 621          * Force Data Address Compare User/Supervisor bits to be User-only
 622          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 623          */
 624         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 625 #else
 626         thread->debug.dbcr1 = 0;
 627 #endif
 628 }
 629
 630 static void prime_debug_regs(struct debug_reg *debug)
 631 {
 632         /*
 633          * We could have inherited MSR_DE from userspace, since
 634          * it doesn't get cleared on exception entry.  Make sure
 635          * MSR_DE is clear before we enable any debug events.
 636          */
 637         mtmsr(mfmsr() & ~MSR_DE);
 638
 639         mtspr(SPRN_IAC1, debug->iac1);
 640         mtspr(SPRN_IAC2, debug->iac2);
 641 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 642         mtspr(SPRN_IAC3, debug->iac3);
 643         mtspr(SPRN_IAC4, debug->iac4);
 644 #endif
 645         mtspr(SPRN_DAC1, debug->dac1);
 646         mtspr(SPRN_DAC2, debug->dac2);
 647 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 648         mtspr(SPRN_DVC1, debug->dvc1);
 649         mtspr(SPRN_DVC2, debug->dvc2);
 650 #endif
 651         mtspr(SPRN_DBCR0, debug->dbcr0);
 652         mtspr(SPRN_DBCR1, debug->dbcr1);
 653 #ifdef CONFIG_BOOKE
 654         mtspr(SPRN_DBCR2, debug->dbcr2);
 655 #endif
 656 }
 657 /*
 658  * Unless neither the old or new thread are making use of the
 659  * debug registers, set the debug registers from the values
 660  * stored in the new thread.
 661  */
 662 void switch_booke_debug_regs(struct debug_reg *new_debug)
 663 {
 664         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 665                 || (new_debug->dbcr0 & DBCR0_IDM))
 666                         prime_debug_regs(new_debug);
 667 }
 668 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 669 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 670 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 671 static void set_debug_reg_defaults(struct thread_struct *thread)
 672 {
 673         thread->hw_brk.address = 0;
 674         thread->hw_brk.type = 0;
 675         set_breakpoint(&thread->hw_brk);
 676 }
 677 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 678 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 679
 680 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 681 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 682 {
 683         mtspr(SPRN_DAC1, dabr);
 684 #ifdef CONFIG_PPC_47x
 685         isync();
 686 #endif
 687         return 0;
 688 }
 689 #elif defined(CONFIG_PPC_BOOK3S)
 690 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 691 {
 692         mtspr(SPRN_DABR, dabr);
 693         if (cpu_has_feature(CPU_FTR_DABRX))
 694                 mtspr(SPRN_DABRX, dabrx);
 695         return 0;
 696 }
 697 #else
 698 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 699 {
 700         return -EINVAL;
 701 }
 702 #endif
 703
 704 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 705 {
 706         unsigned long dabr, dabrx;
 707
 708         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 709         dabrx = ((brk->type >> 3) & 0x7);
 710
 711         if (ppc_md.set_dabr)
 712                 return ppc_md.set_dabr(dabr, dabrx);
 713
 714         return __set_dabr(dabr, dabrx);
 715 }
 716
 717 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 718 {
 719         unsigned long dawr, dawrx, mrd;
 720
 721         dawr = brk->address;
 722
 723         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 724                                    << (63 - 58); //* read/write bits */
 725         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 726                                    << (63 - 59); //* translate */
 727         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 728                                    >> 3; //* PRIM bits */
 729         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 730            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 731            0b111111=64DW.
 732            brk->len is in bytes.
 733            This aligns up to double word size, shifts and does the bias.
 734         */
 735         mrd = ((brk->len + 7) >> 3) - 1;
 736         dawrx |= (mrd & 0x3f) << (63 - 53);
 737
 738         if (ppc_md.set_dawr)
 739                 return ppc_md.set_dawr(dawr, dawrx);
 740         mtspr(SPRN_DAWR, dawr);
 741         mtspr(SPRN_DAWRX, dawrx);
 742         return 0;
 743 }
 744
 745 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 746 {
 747         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 748
 749         if (cpu_has_feature(CPU_FTR_DAWR))
 750                 set_dawr(brk);
 751         else
 752                 set_dabr(brk);
 753 }
 754
 755 void set_breakpoint(struct arch_hw_breakpoint *brk)
 756 {
 757         preempt_disable();
 758         __set_breakpoint(brk);
 759         preempt_enable();
 760 }
 761
 762 #ifdef CONFIG_PPC64
 763 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 764 #endif
 765
 766 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 767                               struct arch_hw_breakpoint *b)
 768 {
 769         if (a->address != b->address)
 770                 return false;
 771         if (a->type != b->type)
 772                 return false;
 773         if (a->len != b->len)
 774                 return false;
 775         return true;
 776 }
 777
 778 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 779 static void tm_reclaim_thread(struct thread_struct *thr,
 780                               struct thread_info *ti, uint8_t cause)
 781 {
 782         unsigned long msr_diff = 0;
 783
 784         /*
 785          * If FP/VSX registers have been already saved to the
 786          * thread_struct, move them to the transact_fp array.
 787          * We clear the TIF_RESTORE_TM bit since after the reclaim
 788          * the thread will no longer be transactional.
 789          */
 790         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 791                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 792                 if (msr_diff & MSR_FP)
 793                         memcpy(&thr->transact_fp, &thr->fp_state,
 794                                sizeof(struct thread_fp_state));
 795                 if (msr_diff & MSR_VEC)
 796                         memcpy(&thr->transact_vr, &thr->vr_state,
 797                                sizeof(struct thread_vr_state));
 798                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 799                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 800         }
 801
 802         /*
 803          * Use the current MSR TM suspended bit to track if we have
 804          * checkpointed state outstanding.
 805          * On signal delivery, we'd normally reclaim the checkpointed
 806          * state to obtain stack pointer (see:get_tm_stackpointer()).
 807          * This will then directly return to userspace without going
 808          * through __switch_to(). However, if the stack frame is bad,
 809          * we need to exit this thread which calls __switch_to() which
 810          * will again attempt to reclaim the already saved tm state.
 811          * Hence we need to check that we've not already reclaimed
 812          * this state.
 813          * We do this using the current MSR, rather tracking it in
 814          * some specific thread_struct bit, as it has the additional
 815          * benefit of checking for a potential TM bad thing exception.
 816          */
 817         if (!MSR_TM_SUSPENDED(mfmsr()))
 818                 return;
 819
 820         tm_reclaim(thr, thr->regs->msr, cause);
 821
 822         /* Having done the reclaim, we now have the checkpointed
 823          * FP/VSX values in the registers.  These might be valid
 824          * even if we have previously called enable_kernel_fp() or
 825          * flush_fp_to_thread(), so update thr->regs->msr to
 826          * indicate their current validity.
 827          */
 828         thr->regs->msr |= msr_diff;
 829 }
 830
 831 void tm_reclaim_current(uint8_t cause)
 832 {
 833         tm_enable();
 834         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 835 }
 836
 837 static inline void tm_reclaim_task(struct task_struct *tsk)
 838 {
 839         /* We have to work out if we're switching from/to a task that's in the
 840          * middle of a transaction.
 841          *
 842          * In switching we need to maintain a 2nd register state as
 843          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 844          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 845          * (current) FPRs into oldtask->thread.transact_fpr[].
 846          *
 847          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 848          */
 849         struct thread_struct *thr = &tsk->thread;
 850
 851         if (!thr->regs)
 852                 return;
 853
 854         if (!MSR_TM_ACTIVE(thr->regs->msr))
 855                 goto out_and_saveregs;
 856
 857         /* Stash the original thread MSR, as giveup_fpu et al will
 858          * modify it.  We hold onto it to see whether the task used
 859          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 860          * ckpt_regs.msr is already set.
 861          */
 862         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 863                 thr->ckpt_regs.msr = thr->regs->msr;
 864
 865         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 866                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 867                  tsk->pid, thr->regs->nip,
 868                  thr->regs->ccr, thr->regs->msr,
 869                  thr->regs->trap);
 870
 871         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 872
 873         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 874                  tsk->pid);
 875
 876 out_and_saveregs:
 877         /* Always save the regs here, even if a transaction's not active.
 878          * This context-switches a thread's TM info SPRs.  We do it here to
 879          * be consistent with the restore path (in recheckpoint) which
 880          * cannot happen later in _switch().
 881          */
 882         tm_save_sprs(thr);
 883 }
 884
 885 extern void __tm_recheckpoint(struct thread_struct *thread,
 886                               unsigned long orig_msr);
 887
 888 void tm_recheckpoint(struct thread_struct *thread,
 889                      unsigned long orig_msr)
 890 {
 891         unsigned long flags;
 892
 893         /* We really can't be interrupted here as the TEXASR registers can't
 894          * change and later in the trecheckpoint code, we have a userspace R1.
 895          * So let's hard disable over this region.
 896          */
 897         local_irq_save(flags);
 898         hard_irq_disable();
 899
 900         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 901          * before the trecheckpoint and no explosion occurs.
 902          */
 903         tm_restore_sprs(thread);
 904
 905         __tm_recheckpoint(thread, orig_msr);
 906
 907         local_irq_restore(flags);
 908 }
 909
 910 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 911 {
 912         unsigned long msr;
 913
 914         if (!cpu_has_feature(CPU_FTR_TM))
 915                 return;
 916
 917         /* Recheckpoint the registers of the thread we're about to switch to.
 918          *
 919          * If the task was using FP, we non-lazily reload both the original and
 920          * the speculative FP register states.  This is because the kernel
 921          * doesn't see if/when a TM rollback occurs, so if we take an FP
 922          * unavoidable later, we are unable to determine which set of FP regs
 923          * need to be restored.
 924          */
 925         if (!new->thread.regs)
 926                 return;
 927
 928         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 929                 tm_restore_sprs(&new->thread);
 930                 return;
 931         }
 932         msr = new->thread.ckpt_regs.msr;
 933         /* Recheckpoint to restore original checkpointed register state. */
 934         TM_DEBUG("*** tm_recheckpoint of pid %d "
 935                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 936                  new->pid, new->thread.regs->msr, msr);
 937
 938         /* This loads the checkpointed FP/VEC state, if used */
 939         tm_recheckpoint(&new->thread, msr);
 940
 941         /* This loads the speculative FP/VEC state, if used */
 942         if (msr & MSR_FP) {
 943                 do_load_up_transact_fpu(&new->thread);
 944                 new->thread.regs->msr |=
 945                         (MSR_FP | new->thread.fpexc_mode);
 946         }
 947 #ifdef CONFIG_ALTIVEC
 948         if (msr & MSR_VEC) {
 949                 do_load_up_transact_altivec(&new->thread);
 950                 new->thread.regs->msr |= MSR_VEC;
 951         }
 952 #endif
 953         /* We may as well turn on VSX too since all the state is restored now */
 954         if (msr & MSR_VSX)
 955                 new->thread.regs->msr |= MSR_VSX;
 956
 957         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 958                  "(kernel msr 0x%lx)\n",
 959                  new->pid, mfmsr());
 960 }
 961
 962 static inline void __switch_to_tm(struct task_struct *prev)
 963 {
 964         if (cpu_has_feature(CPU_FTR_TM)) {
 965                 tm_enable();
 966                 tm_reclaim_task(prev);
 967         }
 968 }
 969
 970 /*
 971  * This is called if we are on the way out to userspace and the
 972  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 973  * FP and/or vector state and does so if necessary.
 974  * If userspace is inside a transaction (whether active or
 975  * suspended) and FP/VMX/VSX instructions have ever been enabled
 976  * inside that transaction, then we have to keep them enabled
 977  * and keep the FP/VMX/VSX state loaded while ever the transaction
 978  * continues.  The reason is that if we didn't, and subsequently
 979  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 980  * we don't know whether it's the same transaction, and thus we
 981  * don't know which of the checkpointed state and the transactional
 982  * state to use.
 983  */
 984 void restore_tm_state(struct pt_regs *regs)
 985 {
 986         unsigned long msr_diff;
 987
 988         clear_thread_flag(TIF_RESTORE_TM);
 989         if (!MSR_TM_ACTIVE(regs->msr))
 990                 return;
 991
 992         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 993         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 994
 995         /* Ensure that restore_math() will restore */
 996         if (msr_diff & MSR_FP)
 997                 current->thread.load_fp = 1;
 998 #ifdef CONFIG_ALIVEC
 999         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1000                 current->thread.load_vec = 1;
1001 #endif
1002         restore_math(regs);
1003
1004         regs->msr |= msr_diff;
1005 }
1006
1007 #else
1008 #define tm_recheckpoint_new_task(new)
1009 #define __switch_to_tm(prev)
1010 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1011
1012 static inline void save_sprs(struct thread_struct *t)
1013 {
1014 #ifdef CONFIG_ALTIVEC
1015         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1016                 t->vrsave = mfspr(SPRN_VRSAVE);
1017 #endif
1018 #ifdef CONFIG_PPC_BOOK3S_64
1019         if (cpu_has_feature(CPU_FTR_DSCR))
1020                 t->dscr = mfspr(SPRN_DSCR);
1021
1022         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1023                 t->bescr = mfspr(SPRN_BESCR);
1024                 t->ebbhr = mfspr(SPRN_EBBHR);
1025                 t->ebbrr = mfspr(SPRN_EBBRR);
1026
1027                 t->fscr = mfspr(SPRN_FSCR);
1028
1029                 /*
1030                  * Note that the TAR is not available for use in the kernel.
1031                  * (To provide this, the TAR should be backed up/restored on
1032                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1033                  * this should be in pt_regs anyway (for debug).)
1034                  */
1035                 t->tar = mfspr(SPRN_TAR);
1036         }
1037
1038         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1039                 /* Conditionally save Load Monitor registers, if enabled */
1040                 if (t->fscr & FSCR_LM) {
1041                         t->lmrr = mfspr(SPRN_LMRR);
1042                         t->lmser = mfspr(SPRN_LMSER);
1043                 }
1044         }
1045 #endif
1046 }
1047
1048 static inline void restore_sprs(struct thread_struct *old_thread,
1049                                 struct thread_struct *new_thread)
1050 {
1051 #ifdef CONFIG_ALTIVEC
1052         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1053             old_thread->vrsave != new_thread->vrsave)
1054                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1055 #endif
1056 #ifdef CONFIG_PPC_BOOK3S_64
1057         if (cpu_has_feature(CPU_FTR_DSCR)) {
1058                 u64 dscr = get_paca()->dscr_default;
1059                 if (new_thread->dscr_inherit)
1060                         dscr = new_thread->dscr;
1061
1062                 if (old_thread->dscr != dscr)
1063                         mtspr(SPRN_DSCR, dscr);
1064         }
1065
1066         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1067                 if (old_thread->bescr != new_thread->bescr)
1068                         mtspr(SPRN_BESCR, new_thread->bescr);
1069                 if (old_thread->ebbhr != new_thread->ebbhr)
1070                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1071                 if (old_thread->ebbrr != new_thread->ebbrr)
1072                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1073
1074                 if (old_thread->fscr != new_thread->fscr)
1075                         mtspr(SPRN_FSCR, new_thread->fscr);
1076
1077                 if (old_thread->tar != new_thread->tar)
1078                         mtspr(SPRN_TAR, new_thread->tar);
1079         }
1080
1081         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1082                 /* Conditionally restore Load Monitor registers, if enabled */
1083                 if (new_thread->fscr & FSCR_LM) {
1084                         if (old_thread->lmrr != new_thread->lmrr)
1085                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1086                         if (old_thread->lmser != new_thread->lmser)
1087                                 mtspr(SPRN_LMSER, new_thread->lmser);
1088                 }
1089         }
1090 #endif
1091 }
1092
1093 struct task_struct *__switch_to(struct task_struct *prev,
1094         struct task_struct *new)
1095 {
1096         struct thread_struct *new_thread, *old_thread;
1097         struct task_struct *last;
1098 #ifdef CONFIG_PPC_BOOK3S_64
1099         struct ppc64_tlb_batch *batch;
1100 #endif
1101
1102         new_thread = &new->thread;
1103         old_thread = &current->thread;
1104
1105         WARN_ON(!irqs_disabled());
1106
1107 #ifdef CONFIG_PPC64
1108         /*
1109          * Collect processor utilization data per process
1110          */
1111         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1112                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1113                 long unsigned start_tb, current_tb;
1114                 start_tb = old_thread->start_tb;
1115                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1116                 old_thread->accum_tb += (current_tb - start_tb);
1117                 new_thread->start_tb = current_tb;
1118         }
1119 #endif /* CONFIG_PPC64 */
1120
1121 #ifdef CONFIG_PPC_STD_MMU_64
1122         batch = this_cpu_ptr(&ppc64_tlb_batch);
1123         if (batch->active) {
1124                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1125                 if (batch->index)
1126                         __flush_tlb_pending(batch);
1127                 batch->active = 0;
1128         }
1129 #endif /* CONFIG_PPC_STD_MMU_64 */
1130
1131 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1132         switch_booke_debug_regs(&new->thread.debug);
1133 #else
1134 /*
1135  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1136  * schedule DABR
1137  */
1138 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1139         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1140                 __set_breakpoint(&new->thread.hw_brk);
1141 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1142 #endif
1143
1144         /*
1145          * We need to save SPRs before treclaim/trecheckpoint as these will
1146          * change a number of them.
1147          */
1148         save_sprs(&prev->thread);
1149
1150         __switch_to_tm(prev);
1151
1152         /* Save FPU, Altivec, VSX and SPE state */
1153         giveup_all(prev);
1154
1155         /*
1156          * We can't take a PMU exception inside _switch() since there is a
1157          * window where the kernel stack SLB and the kernel stack are out
1158          * of sync. Hard disable here.
1159          */
1160         hard_irq_disable();
1161
1162         tm_recheckpoint_new_task(new);
1163
1164         /*
1165          * Call restore_sprs() before calling _switch(). If we move it after
1166          * _switch() then we miss out on calling it for new tasks. The reason
1167          * for this is we manually create a stack frame for new tasks that
1168          * directly returns through ret_from_fork() or
1169          * ret_from_kernel_thread(). See copy_thread() for details.
1170          */
1171         restore_sprs(old_thread, new_thread);
1172
1173         last = _switch(old_thread, new_thread);
1174
1175 #ifdef CONFIG_PPC_STD_MMU_64
1176         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1177                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1178                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1179                 batch->active = 1;
1180         }
1181
1182         if (current_thread_info()->task->thread.regs)
1183                 restore_math(current_thread_info()->task->thread.regs);
1184 #endif /* CONFIG_PPC_STD_MMU_64 */
1185
1186         return last;
1187 }
1188
1189 static int instructions_to_print = 16;
1190
1191 static void show_instructions(struct pt_regs *regs)
1192 {
1193         int i;
1194         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1195                         sizeof(int));
1196
1197         printk("Instruction dump:");
1198
1199         for (i = 0; i < instructions_to_print; i++) {
1200                 int instr;
1201
1202                 if (!(i % 8))
1203                         printk("\n");
1204
1205 #if !defined(CONFIG_BOOKE)
1206                 /* If executing with the IMMU off, adjust pc rather
1207                  * than print XXXXXXXX.
1208                  */
1209                 if (!(regs->msr & MSR_IR))
1210                         pc = (unsigned long)phys_to_virt(pc);
1211 #endif
1212
1213                 if (!__kernel_text_address(pc) ||
1214                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1215                         printk(KERN_CONT "XXXXXXXX ");
1216                 } else {
1217                         if (regs->nip == pc)
1218                                 printk(KERN_CONT "<%08x> ", instr);
1219                         else
1220                                 printk(KERN_CONT "%08x ", instr);
1221                 }
1222
1223                 pc += sizeof(int);
1224         }
1225
1226         printk("\n");
1227 }
1228
1229 struct regbit {
1230         unsigned long bit;
1231         const char *name;
1232 };
1233
1234 static struct regbit msr_bits[] = {
1235 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1236         {MSR_SF,        "SF"},
1237         {MSR_HV,        "HV"},
1238 #endif
1239         {MSR_VEC,       "VEC"},
1240         {MSR_VSX,       "VSX"},
1241 #ifdef CONFIG_BOOKE
1242         {MSR_CE,        "CE"},
1243 #endif
1244         {MSR_EE,        "EE"},
1245         {MSR_PR,        "PR"},
1246         {MSR_FP,        "FP"},
1247         {MSR_ME,        "ME"},
1248 #ifdef CONFIG_BOOKE
1249         {MSR_DE,        "DE"},
1250 #else
1251         {MSR_SE,        "SE"},
1252         {MSR_BE,        "BE"},
1253 #endif
1254         {MSR_IR,        "IR"},
1255         {MSR_DR,        "DR"},
1256         {MSR_PMM,       "PMM"},
1257 #ifndef CONFIG_BOOKE
1258         {MSR_RI,        "RI"},
1259         {MSR_LE,        "LE"},
1260 #endif
1261         {0,             NULL}
1262 };
1263
1264 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1265 {
1266         const char *s = "";
1267
1268         for (; bits->bit; ++bits)
1269                 if (val & bits->bit) {
1270                         printk("%s%s", s, bits->name);
1271                         s = sep;
1272                 }
1273 }
1274
1275 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1276 static struct regbit msr_tm_bits[] = {
1277         {MSR_TS_T,      "T"},
1278         {MSR_TS_S,      "S"},
1279         {MSR_TM,        "E"},
1280         {0,             NULL}
1281 };
1282
1283 static void print_tm_bits(unsigned long val)
1284 {
1285 /*
1286  * This only prints something if at least one of the TM bit is set.
1287  * Inside the TM[], the output means:
1288  *   E: Enabled         (bit 32)
1289  *   S: Suspended       (bit 33)
1290  *   T: Transactional   (bit 34)
1291  */
1292         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1293                 printk(",TM[");
1294                 print_bits(val, msr_tm_bits, "");
1295                 printk("]");
1296         }
1297 }
1298 #else
1299 static void print_tm_bits(unsigned long val) {}
1300 #endif
1301
1302 static void print_msr_bits(unsigned long val)
1303 {
1304         printk("<");
1305         print_bits(val, msr_bits, ",");
1306         print_tm_bits(val);
1307         printk(">");
1308 }
1309
1310 #ifdef CONFIG_PPC64
1311 #define REG             "%016lx"
1312 #define REGS_PER_LINE   4
1313 #define LAST_VOLATILE   13
1314 #else
1315 #define REG             "%08lx"
1316 #define REGS_PER_LINE   8
1317 #define LAST_VOLATILE   12
1318 #endif
1319
1320 void show_regs(struct pt_regs * regs)
1321 {
1322         int i, trap;
1323
1324         show_regs_print_info(KERN_DEFAULT);
1325
1326         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1327                regs->nip, regs->link, regs->ctr);
1328         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1329                regs, regs->trap, print_tainted(), init_utsname()->release);
1330         printk("MSR: "REG" ", regs->msr);
1331         print_msr_bits(regs->msr);
1332         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1333         trap = TRAP(regs);
1334         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1335                 printk("CFAR: "REG" ", regs->orig_gpr3);
1336         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1337 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1338                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1339 #else
1340                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1341 #endif
1342 #ifdef CONFIG_PPC64
1343         printk("SOFTE: %ld ", regs->softe);
1344 #endif
1345 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1346         if (MSR_TM_ACTIVE(regs->msr))
1347                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1348 #endif
1349
1350         for (i = 0;  i < 32;  i++) {
1351                 if ((i % REGS_PER_LINE) == 0)
1352                         printk("\nGPR%02d: ", i);
1353                 printk(REG " ", regs->gpr[i]);
1354                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1355                         break;
1356         }
1357         printk("\n");
1358 #ifdef CONFIG_KALLSYMS
1359         /*
1360          * Lookup NIP late so we have the best change of getting the
1361          * above info out without failing
1362          */
1363         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1364         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1365 #endif
1366         show_stack(current, (unsigned long *) regs->gpr[1]);
1367         if (!user_mode(regs))
1368                 show_instructions(regs);
1369 }
1370
1371 void flush_thread(void)
1372 {
1373 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1374         flush_ptrace_hw_breakpoint(current);
1375 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1376         set_debug_reg_defaults(&current->thread);
1377 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1378 }
1379
1380 void
1381 release_thread(struct task_struct *t)
1382 {
1383 }
1384
1385 /*
1386  * this gets called so that we can store coprocessor state into memory and
1387  * copy the current task into the new thread.
1388  */
1389 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1390 {
1391         flush_all_to_thread(src);
1392         /*
1393          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1394          * flush but it removes the checkpointed state from the current CPU and
1395          * transitions the CPU out of TM mode.  Hence we need to call
1396          * tm_recheckpoint_new_task() (on the same task) to restore the
1397          * checkpointed state back and the TM mode.
1398          */
1399         __switch_to_tm(src);
1400         tm_recheckpoint_new_task(src);
1401
1402         *dst = *src;
1403
1404         clear_task_ebb(dst);
1405
1406         return 0;
1407 }
1408
1409 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1410 {
1411 #ifdef CONFIG_PPC_STD_MMU_64
1412         unsigned long sp_vsid;
1413         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1414
1415         if (radix_enabled())
1416                 return;
1417
1418         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1419                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1420                         << SLB_VSID_SHIFT_1T;
1421         else
1422                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1423                         << SLB_VSID_SHIFT;
1424         sp_vsid |= SLB_VSID_KERNEL | llp;
1425         p->thread.ksp_vsid = sp_vsid;
1426 #endif
1427 }
1428
1429 /*
1430  * Copy a thread..
1431  */
1432
1433 /*
1434  * Copy architecture-specific thread state
1435  */
1436 int copy_thread(unsigned long clone_flags, unsigned long usp,
1437                 unsigned long kthread_arg, struct task_struct *p)
1438 {
1439         struct pt_regs *childregs, *kregs;
1440         extern void ret_from_fork(void);
1441         extern void ret_from_kernel_thread(void);
1442         void (*f)(void);
1443         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1444         struct thread_info *ti = task_thread_info(p);
1445
1446         klp_init_thread_info(ti);
1447
1448         /* Copy registers */
1449         sp -= sizeof(struct pt_regs);
1450         childregs = (struct pt_regs *) sp;
1451         if (unlikely(p->flags & PF_KTHREAD)) {
1452                 /* kernel thread */
1453                 memset(childregs, 0, sizeof(struct pt_regs));
1454                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1455                 /* function */
1456                 if (usp)
1457                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1458 #ifdef CONFIG_PPC64
1459                 clear_tsk_thread_flag(p, TIF_32BIT);
1460                 childregs->softe = 1;
1461 #endif
1462                 childregs->gpr[15] = kthread_arg;
1463                 p->thread.regs = NULL;  /* no user register state */
1464                 ti->flags |= _TIF_RESTOREALL;
1465                 f = ret_from_kernel_thread;
1466         } else {
1467                 /* user thread */
1468                 struct pt_regs *regs = current_pt_regs();
1469                 CHECK_FULL_REGS(regs);
1470                 *childregs = *regs;
1471                 if (usp)
1472                         childregs->gpr[1] = usp;
1473                 p->thread.regs = childregs;
1474                 childregs->gpr[3] = 0;  /* Result from fork() */
1475                 if (clone_flags & CLONE_SETTLS) {
1476 #ifdef CONFIG_PPC64
1477                         if (!is_32bit_task())
1478                                 childregs->gpr[13] = childregs->gpr[6];
1479                         else
1480 #endif
1481                                 childregs->gpr[2] = childregs->gpr[6];
1482                 }
1483
1484                 f = ret_from_fork;
1485         }
1486         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1487         sp -= STACK_FRAME_OVERHEAD;
1488
1489         /*
1490          * The way this works is that at some point in the future
1491          * some task will call _switch to switch to the new task.
1492          * That will pop off the stack frame created below and start
1493          * the new task running at ret_from_fork.  The new task will
1494          * do some house keeping and then return from the fork or clone
1495          * system call, using the stack frame created above.
1496          */
1497         ((unsigned long *)sp)[0] = 0;
1498         sp -= sizeof(struct pt_regs);
1499         kregs = (struct pt_regs *) sp;
1500         sp -= STACK_FRAME_OVERHEAD;
1501         p->thread.ksp = sp;
1502 #ifdef CONFIG_PPC32
1503         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1504                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1505 #endif
1506 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1507         p->thread.ptrace_bps[0] = NULL;
1508 #endif
1509
1510         p->thread.fp_save_area = NULL;
1511 #ifdef CONFIG_ALTIVEC
1512         p->thread.vr_save_area = NULL;
1513 #endif
1514
1515         setup_ksp_vsid(p, sp);
1516
1517 #ifdef CONFIG_PPC64
1518         if (cpu_has_feature(CPU_FTR_DSCR)) {
1519                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1520                 p->thread.dscr = mfspr(SPRN_DSCR);
1521         }
1522         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1523                 p->thread.ppr = INIT_PPR;
1524 #endif
1525         kregs->nip = ppc_function_entry(f);
1526         return 0;
1527 }
1528
1529 /*
1530  * Set up a thread for executing a new program
1531  */
1532 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1533 {
1534 #ifdef CONFIG_PPC64
1535         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1536 #endif
1537
1538         /*
1539          * If we exec out of a kernel thread then thread.regs will not be
1540          * set.  Do it now.
1541          */
1542         if (!current->thread.regs) {
1543                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1544                 current->thread.regs = regs - 1;
1545         }
1546
1547 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1548         /*
1549          * Clear any transactional state, we're exec()ing. The cause is
1550          * not important as there will never be a recheckpoint so it's not
1551          * user visible.
1552          */
1553         if (MSR_TM_SUSPENDED(mfmsr()))
1554                 tm_reclaim_current(0);
1555 #endif
1556
1557         memset(regs->gpr, 0, sizeof(regs->gpr));
1558         regs->ctr = 0;
1559         regs->link = 0;
1560         regs->xer = 0;
1561         regs->ccr = 0;
1562         regs->gpr[1] = sp;
1563
1564         /*
1565          * We have just cleared all the nonvolatile GPRs, so make
1566          * FULL_REGS(regs) return true.  This is necessary to allow
1567          * ptrace to examine the thread immediately after exec.
1568          */
1569         regs->trap &= ~1UL;
1570
1571 #ifdef CONFIG_PPC32
1572         regs->mq = 0;
1573         regs->nip = start;
1574         regs->msr = MSR_USER;
1575 #else
1576         if (!is_32bit_task()) {
1577                 unsigned long entry;
1578
1579                 if (is_elf2_task()) {
1580                         /* Look ma, no function descriptors! */
1581                         entry = start;
1582
1583                         /*
1584                          * Ulrich says:
1585                          *   The latest iteration of the ABI requires that when
1586                          *   calling a function (at its global entry point),
1587                          *   the caller must ensure r12 holds the entry point
1588                          *   address (so that the function can quickly
1589                          *   establish addressability).
1590                          */
1591                         regs->gpr[12] = start;
1592                         /* Make sure that's restored on entry to userspace. */
1593                         set_thread_flag(TIF_RESTOREALL);
1594                 } else {
1595                         unsigned long toc;
1596
1597                         /* start is a relocated pointer to the function
1598                          * descriptor for the elf _start routine.  The first
1599                          * entry in the function descriptor is the entry
1600                          * address of _start and the second entry is the TOC
1601                          * value we need to use.
1602                          */
1603                         __get_user(entry, (unsigned long __user *)start);
1604                         __get_user(toc, (unsigned long __user *)start+1);
1605
1606                         /* Check whether the e_entry function descriptor entries
1607                          * need to be relocated before we can use them.
1608                          */
1609                         if (load_addr != 0) {
1610                                 entry += load_addr;
1611                                 toc   += load_addr;
1612                         }
1613                         regs->gpr[2] = toc;
1614                 }
1615                 regs->nip = entry;
1616                 regs->msr = MSR_USER64;
1617         } else {
1618                 regs->nip = start;
1619                 regs->gpr[2] = 0;
1620                 regs->msr = MSR_USER32;
1621         }
1622 #endif
1623 #ifdef CONFIG_VSX
1624         current->thread.used_vsr = 0;
1625 #endif
1626         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1627         current->thread.fp_save_area = NULL;
1628 #ifdef CONFIG_ALTIVEC
1629         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1630         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1631         current->thread.vr_save_area = NULL;
1632         current->thread.vrsave = 0;
1633         current->thread.used_vr = 0;
1634 #endif /* CONFIG_ALTIVEC */
1635 #ifdef CONFIG_SPE
1636         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1637         current->thread.acc = 0;
1638         current->thread.spefscr = 0;
1639         current->thread.used_spe = 0;
1640 #endif /* CONFIG_SPE */
1641 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1642         if (cpu_has_feature(CPU_FTR_TM))
1643                 regs->msr |= MSR_TM;
1644         current->thread.tm_tfhar = 0;
1645         current->thread.tm_texasr = 0;
1646         current->thread.tm_tfiar = 0;
1647 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1648 }
1649 EXPORT_SYMBOL(start_thread);
1650
1651 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1652                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1653
1654 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1655 {
1656         struct pt_regs *regs = tsk->thread.regs;
1657
1658         /* This is a bit hairy.  If we are an SPE enabled  processor
1659          * (have embedded fp) we store the IEEE exception enable flags in
1660          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1661          * mode (asyn, precise, disabled) for 'Classic' FP. */
1662         if (val & PR_FP_EXC_SW_ENABLE) {
1663 #ifdef CONFIG_SPE
1664                 if (cpu_has_feature(CPU_FTR_SPE)) {
1665                         /*
1666                          * When the sticky exception bits are set
1667                          * directly by userspace, it must call prctl
1668                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1669                          * in the existing prctl settings) or
1670                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1671                          * the bits being set).  <fenv.h> functions
1672                          * saving and restoring the whole
1673                          * floating-point environment need to do so
1674                          * anyway to restore the prctl settings from
1675                          * the saved environment.
1676                          */
1677                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1678                         tsk->thread.fpexc_mode = val &
1679                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1680                         return 0;
1681                 } else {
1682                         return -EINVAL;
1683                 }
1684 #else
1685                 return -EINVAL;
1686 #endif
1687         }
1688
1689         /* on a CONFIG_SPE this does not hurt us.  The bits that
1690          * __pack_fe01 use do not overlap with bits used for
1691          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1692          * on CONFIG_SPE implementations are reserved so writing to
1693          * them does not change anything */
1694         if (val > PR_FP_EXC_PRECISE)
1695                 return -EINVAL;
1696         tsk->thread.fpexc_mode = __pack_fe01(val);
1697         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1698                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1699                         | tsk->thread.fpexc_mode;
1700         return 0;
1701 }
1702
1703 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1704 {
1705         unsigned int val;
1706
1707         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1708 #ifdef CONFIG_SPE
1709                 if (cpu_has_feature(CPU_FTR_SPE)) {
1710                         /*
1711                          * When the sticky exception bits are set
1712                          * directly by userspace, it must call prctl
1713                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1714                          * in the existing prctl settings) or
1715                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1716                          * the bits being set).  <fenv.h> functions
1717                          * saving and restoring the whole
1718                          * floating-point environment need to do so
1719                          * anyway to restore the prctl settings from
1720                          * the saved environment.
1721                          */
1722                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1723                         val = tsk->thread.fpexc_mode;
1724                 } else
1725                         return -EINVAL;
1726 #else
1727                 return -EINVAL;
1728 #endif
1729         else
1730                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1731         return put_user(val, (unsigned int __user *) adr);
1732 }
1733
1734 int set_endian(struct task_struct *tsk, unsigned int val)
1735 {
1736         struct pt_regs *regs = tsk->thread.regs;
1737
1738         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1739             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1740                 return -EINVAL;
1741
1742         if (regs == NULL)
1743                 return -EINVAL;
1744
1745         if (val == PR_ENDIAN_BIG)
1746                 regs->msr &= ~MSR_LE;
1747         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1748                 regs->msr |= MSR_LE;
1749         else
1750                 return -EINVAL;
1751
1752         return 0;
1753 }
1754
1755 int get_endian(struct task_struct *tsk, unsigned long adr)
1756 {
1757         struct pt_regs *regs = tsk->thread.regs;
1758         unsigned int val;
1759
1760         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1761             !cpu_has_feature(CPU_FTR_REAL_LE))
1762                 return -EINVAL;
1763
1764         if (regs == NULL)
1765                 return -EINVAL;
1766
1767         if (regs->msr & MSR_LE) {
1768                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1769                         val = PR_ENDIAN_LITTLE;
1770                 else
1771                         val = PR_ENDIAN_PPC_LITTLE;
1772         } else
1773                 val = PR_ENDIAN_BIG;
1774
1775         return put_user(val, (unsigned int __user *)adr);
1776 }
1777
1778 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1779 {
1780         tsk->thread.align_ctl = val;
1781         return 0;
1782 }
1783
1784 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1785 {
1786         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1787 }
1788
1789 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1790                                   unsigned long nbytes)
1791 {
1792         unsigned long stack_page;
1793         unsigned long cpu = task_cpu(p);
1794
1795         /*
1796          * Avoid crashing if the stack has overflowed and corrupted
1797          * task_cpu(p), which is in the thread_info struct.
1798          */
1799         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1800                 stack_page = (unsigned long) hardirq_ctx[cpu];
1801                 if (sp >= stack_page + sizeof(struct thread_struct)
1802                     && sp <= stack_page + THREAD_SIZE - nbytes)
1803                         return 1;
1804
1805                 stack_page = (unsigned long) softirq_ctx[cpu];
1806                 if (sp >= stack_page + sizeof(struct thread_struct)
1807                     && sp <= stack_page + THREAD_SIZE - nbytes)
1808                         return 1;
1809         }
1810         return 0;
1811 }
1812
1813 int validate_sp(unsigned long sp, struct task_struct *p,
1814                        unsigned long nbytes)
1815 {
1816         unsigned long stack_page = (unsigned long)task_stack_page(p);
1817
1818         if (sp >= stack_page + sizeof(struct thread_struct)
1819             && sp <= stack_page + THREAD_SIZE - nbytes)
1820                 return 1;
1821
1822         return valid_irq_stack(sp, p, nbytes);
1823 }
1824
1825 EXPORT_SYMBOL(validate_sp);
1826
1827 unsigned long get_wchan(struct task_struct *p)
1828 {
1829         unsigned long ip, sp;
1830         int count = 0;
1831
1832         if (!p || p == current || p->state == TASK_RUNNING)
1833                 return 0;
1834
1835         sp = p->thread.ksp;
1836         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1837                 return 0;
1838
1839         do {
1840                 sp = *(unsigned long *)sp;
1841                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1842                         return 0;
1843                 if (count > 0) {
1844                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1845                         if (!in_sched_functions(ip))
1846                                 return ip;
1847                 }
1848         } while (count++ < 16);
1849         return 0;
1850 }
1851
1852 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1853
1854 void show_stack(struct task_struct *tsk, unsigned long *stack)
1855 {
1856         unsigned long sp, ip, lr, newsp;
1857         int count = 0;
1858         int firstframe = 1;
1859 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1860         int curr_frame = current->curr_ret_stack;
1861         extern void return_to_handler(void);
1862         unsigned long rth = (unsigned long)return_to_handler;
1863 #endif
1864
1865         sp = (unsigned long) stack;
1866         if (tsk == NULL)
1867                 tsk = current;
1868         if (sp == 0) {
1869                 if (tsk == current)
1870                         sp = current_stack_pointer();
1871                 else
1872                         sp = tsk->thread.ksp;
1873         }
1874
1875         lr = 0;
1876         printk("Call Trace:\n");
1877         do {
1878                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1879                         return;
1880
1881                 stack = (unsigned long *) sp;
1882                 newsp = stack[0];
1883                 ip = stack[STACK_FRAME_LR_SAVE];
1884                 if (!firstframe || ip != lr) {
1885                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1886 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1887                         if ((ip == rth) && curr_frame >= 0) {
1888                                 printk(" (%pS)",
1889                                        (void *)current->ret_stack[curr_frame].ret);
1890                                 curr_frame--;
1891                         }
1892 #endif
1893                         if (firstframe)
1894                                 printk(" (unreliable)");
1895                         printk("\n");
1896                 }
1897                 firstframe = 0;
1898
1899                 /*
1900                  * See if this is an exception frame.
1901                  * We look for the "regshere" marker in the current frame.
1902                  */
1903                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1904                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1905                         struct pt_regs *regs = (struct pt_regs *)
1906                                 (sp + STACK_FRAME_OVERHEAD);
1907                         lr = regs->link;
1908                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1909                                regs->trap, (void *)regs->nip, (void *)lr);
1910                         firstframe = 1;
1911                 }
1912
1913                 sp = newsp;
1914         } while (count++ < kstack_depth_to_print);
1915 }
1916
1917 #ifdef CONFIG_PPC64
1918 /* Called with hard IRQs off */
1919 void notrace __ppc64_runlatch_on(void)
1920 {
1921         struct thread_info *ti = current_thread_info();
1922         unsigned long ctrl;
1923
1924         ctrl = mfspr(SPRN_CTRLF);
1925         ctrl |= CTRL_RUNLATCH;
1926         mtspr(SPRN_CTRLT, ctrl);
1927
1928         ti->local_flags |= _TLF_RUNLATCH;
1929 }
1930
1931 /* Called with hard IRQs off */
1932 void notrace __ppc64_runlatch_off(void)
1933 {
1934         struct thread_info *ti = current_thread_info();
1935         unsigned long ctrl;
1936
1937         ti->local_flags &= ~_TLF_RUNLATCH;
1938
1939         ctrl = mfspr(SPRN_CTRLF);
1940         ctrl &= ~CTRL_RUNLATCH;
1941         mtspr(SPRN_CTRLT, ctrl);
1942 }
1943 #endif /* CONFIG_PPC64 */
1944
1945 unsigned long arch_align_stack(unsigned long sp)
1946 {
1947         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1948                 sp -= get_random_int() & ~PAGE_MASK;
1949         return sp & ~0xf;
1950 }
1951
1952 static inline unsigned long brk_rnd(void)
1953 {
1954         unsigned long rnd = 0;
1955
1956         /* 8MB for 32bit, 1GB for 64bit */
1957         if (is_32bit_task())
1958                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1959         else
1960                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1961
1962         return rnd << PAGE_SHIFT;
1963 }
1964
1965 unsigned long arch_randomize_brk(struct mm_struct *mm)
1966 {
1967         unsigned long base = mm->brk;
1968         unsigned long ret;
1969
1970 #ifdef CONFIG_PPC_STD_MMU_64
1971         /*
1972          * If we are using 1TB segments and we are allowed to randomise
1973          * the heap, we can put it above 1TB so it is backed by a 1TB
1974          * segment. Otherwise the heap will be in the bottom 1TB
1975          * which always uses 256MB segments and this may result in a
1976          * performance penalty. We don't need to worry about radix. For
1977          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1978          */
1979         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1980                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1981 #endif
1982
1983         ret = PAGE_ALIGN(base + brk_rnd());
1984
1985         if (ret < mm->brk)
1986                 return mm->brk;
1987
1988         return ret;
1989 }
1990