arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 void msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128 }
 129
 130 void __msr_check_and_clear(unsigned long bits)
 131 {
 132         unsigned long oldmsr = mfmsr();
 133         unsigned long newmsr;
 134
 135         newmsr = oldmsr & ~bits;
 136
 137 #ifdef CONFIG_VSX
 138         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 139                 newmsr &= ~MSR_VSX;
 140 #endif
 141
 142         if (oldmsr != newmsr)
 143                 mtmsr_isync(newmsr);
 144 }
 145 EXPORT_SYMBOL(__msr_check_and_clear);
 146
 147 #ifdef CONFIG_PPC_FPU
 148 void __giveup_fpu(struct task_struct *tsk)
 149 {
 150         unsigned long msr;
 151
 152         save_fpu(tsk);
 153         msr = tsk->thread.regs->msr;
 154         msr &= ~MSR_FP;
 155 #ifdef CONFIG_VSX
 156         if (cpu_has_feature(CPU_FTR_VSX))
 157                 msr &= ~MSR_VSX;
 158 #endif
 159         tsk->thread.regs->msr = msr;
 160 }
 161
 162 void giveup_fpu(struct task_struct *tsk)
 163 {
 164         check_if_tm_restore_required(tsk);
 165
 166         msr_check_and_set(MSR_FP);
 167         __giveup_fpu(tsk);
 168         msr_check_and_clear(MSR_FP);
 169 }
 170 EXPORT_SYMBOL(giveup_fpu);
 171
 172 /*
 173  * Make sure the floating-point register state in the
 174  * the thread_struct is up to date for task tsk.
 175  */
 176 void flush_fp_to_thread(struct task_struct *tsk)
 177 {
 178         if (tsk->thread.regs) {
 179                 /*
 180                  * We need to disable preemption here because if we didn't,
 181                  * another process could get scheduled after the regs->msr
 182                  * test but before we have finished saving the FP registers
 183                  * to the thread_struct.  That process could take over the
 184                  * FPU, and then when we get scheduled again we would store
 185                  * bogus values for the remaining FP registers.
 186                  */
 187                 preempt_disable();
 188                 if (tsk->thread.regs->msr & MSR_FP) {
 189                         /*
 190                          * This should only ever be called for current or
 191                          * for a stopped child process.  Since we save away
 192                          * the FP register state on context switch,
 193                          * there is something wrong if a stopped child appears
 194                          * to still have its FP state in the CPU registers.
 195                          */
 196                         BUG_ON(tsk != current);
 197                         giveup_fpu(tsk);
 198                 }
 199                 preempt_enable();
 200         }
 201 }
 202 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 203
 204 void enable_kernel_fp(void)
 205 {
 206         WARN_ON(preemptible());
 207
 208         msr_check_and_set(MSR_FP);
 209
 210         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 211                 check_if_tm_restore_required(current);
 212                 __giveup_fpu(current);
 213         }
 214 }
 215 EXPORT_SYMBOL(enable_kernel_fp);
 216
 217 static int restore_fp(struct task_struct *tsk) {
 218         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 219                 load_fp_state(&current->thread.fp_state);
 220                 current->thread.load_fp++;
 221                 return 1;
 222         }
 223         return 0;
 224 }
 225 #else
 226 static int restore_fp(struct task_struct *tsk) { return 0; }
 227 #endif /* CONFIG_PPC_FPU */
 228
 229 #ifdef CONFIG_ALTIVEC
 230 #define loadvec(thr) ((thr).load_vec)
 231
 232 static void __giveup_altivec(struct task_struct *tsk)
 233 {
 234         unsigned long msr;
 235
 236         save_altivec(tsk);
 237         msr = tsk->thread.regs->msr;
 238         msr &= ~MSR_VEC;
 239 #ifdef CONFIG_VSX
 240         if (cpu_has_feature(CPU_FTR_VSX))
 241                 msr &= ~MSR_VSX;
 242 #endif
 243         tsk->thread.regs->msr = msr;
 244 }
 245
 246 void giveup_altivec(struct task_struct *tsk)
 247 {
 248         check_if_tm_restore_required(tsk);
 249
 250         msr_check_and_set(MSR_VEC);
 251         __giveup_altivec(tsk);
 252         msr_check_and_clear(MSR_VEC);
 253 }
 254 EXPORT_SYMBOL(giveup_altivec);
 255
 256 void enable_kernel_altivec(void)
 257 {
 258         WARN_ON(preemptible());
 259
 260         msr_check_and_set(MSR_VEC);
 261
 262         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 263                 check_if_tm_restore_required(current);
 264                 __giveup_altivec(current);
 265         }
 266 }
 267 EXPORT_SYMBOL(enable_kernel_altivec);
 268
 269 /*
 270  * Make sure the VMX/Altivec register state in the
 271  * the thread_struct is up to date for task tsk.
 272  */
 273 void flush_altivec_to_thread(struct task_struct *tsk)
 274 {
 275         if (tsk->thread.regs) {
 276                 preempt_disable();
 277                 if (tsk->thread.regs->msr & MSR_VEC) {
 278                         BUG_ON(tsk != current);
 279                         giveup_altivec(tsk);
 280                 }
 281                 preempt_enable();
 282         }
 283 }
 284 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 285
 286 static int restore_altivec(struct task_struct *tsk)
 287 {
 288         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 289                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 290                 load_vr_state(&tsk->thread.vr_state);
 291                 tsk->thread.used_vr = 1;
 292                 tsk->thread.load_vec++;
 293
 294                 return 1;
 295         }
 296         return 0;
 297 }
 298 #else
 299 #define loadvec(thr) 0
 300 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 301 #endif /* CONFIG_ALTIVEC */
 302
 303 #ifdef CONFIG_VSX
 304 static void __giveup_vsx(struct task_struct *tsk)
 305 {
 306         if (tsk->thread.regs->msr & MSR_FP)
 307                 __giveup_fpu(tsk);
 308         if (tsk->thread.regs->msr & MSR_VEC)
 309                 __giveup_altivec(tsk);
 310         tsk->thread.regs->msr &= ~MSR_VSX;
 311 }
 312
 313 static void giveup_vsx(struct task_struct *tsk)
 314 {
 315         check_if_tm_restore_required(tsk);
 316
 317         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 318         __giveup_vsx(tsk);
 319         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 320 }
 321
 322 static void save_vsx(struct task_struct *tsk)
 323 {
 324         if (tsk->thread.regs->msr & MSR_FP)
 325                 save_fpu(tsk);
 326         if (tsk->thread.regs->msr & MSR_VEC)
 327                 save_altivec(tsk);
 328 }
 329
 330 void enable_kernel_vsx(void)
 331 {
 332         WARN_ON(preemptible());
 333
 334         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 335
 336         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 337                 check_if_tm_restore_required(current);
 338                 if (current->thread.regs->msr & MSR_FP)
 339                         __giveup_fpu(current);
 340                 if (current->thread.regs->msr & MSR_VEC)
 341                         __giveup_altivec(current);
 342                 __giveup_vsx(current);
 343         }
 344 }
 345 EXPORT_SYMBOL(enable_kernel_vsx);
 346
 347 void flush_vsx_to_thread(struct task_struct *tsk)
 348 {
 349         if (tsk->thread.regs) {
 350                 preempt_disable();
 351                 if (tsk->thread.regs->msr & MSR_VSX) {
 352                         BUG_ON(tsk != current);
 353                         giveup_vsx(tsk);
 354                 }
 355                 preempt_enable();
 356         }
 357 }
 358 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 359
 360 static int restore_vsx(struct task_struct *tsk)
 361 {
 362         if (cpu_has_feature(CPU_FTR_VSX)) {
 363                 tsk->thread.used_vsr = 1;
 364                 return 1;
 365         }
 366
 367         return 0;
 368 }
 369 #else
 370 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 371 static inline void save_vsx(struct task_struct *tsk) { }
 372 #endif /* CONFIG_VSX */
 373
 374 #ifdef CONFIG_SPE
 375 void giveup_spe(struct task_struct *tsk)
 376 {
 377         check_if_tm_restore_required(tsk);
 378
 379         msr_check_and_set(MSR_SPE);
 380         __giveup_spe(tsk);
 381         msr_check_and_clear(MSR_SPE);
 382 }
 383 EXPORT_SYMBOL(giveup_spe);
 384
 385 void enable_kernel_spe(void)
 386 {
 387         WARN_ON(preemptible());
 388
 389         msr_check_and_set(MSR_SPE);
 390
 391         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 392                 check_if_tm_restore_required(current);
 393                 __giveup_spe(current);
 394         }
 395 }
 396 EXPORT_SYMBOL(enable_kernel_spe);
 397
 398 void flush_spe_to_thread(struct task_struct *tsk)
 399 {
 400         if (tsk->thread.regs) {
 401                 preempt_disable();
 402                 if (tsk->thread.regs->msr & MSR_SPE) {
 403                         BUG_ON(tsk != current);
 404                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 405                         giveup_spe(tsk);
 406                 }
 407                 preempt_enable();
 408         }
 409 }
 410 #endif /* CONFIG_SPE */
 411
 412 static unsigned long msr_all_available;
 413
 414 static int __init init_msr_all_available(void)
 415 {
 416 #ifdef CONFIG_PPC_FPU
 417         msr_all_available |= MSR_FP;
 418 #endif
 419 #ifdef CONFIG_ALTIVEC
 420         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 421                 msr_all_available |= MSR_VEC;
 422 #endif
 423 #ifdef CONFIG_VSX
 424         if (cpu_has_feature(CPU_FTR_VSX))
 425                 msr_all_available |= MSR_VSX;
 426 #endif
 427 #ifdef CONFIG_SPE
 428         if (cpu_has_feature(CPU_FTR_SPE))
 429                 msr_all_available |= MSR_SPE;
 430 #endif
 431
 432         return 0;
 433 }
 434 early_initcall(init_msr_all_available);
 435
 436 void giveup_all(struct task_struct *tsk)
 437 {
 438         unsigned long usermsr;
 439
 440         if (!tsk->thread.regs)
 441                 return;
 442
 443         usermsr = tsk->thread.regs->msr;
 444
 445         if ((usermsr & msr_all_available) == 0)
 446                 return;
 447
 448         msr_check_and_set(msr_all_available);
 449         check_if_tm_restore_required(tsk);
 450
 451 #ifdef CONFIG_PPC_FPU
 452         if (usermsr & MSR_FP)
 453                 __giveup_fpu(tsk);
 454 #endif
 455 #ifdef CONFIG_ALTIVEC
 456         if (usermsr & MSR_VEC)
 457                 __giveup_altivec(tsk);
 458 #endif
 459 #ifdef CONFIG_VSX
 460         if (usermsr & MSR_VSX)
 461                 __giveup_vsx(tsk);
 462 #endif
 463 #ifdef CONFIG_SPE
 464         if (usermsr & MSR_SPE)
 465                 __giveup_spe(tsk);
 466 #endif
 467
 468         msr_check_and_clear(msr_all_available);
 469 }
 470 EXPORT_SYMBOL(giveup_all);
 471
 472 void restore_math(struct pt_regs *regs)
 473 {
 474         unsigned long msr;
 475
 476         if (!msr_tm_active(regs->msr) &&
 477                 !current->thread.load_fp && !loadvec(current->thread))
 478                 return;
 479
 480         msr = regs->msr;
 481         msr_check_and_set(msr_all_available);
 482
 483         /*
 484          * Only reload if the bit is not set in the user MSR, the bit BEING set
 485          * indicates that the registers are hot
 486          */
 487         if ((!(msr & MSR_FP)) && restore_fp(current))
 488                 msr |= MSR_FP | current->thread.fpexc_mode;
 489
 490         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 491                 msr |= MSR_VEC;
 492
 493         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 494                         restore_vsx(current)) {
 495                 msr |= MSR_VSX;
 496         }
 497
 498         msr_check_and_clear(msr_all_available);
 499
 500         regs->msr = msr;
 501 }
 502
 503 void save_all(struct task_struct *tsk)
 504 {
 505         unsigned long usermsr;
 506
 507         if (!tsk->thread.regs)
 508                 return;
 509
 510         usermsr = tsk->thread.regs->msr;
 511
 512         if ((usermsr & msr_all_available) == 0)
 513                 return;
 514
 515         msr_check_and_set(msr_all_available);
 516
 517         /*
 518          * Saving the way the register space is in hardware, save_vsx boils
 519          * down to a save_fpu() and save_altivec()
 520          */
 521         if (usermsr & MSR_VSX) {
 522                 save_vsx(tsk);
 523         } else {
 524                 if (usermsr & MSR_FP)
 525                         save_fpu(tsk);
 526
 527                 if (usermsr & MSR_VEC)
 528                         save_altivec(tsk);
 529         }
 530
 531         if (usermsr & MSR_SPE)
 532                 __giveup_spe(tsk);
 533
 534         msr_check_and_clear(msr_all_available);
 535 }
 536
 537 void flush_all_to_thread(struct task_struct *tsk)
 538 {
 539         if (tsk->thread.regs) {
 540                 preempt_disable();
 541                 BUG_ON(tsk != current);
 542                 save_all(tsk);
 543
 544 #ifdef CONFIG_SPE
 545                 if (tsk->thread.regs->msr & MSR_SPE)
 546                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 547 #endif
 548
 549                 preempt_enable();
 550         }
 551 }
 552 EXPORT_SYMBOL(flush_all_to_thread);
 553
 554 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 555 void do_send_trap(struct pt_regs *regs, unsigned long address,
 556                   unsigned long error_code, int signal_code, int breakpt)
 557 {
 558         siginfo_t info;
 559
 560         current->thread.trap_nr = signal_code;
 561         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 562                         11, SIGSEGV) == NOTIFY_STOP)
 563                 return;
 564
 565         /* Deliver the signal to userspace */
 566         info.si_signo = SIGTRAP;
 567         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 568         info.si_code = signal_code;
 569         info.si_addr = (void __user *)address;
 570         force_sig_info(SIGTRAP, &info, current);
 571 }
 572 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 573 void do_break (struct pt_regs *regs, unsigned long address,
 574                     unsigned long error_code)
 575 {
 576         siginfo_t info;
 577
 578         current->thread.trap_nr = TRAP_HWBKPT;
 579         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 580                         11, SIGSEGV) == NOTIFY_STOP)
 581                 return;
 582
 583         if (debugger_break_match(regs))
 584                 return;
 585
 586         /* Clear the breakpoint */
 587         hw_breakpoint_disable();
 588
 589         /* Deliver the signal to userspace */
 590         info.si_signo = SIGTRAP;
 591         info.si_errno = 0;
 592         info.si_code = TRAP_HWBKPT;
 593         info.si_addr = (void __user *)address;
 594         force_sig_info(SIGTRAP, &info, current);
 595 }
 596 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 597
 598 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 599
 600 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 601 /*
 602  * Set the debug registers back to their default "safe" values.
 603  */
 604 static void set_debug_reg_defaults(struct thread_struct *thread)
 605 {
 606         thread->debug.iac1 = thread->debug.iac2 = 0;
 607 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 608         thread->debug.iac3 = thread->debug.iac4 = 0;
 609 #endif
 610         thread->debug.dac1 = thread->debug.dac2 = 0;
 611 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 612         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 613 #endif
 614         thread->debug.dbcr0 = 0;
 615 #ifdef CONFIG_BOOKE
 616         /*
 617          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 618          */
 619         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 620                         DBCR1_IAC3US | DBCR1_IAC4US;
 621         /*
 622          * Force Data Address Compare User/Supervisor bits to be User-only
 623          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 624          */
 625         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 626 #else
 627         thread->debug.dbcr1 = 0;
 628 #endif
 629 }
 630
 631 static void prime_debug_regs(struct debug_reg *debug)
 632 {
 633         /*
 634          * We could have inherited MSR_DE from userspace, since
 635          * it doesn't get cleared on exception entry.  Make sure
 636          * MSR_DE is clear before we enable any debug events.
 637          */
 638         mtmsr(mfmsr() & ~MSR_DE);
 639
 640         mtspr(SPRN_IAC1, debug->iac1);
 641         mtspr(SPRN_IAC2, debug->iac2);
 642 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 643         mtspr(SPRN_IAC3, debug->iac3);
 644         mtspr(SPRN_IAC4, debug->iac4);
 645 #endif
 646         mtspr(SPRN_DAC1, debug->dac1);
 647         mtspr(SPRN_DAC2, debug->dac2);
 648 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 649         mtspr(SPRN_DVC1, debug->dvc1);
 650         mtspr(SPRN_DVC2, debug->dvc2);
 651 #endif
 652         mtspr(SPRN_DBCR0, debug->dbcr0);
 653         mtspr(SPRN_DBCR1, debug->dbcr1);
 654 #ifdef CONFIG_BOOKE
 655         mtspr(SPRN_DBCR2, debug->dbcr2);
 656 #endif
 657 }
 658 /*
 659  * Unless neither the old or new thread are making use of the
 660  * debug registers, set the debug registers from the values
 661  * stored in the new thread.
 662  */
 663 void switch_booke_debug_regs(struct debug_reg *new_debug)
 664 {
 665         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 666                 || (new_debug->dbcr0 & DBCR0_IDM))
 667                         prime_debug_regs(new_debug);
 668 }
 669 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 670 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 671 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 672 static void set_debug_reg_defaults(struct thread_struct *thread)
 673 {
 674         thread->hw_brk.address = 0;
 675         thread->hw_brk.type = 0;
 676         set_breakpoint(&thread->hw_brk);
 677 }
 678 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 679 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 680
 681 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 682 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 683 {
 684         mtspr(SPRN_DAC1, dabr);
 685 #ifdef CONFIG_PPC_47x
 686         isync();
 687 #endif
 688         return 0;
 689 }
 690 #elif defined(CONFIG_PPC_BOOK3S)
 691 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 692 {
 693         mtspr(SPRN_DABR, dabr);
 694         if (cpu_has_feature(CPU_FTR_DABRX))
 695                 mtspr(SPRN_DABRX, dabrx);
 696         return 0;
 697 }
 698 #else
 699 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 700 {
 701         return -EINVAL;
 702 }
 703 #endif
 704
 705 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 706 {
 707         unsigned long dabr, dabrx;
 708
 709         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 710         dabrx = ((brk->type >> 3) & 0x7);
 711
 712         if (ppc_md.set_dabr)
 713                 return ppc_md.set_dabr(dabr, dabrx);
 714
 715         return __set_dabr(dabr, dabrx);
 716 }
 717
 718 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 719 {
 720         unsigned long dawr, dawrx, mrd;
 721
 722         dawr = brk->address;
 723
 724         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 725                                    << (63 - 58); //* read/write bits */
 726         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 727                                    << (63 - 59); //* translate */
 728         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 729                                    >> 3; //* PRIM bits */
 730         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 731            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 732            0b111111=64DW.
 733            brk->len is in bytes.
 734            This aligns up to double word size, shifts and does the bias.
 735         */
 736         mrd = ((brk->len + 7) >> 3) - 1;
 737         dawrx |= (mrd & 0x3f) << (63 - 53);
 738
 739         if (ppc_md.set_dawr)
 740                 return ppc_md.set_dawr(dawr, dawrx);
 741         mtspr(SPRN_DAWR, dawr);
 742         mtspr(SPRN_DAWRX, dawrx);
 743         return 0;
 744 }
 745
 746 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 747 {
 748         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 749
 750         if (cpu_has_feature(CPU_FTR_DAWR))
 751                 set_dawr(brk);
 752         else
 753                 set_dabr(brk);
 754 }
 755
 756 void set_breakpoint(struct arch_hw_breakpoint *brk)
 757 {
 758         preempt_disable();
 759         __set_breakpoint(brk);
 760         preempt_enable();
 761 }
 762
 763 #ifdef CONFIG_PPC64
 764 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 765 #endif
 766
 767 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 768                               struct arch_hw_breakpoint *b)
 769 {
 770         if (a->address != b->address)
 771                 return false;
 772         if (a->type != b->type)
 773                 return false;
 774         if (a->len != b->len)
 775                 return false;
 776         return true;
 777 }
 778
 779 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 780 static void tm_reclaim_thread(struct thread_struct *thr,
 781                               struct thread_info *ti, uint8_t cause)
 782 {
 783         unsigned long msr_diff = 0;
 784
 785         /*
 786          * If FP/VSX registers have been already saved to the
 787          * thread_struct, move them to the transact_fp array.
 788          * We clear the TIF_RESTORE_TM bit since after the reclaim
 789          * the thread will no longer be transactional.
 790          */
 791         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 792                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 793                 if (msr_diff & MSR_FP)
 794                         memcpy(&thr->transact_fp, &thr->fp_state,
 795                                sizeof(struct thread_fp_state));
 796                 if (msr_diff & MSR_VEC)
 797                         memcpy(&thr->transact_vr, &thr->vr_state,
 798                                sizeof(struct thread_vr_state));
 799                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 800                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 801         }
 802
 803         /*
 804          * Use the current MSR TM suspended bit to track if we have
 805          * checkpointed state outstanding.
 806          * On signal delivery, we'd normally reclaim the checkpointed
 807          * state to obtain stack pointer (see:get_tm_stackpointer()).
 808          * This will then directly return to userspace without going
 809          * through __switch_to(). However, if the stack frame is bad,
 810          * we need to exit this thread which calls __switch_to() which
 811          * will again attempt to reclaim the already saved tm state.
 812          * Hence we need to check that we've not already reclaimed
 813          * this state.
 814          * We do this using the current MSR, rather tracking it in
 815          * some specific thread_struct bit, as it has the additional
 816          * benefit of checking for a potential TM bad thing exception.
 817          */
 818         if (!MSR_TM_SUSPENDED(mfmsr()))
 819                 return;
 820
 821         tm_reclaim(thr, thr->regs->msr, cause);
 822
 823         /* Having done the reclaim, we now have the checkpointed
 824          * FP/VSX values in the registers.  These might be valid
 825          * even if we have previously called enable_kernel_fp() or
 826          * flush_fp_to_thread(), so update thr->regs->msr to
 827          * indicate their current validity.
 828          */
 829         thr->regs->msr |= msr_diff;
 830 }
 831
 832 void tm_reclaim_current(uint8_t cause)
 833 {
 834         tm_enable();
 835         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 836 }
 837
 838 static inline void tm_reclaim_task(struct task_struct *tsk)
 839 {
 840         /* We have to work out if we're switching from/to a task that's in the
 841          * middle of a transaction.
 842          *
 843          * In switching we need to maintain a 2nd register state as
 844          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 845          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 846          * (current) FPRs into oldtask->thread.transact_fpr[].
 847          *
 848          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 849          */
 850         struct thread_struct *thr = &tsk->thread;
 851
 852         if (!thr->regs)
 853                 return;
 854
 855         if (!MSR_TM_ACTIVE(thr->regs->msr))
 856                 goto out_and_saveregs;
 857
 858         /* Stash the original thread MSR, as giveup_fpu et al will
 859          * modify it.  We hold onto it to see whether the task used
 860          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 861          * ckpt_regs.msr is already set.
 862          */
 863         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 864                 thr->ckpt_regs.msr = thr->regs->msr;
 865
 866         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 867                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 868                  tsk->pid, thr->regs->nip,
 869                  thr->regs->ccr, thr->regs->msr,
 870                  thr->regs->trap);
 871
 872         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 873
 874         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 875                  tsk->pid);
 876
 877 out_and_saveregs:
 878         /* Always save the regs here, even if a transaction's not active.
 879          * This context-switches a thread's TM info SPRs.  We do it here to
 880          * be consistent with the restore path (in recheckpoint) which
 881          * cannot happen later in _switch().
 882          */
 883         tm_save_sprs(thr);
 884 }
 885
 886 extern void __tm_recheckpoint(struct thread_struct *thread,
 887                               unsigned long orig_msr);
 888
 889 void tm_recheckpoint(struct thread_struct *thread,
 890                      unsigned long orig_msr)
 891 {
 892         unsigned long flags;
 893
 894         /* We really can't be interrupted here as the TEXASR registers can't
 895          * change and later in the trecheckpoint code, we have a userspace R1.
 896          * So let's hard disable over this region.
 897          */
 898         local_irq_save(flags);
 899         hard_irq_disable();
 900
 901         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 902          * before the trecheckpoint and no explosion occurs.
 903          */
 904         tm_restore_sprs(thread);
 905
 906         __tm_recheckpoint(thread, orig_msr);
 907
 908         local_irq_restore(flags);
 909 }
 910
 911 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 912 {
 913         unsigned long msr;
 914
 915         if (!cpu_has_feature(CPU_FTR_TM))
 916                 return;
 917
 918         /* Recheckpoint the registers of the thread we're about to switch to.
 919          *
 920          * If the task was using FP, we non-lazily reload both the original and
 921          * the speculative FP register states.  This is because the kernel
 922          * doesn't see if/when a TM rollback occurs, so if we take an FP
 923          * unavoidable later, we are unable to determine which set of FP regs
 924          * need to be restored.
 925          */
 926         if (!new->thread.regs)
 927                 return;
 928
 929         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 930                 tm_restore_sprs(&new->thread);
 931                 return;
 932         }
 933         msr = new->thread.ckpt_regs.msr;
 934         /* Recheckpoint to restore original checkpointed register state. */
 935         TM_DEBUG("*** tm_recheckpoint of pid %d "
 936                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 937                  new->pid, new->thread.regs->msr, msr);
 938
 939         /* This loads the checkpointed FP/VEC state, if used */
 940         tm_recheckpoint(&new->thread, msr);
 941
 942         /* This loads the speculative FP/VEC state, if used */
 943         if (msr & MSR_FP) {
 944                 do_load_up_transact_fpu(&new->thread);
 945                 new->thread.regs->msr |=
 946                         (MSR_FP | new->thread.fpexc_mode);
 947         }
 948 #ifdef CONFIG_ALTIVEC
 949         if (msr & MSR_VEC) {
 950                 do_load_up_transact_altivec(&new->thread);
 951                 new->thread.regs->msr |= MSR_VEC;
 952         }
 953 #endif
 954         /* We may as well turn on VSX too since all the state is restored now */
 955         if (msr & MSR_VSX)
 956                 new->thread.regs->msr |= MSR_VSX;
 957
 958         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 959                  "(kernel msr 0x%lx)\n",
 960                  new->pid, mfmsr());
 961 }
 962
 963 static inline void __switch_to_tm(struct task_struct *prev)
 964 {
 965         if (cpu_has_feature(CPU_FTR_TM)) {
 966                 tm_enable();
 967                 tm_reclaim_task(prev);
 968         }
 969 }
 970
 971 /*
 972  * This is called if we are on the way out to userspace and the
 973  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 974  * FP and/or vector state and does so if necessary.
 975  * If userspace is inside a transaction (whether active or
 976  * suspended) and FP/VMX/VSX instructions have ever been enabled
 977  * inside that transaction, then we have to keep them enabled
 978  * and keep the FP/VMX/VSX state loaded while ever the transaction
 979  * continues.  The reason is that if we didn't, and subsequently
 980  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 981  * we don't know whether it's the same transaction, and thus we
 982  * don't know which of the checkpointed state and the transactional
 983  * state to use.
 984  */
 985 void restore_tm_state(struct pt_regs *regs)
 986 {
 987         unsigned long msr_diff;
 988
 989         clear_thread_flag(TIF_RESTORE_TM);
 990         if (!MSR_TM_ACTIVE(regs->msr))
 991                 return;
 992
 993         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 994         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 995
 996         /* Ensure that restore_math() will restore */
 997         if (msr_diff & MSR_FP)
 998                 current->thread.load_fp = 1;
 999 #ifdef CONFIG_ALIVEC
1000         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1001                 current->thread.load_vec = 1;
1002 #endif
1003         restore_math(regs);
1004
1005         regs->msr |= msr_diff;
1006 }
1007
1008 #else
1009 #define tm_recheckpoint_new_task(new)
1010 #define __switch_to_tm(prev)
1011 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1012
1013 static inline void save_sprs(struct thread_struct *t)
1014 {
1015 #ifdef CONFIG_ALTIVEC
1016         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1017                 t->vrsave = mfspr(SPRN_VRSAVE);
1018 #endif
1019 #ifdef CONFIG_PPC_BOOK3S_64
1020         if (cpu_has_feature(CPU_FTR_DSCR))
1021                 t->dscr = mfspr(SPRN_DSCR);
1022
1023         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1024                 t->bescr = mfspr(SPRN_BESCR);
1025                 t->ebbhr = mfspr(SPRN_EBBHR);
1026                 t->ebbrr = mfspr(SPRN_EBBRR);
1027
1028                 t->fscr = mfspr(SPRN_FSCR);
1029
1030                 /*
1031                  * Note that the TAR is not available for use in the kernel.
1032                  * (To provide this, the TAR should be backed up/restored on
1033                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1034                  * this should be in pt_regs anyway (for debug).)
1035                  */
1036                 t->tar = mfspr(SPRN_TAR);
1037         }
1038
1039         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1040                 /* Conditionally save Load Monitor registers, if enabled */
1041                 if (t->fscr & FSCR_LM) {
1042                         t->lmrr = mfspr(SPRN_LMRR);
1043                         t->lmser = mfspr(SPRN_LMSER);
1044                 }
1045         }
1046 #endif
1047 }
1048
1049 static inline void restore_sprs(struct thread_struct *old_thread,
1050                                 struct thread_struct *new_thread)
1051 {
1052 #ifdef CONFIG_ALTIVEC
1053         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1054             old_thread->vrsave != new_thread->vrsave)
1055                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1056 #endif
1057 #ifdef CONFIG_PPC_BOOK3S_64
1058         if (cpu_has_feature(CPU_FTR_DSCR)) {
1059                 u64 dscr = get_paca()->dscr_default;
1060                 if (new_thread->dscr_inherit)
1061                         dscr = new_thread->dscr;
1062
1063                 if (old_thread->dscr != dscr)
1064                         mtspr(SPRN_DSCR, dscr);
1065         }
1066
1067         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1068                 if (old_thread->bescr != new_thread->bescr)
1069                         mtspr(SPRN_BESCR, new_thread->bescr);
1070                 if (old_thread->ebbhr != new_thread->ebbhr)
1071                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1072                 if (old_thread->ebbrr != new_thread->ebbrr)
1073                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1074
1075                 if (old_thread->fscr != new_thread->fscr)
1076                         mtspr(SPRN_FSCR, new_thread->fscr);
1077
1078                 if (old_thread->tar != new_thread->tar)
1079                         mtspr(SPRN_TAR, new_thread->tar);
1080         }
1081
1082         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1083                 /* Conditionally restore Load Monitor registers, if enabled */
1084                 if (new_thread->fscr & FSCR_LM) {
1085                         if (old_thread->lmrr != new_thread->lmrr)
1086                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1087                         if (old_thread->lmser != new_thread->lmser)
1088                                 mtspr(SPRN_LMSER, new_thread->lmser);
1089                 }
1090         }
1091 #endif
1092 }
1093
1094 struct task_struct *__switch_to(struct task_struct *prev,
1095         struct task_struct *new)
1096 {
1097         struct thread_struct *new_thread, *old_thread;
1098         struct task_struct *last;
1099 #ifdef CONFIG_PPC_BOOK3S_64
1100         struct ppc64_tlb_batch *batch;
1101 #endif
1102
1103         new_thread = &new->thread;
1104         old_thread = &current->thread;
1105
1106         WARN_ON(!irqs_disabled());
1107
1108 #ifdef CONFIG_PPC64
1109         /*
1110          * Collect processor utilization data per process
1111          */
1112         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1113                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1114                 long unsigned start_tb, current_tb;
1115                 start_tb = old_thread->start_tb;
1116                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1117                 old_thread->accum_tb += (current_tb - start_tb);
1118                 new_thread->start_tb = current_tb;
1119         }
1120 #endif /* CONFIG_PPC64 */
1121
1122 #ifdef CONFIG_PPC_STD_MMU_64
1123         batch = this_cpu_ptr(&ppc64_tlb_batch);
1124         if (batch->active) {
1125                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1126                 if (batch->index)
1127                         __flush_tlb_pending(batch);
1128                 batch->active = 0;
1129         }
1130 #endif /* CONFIG_PPC_STD_MMU_64 */
1131
1132 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1133         switch_booke_debug_regs(&new->thread.debug);
1134 #else
1135 /*
1136  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1137  * schedule DABR
1138  */
1139 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1140         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1141                 __set_breakpoint(&new->thread.hw_brk);
1142 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1143 #endif
1144
1145         /*
1146          * We need to save SPRs before treclaim/trecheckpoint as these will
1147          * change a number of them.
1148          */
1149         save_sprs(&prev->thread);
1150
1151         __switch_to_tm(prev);
1152
1153         /* Save FPU, Altivec, VSX and SPE state */
1154         giveup_all(prev);
1155
1156         /*
1157          * We can't take a PMU exception inside _switch() since there is a
1158          * window where the kernel stack SLB and the kernel stack are out
1159          * of sync. Hard disable here.
1160          */
1161         hard_irq_disable();
1162
1163         tm_recheckpoint_new_task(new);
1164
1165         /*
1166          * Call restore_sprs() before calling _switch(). If we move it after
1167          * _switch() then we miss out on calling it for new tasks. The reason
1168          * for this is we manually create a stack frame for new tasks that
1169          * directly returns through ret_from_fork() or
1170          * ret_from_kernel_thread(). See copy_thread() for details.
1171          */
1172         restore_sprs(old_thread, new_thread);
1173
1174         last = _switch(old_thread, new_thread);
1175
1176 #ifdef CONFIG_PPC_STD_MMU_64
1177         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1178                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1179                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1180                 batch->active = 1;
1181         }
1182
1183         if (current_thread_info()->task->thread.regs)
1184                 restore_math(current_thread_info()->task->thread.regs);
1185 #endif /* CONFIG_PPC_STD_MMU_64 */
1186
1187         return last;
1188 }
1189
1190 static int instructions_to_print = 16;
1191
1192 static void show_instructions(struct pt_regs *regs)
1193 {
1194         int i;
1195         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1196                         sizeof(int));
1197
1198         printk("Instruction dump:");
1199
1200         for (i = 0; i < instructions_to_print; i++) {
1201                 int instr;
1202
1203                 if (!(i % 8))
1204                         printk("\n");
1205
1206 #if !defined(CONFIG_BOOKE)
1207                 /* If executing with the IMMU off, adjust pc rather
1208                  * than print XXXXXXXX.
1209                  */
1210                 if (!(regs->msr & MSR_IR))
1211                         pc = (unsigned long)phys_to_virt(pc);
1212 #endif
1213
1214                 if (!__kernel_text_address(pc) ||
1215                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1216                         printk(KERN_CONT "XXXXXXXX ");
1217                 } else {
1218                         if (regs->nip == pc)
1219                                 printk(KERN_CONT "<%08x> ", instr);
1220                         else
1221                                 printk(KERN_CONT "%08x ", instr);
1222                 }
1223
1224                 pc += sizeof(int);
1225         }
1226
1227         printk("\n");
1228 }
1229
1230 struct regbit {
1231         unsigned long bit;
1232         const char *name;
1233 };
1234
1235 static struct regbit msr_bits[] = {
1236 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1237         {MSR_SF,        "SF"},
1238         {MSR_HV,        "HV"},
1239 #endif
1240         {MSR_VEC,       "VEC"},
1241         {MSR_VSX,       "VSX"},
1242 #ifdef CONFIG_BOOKE
1243         {MSR_CE,        "CE"},
1244 #endif
1245         {MSR_EE,        "EE"},
1246         {MSR_PR,        "PR"},
1247         {MSR_FP,        "FP"},
1248         {MSR_ME,        "ME"},
1249 #ifdef CONFIG_BOOKE
1250         {MSR_DE,        "DE"},
1251 #else
1252         {MSR_SE,        "SE"},
1253         {MSR_BE,        "BE"},
1254 #endif
1255         {MSR_IR,        "IR"},
1256         {MSR_DR,        "DR"},
1257         {MSR_PMM,       "PMM"},
1258 #ifndef CONFIG_BOOKE
1259         {MSR_RI,        "RI"},
1260         {MSR_LE,        "LE"},
1261 #endif
1262         {0,             NULL}
1263 };
1264
1265 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1266 {
1267         const char *s = "";
1268
1269         for (; bits->bit; ++bits)
1270                 if (val & bits->bit) {
1271                         printk("%s%s", s, bits->name);
1272                         s = sep;
1273                 }
1274 }
1275
1276 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1277 static struct regbit msr_tm_bits[] = {
1278         {MSR_TS_T,      "T"},
1279         {MSR_TS_S,      "S"},
1280         {MSR_TM,        "E"},
1281         {0,             NULL}
1282 };
1283
1284 static void print_tm_bits(unsigned long val)
1285 {
1286 /*
1287  * This only prints something if at least one of the TM bit is set.
1288  * Inside the TM[], the output means:
1289  *   E: Enabled         (bit 32)
1290  *   S: Suspended       (bit 33)
1291  *   T: Transactional   (bit 34)
1292  */
1293         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1294                 printk(",TM[");
1295                 print_bits(val, msr_tm_bits, "");
1296                 printk("]");
1297         }
1298 }
1299 #else
1300 static void print_tm_bits(unsigned long val) {}
1301 #endif
1302
1303 static void print_msr_bits(unsigned long val)
1304 {
1305         printk("<");
1306         print_bits(val, msr_bits, ",");
1307         print_tm_bits(val);
1308         printk(">");
1309 }
1310
1311 #ifdef CONFIG_PPC64
1312 #define REG             "%016lx"
1313 #define REGS_PER_LINE   4
1314 #define LAST_VOLATILE   13
1315 #else
1316 #define REG             "%08lx"
1317 #define REGS_PER_LINE   8
1318 #define LAST_VOLATILE   12
1319 #endif
1320
1321 void show_regs(struct pt_regs * regs)
1322 {
1323         int i, trap;
1324
1325         show_regs_print_info(KERN_DEFAULT);
1326
1327         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1328                regs->nip, regs->link, regs->ctr);
1329         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1330                regs, regs->trap, print_tainted(), init_utsname()->release);
1331         printk("MSR: "REG" ", regs->msr);
1332         print_msr_bits(regs->msr);
1333         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1334         trap = TRAP(regs);
1335         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1336                 printk("CFAR: "REG" ", regs->orig_gpr3);
1337         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1338 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1339                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1340 #else
1341                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1342 #endif
1343 #ifdef CONFIG_PPC64
1344         printk("SOFTE: %ld ", regs->softe);
1345 #endif
1346 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1347         if (MSR_TM_ACTIVE(regs->msr))
1348                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1349 #endif
1350
1351         for (i = 0;  i < 32;  i++) {
1352                 if ((i % REGS_PER_LINE) == 0)
1353                         printk("\nGPR%02d: ", i);
1354                 printk(REG " ", regs->gpr[i]);
1355                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1356                         break;
1357         }
1358         printk("\n");
1359 #ifdef CONFIG_KALLSYMS
1360         /*
1361          * Lookup NIP late so we have the best change of getting the
1362          * above info out without failing
1363          */
1364         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1365         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1366 #endif
1367         show_stack(current, (unsigned long *) regs->gpr[1]);
1368         if (!user_mode(regs))
1369                 show_instructions(regs);
1370 }
1371
1372 void flush_thread(void)
1373 {
1374 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1375         flush_ptrace_hw_breakpoint(current);
1376 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1377         set_debug_reg_defaults(&current->thread);
1378 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1379 }
1380
1381 void
1382 release_thread(struct task_struct *t)
1383 {
1384 }
1385
1386 /*
1387  * this gets called so that we can store coprocessor state into memory and
1388  * copy the current task into the new thread.
1389  */
1390 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1391 {
1392         flush_all_to_thread(src);
1393         /*
1394          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1395          * flush but it removes the checkpointed state from the current CPU and
1396          * transitions the CPU out of TM mode.  Hence we need to call
1397          * tm_recheckpoint_new_task() (on the same task) to restore the
1398          * checkpointed state back and the TM mode.
1399          */
1400         __switch_to_tm(src);
1401         tm_recheckpoint_new_task(src);
1402
1403         *dst = *src;
1404
1405         clear_task_ebb(dst);
1406
1407         return 0;
1408 }
1409
1410 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1411 {
1412 #ifdef CONFIG_PPC_STD_MMU_64
1413         unsigned long sp_vsid;
1414         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1415
1416         if (radix_enabled())
1417                 return;
1418
1419         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1420                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1421                         << SLB_VSID_SHIFT_1T;
1422         else
1423                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1424                         << SLB_VSID_SHIFT;
1425         sp_vsid |= SLB_VSID_KERNEL | llp;
1426         p->thread.ksp_vsid = sp_vsid;
1427 #endif
1428 }
1429
1430 /*
1431  * Copy a thread..
1432  */
1433
1434 /*
1435  * Copy architecture-specific thread state
1436  */
1437 int copy_thread(unsigned long clone_flags, unsigned long usp,
1438                 unsigned long kthread_arg, struct task_struct *p)
1439 {
1440         struct pt_regs *childregs, *kregs;
1441         extern void ret_from_fork(void);
1442         extern void ret_from_kernel_thread(void);
1443         void (*f)(void);
1444         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1445         struct thread_info *ti = task_thread_info(p);
1446
1447         klp_init_thread_info(ti);
1448
1449         /* Copy registers */
1450         sp -= sizeof(struct pt_regs);
1451         childregs = (struct pt_regs *) sp;
1452         if (unlikely(p->flags & PF_KTHREAD)) {
1453                 /* kernel thread */
1454                 memset(childregs, 0, sizeof(struct pt_regs));
1455                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1456                 /* function */
1457                 if (usp)
1458                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1459 #ifdef CONFIG_PPC64
1460                 clear_tsk_thread_flag(p, TIF_32BIT);
1461                 childregs->softe = 1;
1462 #endif
1463                 childregs->gpr[15] = kthread_arg;
1464                 p->thread.regs = NULL;  /* no user register state */
1465                 ti->flags |= _TIF_RESTOREALL;
1466                 f = ret_from_kernel_thread;
1467         } else {
1468                 /* user thread */
1469                 struct pt_regs *regs = current_pt_regs();
1470                 CHECK_FULL_REGS(regs);
1471                 *childregs = *regs;
1472                 if (usp)
1473                         childregs->gpr[1] = usp;
1474                 p->thread.regs = childregs;
1475                 childregs->gpr[3] = 0;  /* Result from fork() */
1476                 if (clone_flags & CLONE_SETTLS) {
1477 #ifdef CONFIG_PPC64
1478                         if (!is_32bit_task())
1479                                 childregs->gpr[13] = childregs->gpr[6];
1480                         else
1481 #endif
1482                                 childregs->gpr[2] = childregs->gpr[6];
1483                 }
1484
1485                 f = ret_from_fork;
1486         }
1487         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1488         sp -= STACK_FRAME_OVERHEAD;
1489
1490         /*
1491          * The way this works is that at some point in the future
1492          * some task will call _switch to switch to the new task.
1493          * That will pop off the stack frame created below and start
1494          * the new task running at ret_from_fork.  The new task will
1495          * do some house keeping and then return from the fork or clone
1496          * system call, using the stack frame created above.
1497          */
1498         ((unsigned long *)sp)[0] = 0;
1499         sp -= sizeof(struct pt_regs);
1500         kregs = (struct pt_regs *) sp;
1501         sp -= STACK_FRAME_OVERHEAD;
1502         p->thread.ksp = sp;
1503 #ifdef CONFIG_PPC32
1504         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1505                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1506 #endif
1507 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1508         p->thread.ptrace_bps[0] = NULL;
1509 #endif
1510
1511         p->thread.fp_save_area = NULL;
1512 #ifdef CONFIG_ALTIVEC
1513         p->thread.vr_save_area = NULL;
1514 #endif
1515
1516         setup_ksp_vsid(p, sp);
1517
1518 #ifdef CONFIG_PPC64
1519         if (cpu_has_feature(CPU_FTR_DSCR)) {
1520                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1521                 p->thread.dscr = mfspr(SPRN_DSCR);
1522         }
1523         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1524                 p->thread.ppr = INIT_PPR;
1525 #endif
1526         kregs->nip = ppc_function_entry(f);
1527         return 0;
1528 }
1529
1530 /*
1531  * Set up a thread for executing a new program
1532  */
1533 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1534 {
1535 #ifdef CONFIG_PPC64
1536         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1537 #endif
1538
1539         /*
1540          * If we exec out of a kernel thread then thread.regs will not be
1541          * set.  Do it now.
1542          */
1543         if (!current->thread.regs) {
1544                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1545                 current->thread.regs = regs - 1;
1546         }
1547
1548 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1549         /*
1550          * Clear any transactional state, we're exec()ing. The cause is
1551          * not important as there will never be a recheckpoint so it's not
1552          * user visible.
1553          */
1554         if (MSR_TM_SUSPENDED(mfmsr()))
1555                 tm_reclaim_current(0);
1556 #endif
1557
1558         memset(regs->gpr, 0, sizeof(regs->gpr));
1559         regs->ctr = 0;
1560         regs->link = 0;
1561         regs->xer = 0;
1562         regs->ccr = 0;
1563         regs->gpr[1] = sp;
1564
1565         /*
1566          * We have just cleared all the nonvolatile GPRs, so make
1567          * FULL_REGS(regs) return true.  This is necessary to allow
1568          * ptrace to examine the thread immediately after exec.
1569          */
1570         regs->trap &= ~1UL;
1571
1572 #ifdef CONFIG_PPC32
1573         regs->mq = 0;
1574         regs->nip = start;
1575         regs->msr = MSR_USER;
1576 #else
1577         if (!is_32bit_task()) {
1578                 unsigned long entry;
1579
1580                 if (is_elf2_task()) {
1581                         /* Look ma, no function descriptors! */
1582                         entry = start;
1583
1584                         /*
1585                          * Ulrich says:
1586                          *   The latest iteration of the ABI requires that when
1587                          *   calling a function (at its global entry point),
1588                          *   the caller must ensure r12 holds the entry point
1589                          *   address (so that the function can quickly
1590                          *   establish addressability).
1591                          */
1592                         regs->gpr[12] = start;
1593                         /* Make sure that's restored on entry to userspace. */
1594                         set_thread_flag(TIF_RESTOREALL);
1595                 } else {
1596                         unsigned long toc;
1597
1598                         /* start is a relocated pointer to the function
1599                          * descriptor for the elf _start routine.  The first
1600                          * entry in the function descriptor is the entry
1601                          * address of _start and the second entry is the TOC
1602                          * value we need to use.
1603                          */
1604                         __get_user(entry, (unsigned long __user *)start);
1605                         __get_user(toc, (unsigned long __user *)start+1);
1606
1607                         /* Check whether the e_entry function descriptor entries
1608                          * need to be relocated before we can use them.
1609                          */
1610                         if (load_addr != 0) {
1611                                 entry += load_addr;
1612                                 toc   += load_addr;
1613                         }
1614                         regs->gpr[2] = toc;
1615                 }
1616                 regs->nip = entry;
1617                 regs->msr = MSR_USER64;
1618         } else {
1619                 regs->nip = start;
1620                 regs->gpr[2] = 0;
1621                 regs->msr = MSR_USER32;
1622         }
1623 #endif
1624 #ifdef CONFIG_VSX
1625         current->thread.used_vsr = 0;
1626 #endif
1627         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1628         current->thread.fp_save_area = NULL;
1629 #ifdef CONFIG_ALTIVEC
1630         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1631         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1632         current->thread.vr_save_area = NULL;
1633         current->thread.vrsave = 0;
1634         current->thread.used_vr = 0;
1635 #endif /* CONFIG_ALTIVEC */
1636 #ifdef CONFIG_SPE
1637         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1638         current->thread.acc = 0;
1639         current->thread.spefscr = 0;
1640         current->thread.used_spe = 0;
1641 #endif /* CONFIG_SPE */
1642 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1643         if (cpu_has_feature(CPU_FTR_TM))
1644                 regs->msr |= MSR_TM;
1645         current->thread.tm_tfhar = 0;
1646         current->thread.tm_texasr = 0;
1647         current->thread.tm_tfiar = 0;
1648 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1649 }
1650 EXPORT_SYMBOL(start_thread);
1651
1652 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1653                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1654
1655 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1656 {
1657         struct pt_regs *regs = tsk->thread.regs;
1658
1659         /* This is a bit hairy.  If we are an SPE enabled  processor
1660          * (have embedded fp) we store the IEEE exception enable flags in
1661          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1662          * mode (asyn, precise, disabled) for 'Classic' FP. */
1663         if (val & PR_FP_EXC_SW_ENABLE) {
1664 #ifdef CONFIG_SPE
1665                 if (cpu_has_feature(CPU_FTR_SPE)) {
1666                         /*
1667                          * When the sticky exception bits are set
1668                          * directly by userspace, it must call prctl
1669                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1670                          * in the existing prctl settings) or
1671                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1672                          * the bits being set).  <fenv.h> functions
1673                          * saving and restoring the whole
1674                          * floating-point environment need to do so
1675                          * anyway to restore the prctl settings from
1676                          * the saved environment.
1677                          */
1678                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1679                         tsk->thread.fpexc_mode = val &
1680                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1681                         return 0;
1682                 } else {
1683                         return -EINVAL;
1684                 }
1685 #else
1686                 return -EINVAL;
1687 #endif
1688         }
1689
1690         /* on a CONFIG_SPE this does not hurt us.  The bits that
1691          * __pack_fe01 use do not overlap with bits used for
1692          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1693          * on CONFIG_SPE implementations are reserved so writing to
1694          * them does not change anything */
1695         if (val > PR_FP_EXC_PRECISE)
1696                 return -EINVAL;
1697         tsk->thread.fpexc_mode = __pack_fe01(val);
1698         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1699                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1700                         | tsk->thread.fpexc_mode;
1701         return 0;
1702 }
1703
1704 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1705 {
1706         unsigned int val;
1707
1708         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1709 #ifdef CONFIG_SPE
1710                 if (cpu_has_feature(CPU_FTR_SPE)) {
1711                         /*
1712                          * When the sticky exception bits are set
1713                          * directly by userspace, it must call prctl
1714                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1715                          * in the existing prctl settings) or
1716                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1717                          * the bits being set).  <fenv.h> functions
1718                          * saving and restoring the whole
1719                          * floating-point environment need to do so
1720                          * anyway to restore the prctl settings from
1721                          * the saved environment.
1722                          */
1723                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1724                         val = tsk->thread.fpexc_mode;
1725                 } else
1726                         return -EINVAL;
1727 #else
1728                 return -EINVAL;
1729 #endif
1730         else
1731                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1732         return put_user(val, (unsigned int __user *) adr);
1733 }
1734
1735 int set_endian(struct task_struct *tsk, unsigned int val)
1736 {
1737         struct pt_regs *regs = tsk->thread.regs;
1738
1739         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1740             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1741                 return -EINVAL;
1742
1743         if (regs == NULL)
1744                 return -EINVAL;
1745
1746         if (val == PR_ENDIAN_BIG)
1747                 regs->msr &= ~MSR_LE;
1748         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1749                 regs->msr |= MSR_LE;
1750         else
1751                 return -EINVAL;
1752
1753         return 0;
1754 }
1755
1756 int get_endian(struct task_struct *tsk, unsigned long adr)
1757 {
1758         struct pt_regs *regs = tsk->thread.regs;
1759         unsigned int val;
1760
1761         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1762             !cpu_has_feature(CPU_FTR_REAL_LE))
1763                 return -EINVAL;
1764
1765         if (regs == NULL)
1766                 return -EINVAL;
1767
1768         if (regs->msr & MSR_LE) {
1769                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1770                         val = PR_ENDIAN_LITTLE;
1771                 else
1772                         val = PR_ENDIAN_PPC_LITTLE;
1773         } else
1774                 val = PR_ENDIAN_BIG;
1775
1776         return put_user(val, (unsigned int __user *)adr);
1777 }
1778
1779 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1780 {
1781         tsk->thread.align_ctl = val;
1782         return 0;
1783 }
1784
1785 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1786 {
1787         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1788 }
1789
1790 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1791                                   unsigned long nbytes)
1792 {
1793         unsigned long stack_page;
1794         unsigned long cpu = task_cpu(p);
1795
1796         /*
1797          * Avoid crashing if the stack has overflowed and corrupted
1798          * task_cpu(p), which is in the thread_info struct.
1799          */
1800         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1801                 stack_page = (unsigned long) hardirq_ctx[cpu];
1802                 if (sp >= stack_page + sizeof(struct thread_struct)
1803                     && sp <= stack_page + THREAD_SIZE - nbytes)
1804                         return 1;
1805
1806                 stack_page = (unsigned long) softirq_ctx[cpu];
1807                 if (sp >= stack_page + sizeof(struct thread_struct)
1808                     && sp <= stack_page + THREAD_SIZE - nbytes)
1809                         return 1;
1810         }
1811         return 0;
1812 }
1813
1814 int validate_sp(unsigned long sp, struct task_struct *p,
1815                        unsigned long nbytes)
1816 {
1817         unsigned long stack_page = (unsigned long)task_stack_page(p);
1818
1819         if (sp >= stack_page + sizeof(struct thread_struct)
1820             && sp <= stack_page + THREAD_SIZE - nbytes)
1821                 return 1;
1822
1823         return valid_irq_stack(sp, p, nbytes);
1824 }
1825
1826 EXPORT_SYMBOL(validate_sp);
1827
1828 unsigned long get_wchan(struct task_struct *p)
1829 {
1830         unsigned long ip, sp;
1831         int count = 0;
1832
1833         if (!p || p == current || p->state == TASK_RUNNING)
1834                 return 0;
1835
1836         sp = p->thread.ksp;
1837         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1838                 return 0;
1839
1840         do {
1841                 sp = *(unsigned long *)sp;
1842                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1843                         return 0;
1844                 if (count > 0) {
1845                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1846                         if (!in_sched_functions(ip))
1847                                 return ip;
1848                 }
1849         } while (count++ < 16);
1850         return 0;
1851 }
1852
1853 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1854
1855 void show_stack(struct task_struct *tsk, unsigned long *stack)
1856 {
1857         unsigned long sp, ip, lr, newsp;
1858         int count = 0;
1859         int firstframe = 1;
1860 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1861         int curr_frame = current->curr_ret_stack;
1862         extern void return_to_handler(void);
1863         unsigned long rth = (unsigned long)return_to_handler;
1864 #endif
1865
1866         sp = (unsigned long) stack;
1867         if (tsk == NULL)
1868                 tsk = current;
1869         if (sp == 0) {
1870                 if (tsk == current)
1871                         sp = current_stack_pointer();
1872                 else
1873                         sp = tsk->thread.ksp;
1874         }
1875
1876         lr = 0;
1877         printk("Call Trace:\n");
1878         do {
1879                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1880                         return;
1881
1882                 stack = (unsigned long *) sp;
1883                 newsp = stack[0];
1884                 ip = stack[STACK_FRAME_LR_SAVE];
1885                 if (!firstframe || ip != lr) {
1886                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1887 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1888                         if ((ip == rth) && curr_frame >= 0) {
1889                                 printk(" (%pS)",
1890                                        (void *)current->ret_stack[curr_frame].ret);
1891                                 curr_frame--;
1892                         }
1893 #endif
1894                         if (firstframe)
1895                                 printk(" (unreliable)");
1896                         printk("\n");
1897                 }
1898                 firstframe = 0;
1899
1900                 /*
1901                  * See if this is an exception frame.
1902                  * We look for the "regshere" marker in the current frame.
1903                  */
1904                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1905                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1906                         struct pt_regs *regs = (struct pt_regs *)
1907                                 (sp + STACK_FRAME_OVERHEAD);
1908                         lr = regs->link;
1909                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1910                                regs->trap, (void *)regs->nip, (void *)lr);
1911                         firstframe = 1;
1912                 }
1913
1914                 sp = newsp;
1915         } while (count++ < kstack_depth_to_print);
1916 }
1917
1918 #ifdef CONFIG_PPC64
1919 /* Called with hard IRQs off */
1920 void notrace __ppc64_runlatch_on(void)
1921 {
1922         struct thread_info *ti = current_thread_info();
1923         unsigned long ctrl;
1924
1925         ctrl = mfspr(SPRN_CTRLF);
1926         ctrl |= CTRL_RUNLATCH;
1927         mtspr(SPRN_CTRLT, ctrl);
1928
1929         ti->local_flags |= _TLF_RUNLATCH;
1930 }
1931
1932 /* Called with hard IRQs off */
1933 void notrace __ppc64_runlatch_off(void)
1934 {
1935         struct thread_info *ti = current_thread_info();
1936         unsigned long ctrl;
1937
1938         ti->local_flags &= ~_TLF_RUNLATCH;
1939
1940         ctrl = mfspr(SPRN_CTRLF);
1941         ctrl &= ~CTRL_RUNLATCH;
1942         mtspr(SPRN_CTRLT, ctrl);
1943 }
1944 #endif /* CONFIG_PPC64 */
1945
1946 unsigned long arch_align_stack(unsigned long sp)
1947 {
1948         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1949                 sp -= get_random_int() & ~PAGE_MASK;
1950         return sp & ~0xf;
1951 }
1952
1953 static inline unsigned long brk_rnd(void)
1954 {
1955         unsigned long rnd = 0;
1956
1957         /* 8MB for 32bit, 1GB for 64bit */
1958         if (is_32bit_task())
1959                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1960         else
1961                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1962
1963         return rnd << PAGE_SHIFT;
1964 }
1965
1966 unsigned long arch_randomize_brk(struct mm_struct *mm)
1967 {
1968         unsigned long base = mm->brk;
1969         unsigned long ret;
1970
1971 #ifdef CONFIG_PPC_STD_MMU_64
1972         /*
1973          * If we are using 1TB segments and we are allowed to randomise
1974          * the heap, we can put it above 1TB so it is backed by a 1TB
1975          * segment. Otherwise the heap will be in the bottom 1TB
1976          * which always uses 256MB segments and this may result in a
1977          * performance penalty. We don't need to worry about radix. For
1978          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1979          */
1980         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1981                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1982 #endif
1983
1984         ret = PAGE_ALIGN(base + brk_rnd());
1985
1986         if (ret < mm->brk)
1987                 return mm->brk;
1988
1989         return ret;
1990 }
1991