arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 unsigned long msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128
 129         return newmsr;
 130 }
 131
 132 void __msr_check_and_clear(unsigned long bits)
 133 {
 134         unsigned long oldmsr = mfmsr();
 135         unsigned long newmsr;
 136
 137         newmsr = oldmsr & ~bits;
 138
 139 #ifdef CONFIG_VSX
 140         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 141                 newmsr &= ~MSR_VSX;
 142 #endif
 143
 144         if (oldmsr != newmsr)
 145                 mtmsr_isync(newmsr);
 146 }
 147 EXPORT_SYMBOL(__msr_check_and_clear);
 148
 149 #ifdef CONFIG_PPC_FPU
 150 void __giveup_fpu(struct task_struct *tsk)
 151 {
 152         unsigned long msr;
 153
 154         save_fpu(tsk);
 155         msr = tsk->thread.regs->msr;
 156         msr &= ~MSR_FP;
 157 #ifdef CONFIG_VSX
 158         if (cpu_has_feature(CPU_FTR_VSX))
 159                 msr &= ~MSR_VSX;
 160 #endif
 161         tsk->thread.regs->msr = msr;
 162 }
 163
 164 void giveup_fpu(struct task_struct *tsk)
 165 {
 166         check_if_tm_restore_required(tsk);
 167
 168         msr_check_and_set(MSR_FP);
 169         __giveup_fpu(tsk);
 170         msr_check_and_clear(MSR_FP);
 171 }
 172 EXPORT_SYMBOL(giveup_fpu);
 173
 174 /*
 175  * Make sure the floating-point register state in the
 176  * the thread_struct is up to date for task tsk.
 177  */
 178 void flush_fp_to_thread(struct task_struct *tsk)
 179 {
 180         if (tsk->thread.regs) {
 181                 /*
 182                  * We need to disable preemption here because if we didn't,
 183                  * another process could get scheduled after the regs->msr
 184                  * test but before we have finished saving the FP registers
 185                  * to the thread_struct.  That process could take over the
 186                  * FPU, and then when we get scheduled again we would store
 187                  * bogus values for the remaining FP registers.
 188                  */
 189                 preempt_disable();
 190                 if (tsk->thread.regs->msr & MSR_FP) {
 191                         /*
 192                          * This should only ever be called for current or
 193                          * for a stopped child process.  Since we save away
 194                          * the FP register state on context switch,
 195                          * there is something wrong if a stopped child appears
 196                          * to still have its FP state in the CPU registers.
 197                          */
 198                         BUG_ON(tsk != current);
 199                         giveup_fpu(tsk);
 200                 }
 201                 preempt_enable();
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 205
 206 void enable_kernel_fp(void)
 207 {
 208         unsigned long cpumsr;
 209
 210         WARN_ON(preemptible());
 211
 212         cpumsr = msr_check_and_set(MSR_FP);
 213
 214         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 215                 check_if_tm_restore_required(current);
 216                 /*
 217                  * If a thread has already been reclaimed then the
 218                  * checkpointed registers are on the CPU but have definitely
 219                  * been saved by the reclaim code. Don't need to and *cannot*
 220                  * giveup as this would save  to the 'live' structure not the
 221                  * checkpointed structure.
 222                  */
 223                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 224                         return;
 225                 __giveup_fpu(current);
 226         }
 227 }
 228 EXPORT_SYMBOL(enable_kernel_fp);
 229
 230 static int restore_fp(struct task_struct *tsk) {
 231         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 232                 load_fp_state(&current->thread.fp_state);
 233                 current->thread.load_fp++;
 234                 return 1;
 235         }
 236         return 0;
 237 }
 238 #else
 239 static int restore_fp(struct task_struct *tsk) { return 0; }
 240 #endif /* CONFIG_PPC_FPU */
 241
 242 #ifdef CONFIG_ALTIVEC
 243 #define loadvec(thr) ((thr).load_vec)
 244
 245 static void __giveup_altivec(struct task_struct *tsk)
 246 {
 247         unsigned long msr;
 248
 249         save_altivec(tsk);
 250         msr = tsk->thread.regs->msr;
 251         msr &= ~MSR_VEC;
 252 #ifdef CONFIG_VSX
 253         if (cpu_has_feature(CPU_FTR_VSX))
 254                 msr &= ~MSR_VSX;
 255 #endif
 256         tsk->thread.regs->msr = msr;
 257 }
 258
 259 void giveup_altivec(struct task_struct *tsk)
 260 {
 261         check_if_tm_restore_required(tsk);
 262
 263         msr_check_and_set(MSR_VEC);
 264         __giveup_altivec(tsk);
 265         msr_check_and_clear(MSR_VEC);
 266 }
 267 EXPORT_SYMBOL(giveup_altivec);
 268
 269 void enable_kernel_altivec(void)
 270 {
 271         unsigned long cpumsr;
 272
 273         WARN_ON(preemptible());
 274
 275         cpumsr = msr_check_and_set(MSR_VEC);
 276
 277         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 278                 check_if_tm_restore_required(current);
 279                 /*
 280                  * If a thread has already been reclaimed then the
 281                  * checkpointed registers are on the CPU but have definitely
 282                  * been saved by the reclaim code. Don't need to and *cannot*
 283                  * giveup as this would save  to the 'live' structure not the
 284                  * checkpointed structure.
 285                  */
 286                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 287                         return;
 288                 __giveup_altivec(current);
 289         }
 290 }
 291 EXPORT_SYMBOL(enable_kernel_altivec);
 292
 293 /*
 294  * Make sure the VMX/Altivec register state in the
 295  * the thread_struct is up to date for task tsk.
 296  */
 297 void flush_altivec_to_thread(struct task_struct *tsk)
 298 {
 299         if (tsk->thread.regs) {
 300                 preempt_disable();
 301                 if (tsk->thread.regs->msr & MSR_VEC) {
 302                         BUG_ON(tsk != current);
 303                         giveup_altivec(tsk);
 304                 }
 305                 preempt_enable();
 306         }
 307 }
 308 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 309
 310 static int restore_altivec(struct task_struct *tsk)
 311 {
 312         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 313                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 314                 load_vr_state(&tsk->thread.vr_state);
 315                 tsk->thread.used_vr = 1;
 316                 tsk->thread.load_vec++;
 317
 318                 return 1;
 319         }
 320         return 0;
 321 }
 322 #else
 323 #define loadvec(thr) 0
 324 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 325 #endif /* CONFIG_ALTIVEC */
 326
 327 #ifdef CONFIG_VSX
 328 static void __giveup_vsx(struct task_struct *tsk)
 329 {
 330         if (tsk->thread.regs->msr & MSR_FP)
 331                 __giveup_fpu(tsk);
 332         if (tsk->thread.regs->msr & MSR_VEC)
 333                 __giveup_altivec(tsk);
 334         tsk->thread.regs->msr &= ~MSR_VSX;
 335 }
 336
 337 static void giveup_vsx(struct task_struct *tsk)
 338 {
 339         check_if_tm_restore_required(tsk);
 340
 341         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 342         __giveup_vsx(tsk);
 343         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 344 }
 345
 346 static void save_vsx(struct task_struct *tsk)
 347 {
 348         if (tsk->thread.regs->msr & MSR_FP)
 349                 save_fpu(tsk);
 350         if (tsk->thread.regs->msr & MSR_VEC)
 351                 save_altivec(tsk);
 352 }
 353
 354 void enable_kernel_vsx(void)
 355 {
 356         unsigned long cpumsr;
 357
 358         WARN_ON(preemptible());
 359
 360         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 361
 362         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 363                 check_if_tm_restore_required(current);
 364                 /*
 365                  * If a thread has already been reclaimed then the
 366                  * checkpointed registers are on the CPU but have definitely
 367                  * been saved by the reclaim code. Don't need to and *cannot*
 368                  * giveup as this would save  to the 'live' structure not the
 369                  * checkpointed structure.
 370                  */
 371                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 372                         return;
 373                 if (current->thread.regs->msr & MSR_FP)
 374                         __giveup_fpu(current);
 375                 if (current->thread.regs->msr & MSR_VEC)
 376                         __giveup_altivec(current);
 377                 __giveup_vsx(current);
 378         }
 379 }
 380 EXPORT_SYMBOL(enable_kernel_vsx);
 381
 382 void flush_vsx_to_thread(struct task_struct *tsk)
 383 {
 384         if (tsk->thread.regs) {
 385                 preempt_disable();
 386                 if (tsk->thread.regs->msr & MSR_VSX) {
 387                         BUG_ON(tsk != current);
 388                         giveup_vsx(tsk);
 389                 }
 390                 preempt_enable();
 391         }
 392 }
 393 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 394
 395 static int restore_vsx(struct task_struct *tsk)
 396 {
 397         if (cpu_has_feature(CPU_FTR_VSX)) {
 398                 tsk->thread.used_vsr = 1;
 399                 return 1;
 400         }
 401
 402         return 0;
 403 }
 404 #else
 405 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 406 static inline void save_vsx(struct task_struct *tsk) { }
 407 #endif /* CONFIG_VSX */
 408
 409 #ifdef CONFIG_SPE
 410 void giveup_spe(struct task_struct *tsk)
 411 {
 412         check_if_tm_restore_required(tsk);
 413
 414         msr_check_and_set(MSR_SPE);
 415         __giveup_spe(tsk);
 416         msr_check_and_clear(MSR_SPE);
 417 }
 418 EXPORT_SYMBOL(giveup_spe);
 419
 420 void enable_kernel_spe(void)
 421 {
 422         WARN_ON(preemptible());
 423
 424         msr_check_and_set(MSR_SPE);
 425
 426         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 427                 check_if_tm_restore_required(current);
 428                 __giveup_spe(current);
 429         }
 430 }
 431 EXPORT_SYMBOL(enable_kernel_spe);
 432
 433 void flush_spe_to_thread(struct task_struct *tsk)
 434 {
 435         if (tsk->thread.regs) {
 436                 preempt_disable();
 437                 if (tsk->thread.regs->msr & MSR_SPE) {
 438                         BUG_ON(tsk != current);
 439                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 440                         giveup_spe(tsk);
 441                 }
 442                 preempt_enable();
 443         }
 444 }
 445 #endif /* CONFIG_SPE */
 446
 447 static unsigned long msr_all_available;
 448
 449 static int __init init_msr_all_available(void)
 450 {
 451 #ifdef CONFIG_PPC_FPU
 452         msr_all_available |= MSR_FP;
 453 #endif
 454 #ifdef CONFIG_ALTIVEC
 455         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 456                 msr_all_available |= MSR_VEC;
 457 #endif
 458 #ifdef CONFIG_VSX
 459         if (cpu_has_feature(CPU_FTR_VSX))
 460                 msr_all_available |= MSR_VSX;
 461 #endif
 462 #ifdef CONFIG_SPE
 463         if (cpu_has_feature(CPU_FTR_SPE))
 464                 msr_all_available |= MSR_SPE;
 465 #endif
 466
 467         return 0;
 468 }
 469 early_initcall(init_msr_all_available);
 470
 471 void giveup_all(struct task_struct *tsk)
 472 {
 473         unsigned long usermsr;
 474
 475         if (!tsk->thread.regs)
 476                 return;
 477
 478         usermsr = tsk->thread.regs->msr;
 479
 480         if ((usermsr & msr_all_available) == 0)
 481                 return;
 482
 483         msr_check_and_set(msr_all_available);
 484         check_if_tm_restore_required(tsk);
 485
 486 #ifdef CONFIG_PPC_FPU
 487         if (usermsr & MSR_FP)
 488                 __giveup_fpu(tsk);
 489 #endif
 490 #ifdef CONFIG_ALTIVEC
 491         if (usermsr & MSR_VEC)
 492                 __giveup_altivec(tsk);
 493 #endif
 494 #ifdef CONFIG_VSX
 495         if (usermsr & MSR_VSX)
 496                 __giveup_vsx(tsk);
 497 #endif
 498 #ifdef CONFIG_SPE
 499         if (usermsr & MSR_SPE)
 500                 __giveup_spe(tsk);
 501 #endif
 502
 503         msr_check_and_clear(msr_all_available);
 504 }
 505 EXPORT_SYMBOL(giveup_all);
 506
 507 void restore_math(struct pt_regs *regs)
 508 {
 509         unsigned long msr;
 510
 511         if (!msr_tm_active(regs->msr) &&
 512                 !current->thread.load_fp && !loadvec(current->thread))
 513                 return;
 514
 515         msr = regs->msr;
 516         msr_check_and_set(msr_all_available);
 517
 518         /*
 519          * Only reload if the bit is not set in the user MSR, the bit BEING set
 520          * indicates that the registers are hot
 521          */
 522         if ((!(msr & MSR_FP)) && restore_fp(current))
 523                 msr |= MSR_FP | current->thread.fpexc_mode;
 524
 525         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 526                 msr |= MSR_VEC;
 527
 528         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 529                         restore_vsx(current)) {
 530                 msr |= MSR_VSX;
 531         }
 532
 533         msr_check_and_clear(msr_all_available);
 534
 535         regs->msr = msr;
 536 }
 537
 538 void save_all(struct task_struct *tsk)
 539 {
 540         unsigned long usermsr;
 541
 542         if (!tsk->thread.regs)
 543                 return;
 544
 545         usermsr = tsk->thread.regs->msr;
 546
 547         if ((usermsr & msr_all_available) == 0)
 548                 return;
 549
 550         msr_check_and_set(msr_all_available);
 551
 552         /*
 553          * Saving the way the register space is in hardware, save_vsx boils
 554          * down to a save_fpu() and save_altivec()
 555          */
 556         if (usermsr & MSR_VSX) {
 557                 save_vsx(tsk);
 558         } else {
 559                 if (usermsr & MSR_FP)
 560                         save_fpu(tsk);
 561
 562                 if (usermsr & MSR_VEC)
 563                         save_altivec(tsk);
 564         }
 565
 566         if (usermsr & MSR_SPE)
 567                 __giveup_spe(tsk);
 568
 569         msr_check_and_clear(msr_all_available);
 570 }
 571
 572 void flush_all_to_thread(struct task_struct *tsk)
 573 {
 574         if (tsk->thread.regs) {
 575                 preempt_disable();
 576                 BUG_ON(tsk != current);
 577                 save_all(tsk);
 578
 579 #ifdef CONFIG_SPE
 580                 if (tsk->thread.regs->msr & MSR_SPE)
 581                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 582 #endif
 583
 584                 preempt_enable();
 585         }
 586 }
 587 EXPORT_SYMBOL(flush_all_to_thread);
 588
 589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 590 void do_send_trap(struct pt_regs *regs, unsigned long address,
 591                   unsigned long error_code, int signal_code, int breakpt)
 592 {
 593         siginfo_t info;
 594
 595         current->thread.trap_nr = signal_code;
 596         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 597                         11, SIGSEGV) == NOTIFY_STOP)
 598                 return;
 599
 600         /* Deliver the signal to userspace */
 601         info.si_signo = SIGTRAP;
 602         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 603         info.si_code = signal_code;
 604         info.si_addr = (void __user *)address;
 605         force_sig_info(SIGTRAP, &info, current);
 606 }
 607 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 608 void do_break (struct pt_regs *regs, unsigned long address,
 609                     unsigned long error_code)
 610 {
 611         siginfo_t info;
 612
 613         current->thread.trap_nr = TRAP_HWBKPT;
 614         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 615                         11, SIGSEGV) == NOTIFY_STOP)
 616                 return;
 617
 618         if (debugger_break_match(regs))
 619                 return;
 620
 621         /* Clear the breakpoint */
 622         hw_breakpoint_disable();
 623
 624         /* Deliver the signal to userspace */
 625         info.si_signo = SIGTRAP;
 626         info.si_errno = 0;
 627         info.si_code = TRAP_HWBKPT;
 628         info.si_addr = (void __user *)address;
 629         force_sig_info(SIGTRAP, &info, current);
 630 }
 631 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 632
 633 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 634
 635 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 636 /*
 637  * Set the debug registers back to their default "safe" values.
 638  */
 639 static void set_debug_reg_defaults(struct thread_struct *thread)
 640 {
 641         thread->debug.iac1 = thread->debug.iac2 = 0;
 642 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 643         thread->debug.iac3 = thread->debug.iac4 = 0;
 644 #endif
 645         thread->debug.dac1 = thread->debug.dac2 = 0;
 646 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 647         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 648 #endif
 649         thread->debug.dbcr0 = 0;
 650 #ifdef CONFIG_BOOKE
 651         /*
 652          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 653          */
 654         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 655                         DBCR1_IAC3US | DBCR1_IAC4US;
 656         /*
 657          * Force Data Address Compare User/Supervisor bits to be User-only
 658          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 659          */
 660         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 661 #else
 662         thread->debug.dbcr1 = 0;
 663 #endif
 664 }
 665
 666 static void prime_debug_regs(struct debug_reg *debug)
 667 {
 668         /*
 669          * We could have inherited MSR_DE from userspace, since
 670          * it doesn't get cleared on exception entry.  Make sure
 671          * MSR_DE is clear before we enable any debug events.
 672          */
 673         mtmsr(mfmsr() & ~MSR_DE);
 674
 675         mtspr(SPRN_IAC1, debug->iac1);
 676         mtspr(SPRN_IAC2, debug->iac2);
 677 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 678         mtspr(SPRN_IAC3, debug->iac3);
 679         mtspr(SPRN_IAC4, debug->iac4);
 680 #endif
 681         mtspr(SPRN_DAC1, debug->dac1);
 682         mtspr(SPRN_DAC2, debug->dac2);
 683 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 684         mtspr(SPRN_DVC1, debug->dvc1);
 685         mtspr(SPRN_DVC2, debug->dvc2);
 686 #endif
 687         mtspr(SPRN_DBCR0, debug->dbcr0);
 688         mtspr(SPRN_DBCR1, debug->dbcr1);
 689 #ifdef CONFIG_BOOKE
 690         mtspr(SPRN_DBCR2, debug->dbcr2);
 691 #endif
 692 }
 693 /*
 694  * Unless neither the old or new thread are making use of the
 695  * debug registers, set the debug registers from the values
 696  * stored in the new thread.
 697  */
 698 void switch_booke_debug_regs(struct debug_reg *new_debug)
 699 {
 700         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 701                 || (new_debug->dbcr0 & DBCR0_IDM))
 702                         prime_debug_regs(new_debug);
 703 }
 704 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 705 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 706 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 707 static void set_debug_reg_defaults(struct thread_struct *thread)
 708 {
 709         thread->hw_brk.address = 0;
 710         thread->hw_brk.type = 0;
 711         set_breakpoint(&thread->hw_brk);
 712 }
 713 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 714 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 715
 716 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 717 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 718 {
 719         mtspr(SPRN_DAC1, dabr);
 720 #ifdef CONFIG_PPC_47x
 721         isync();
 722 #endif
 723         return 0;
 724 }
 725 #elif defined(CONFIG_PPC_BOOK3S)
 726 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 727 {
 728         mtspr(SPRN_DABR, dabr);
 729         if (cpu_has_feature(CPU_FTR_DABRX))
 730                 mtspr(SPRN_DABRX, dabrx);
 731         return 0;
 732 }
 733 #else
 734 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 735 {
 736         return -EINVAL;
 737 }
 738 #endif
 739
 740 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 741 {
 742         unsigned long dabr, dabrx;
 743
 744         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 745         dabrx = ((brk->type >> 3) & 0x7);
 746
 747         if (ppc_md.set_dabr)
 748                 return ppc_md.set_dabr(dabr, dabrx);
 749
 750         return __set_dabr(dabr, dabrx);
 751 }
 752
 753 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 754 {
 755         unsigned long dawr, dawrx, mrd;
 756
 757         dawr = brk->address;
 758
 759         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 760                                    << (63 - 58); //* read/write bits */
 761         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 762                                    << (63 - 59); //* translate */
 763         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 764                                    >> 3; //* PRIM bits */
 765         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 766            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 767            0b111111=64DW.
 768            brk->len is in bytes.
 769            This aligns up to double word size, shifts and does the bias.
 770         */
 771         mrd = ((brk->len + 7) >> 3) - 1;
 772         dawrx |= (mrd & 0x3f) << (63 - 53);
 773
 774         if (ppc_md.set_dawr)
 775                 return ppc_md.set_dawr(dawr, dawrx);
 776         mtspr(SPRN_DAWR, dawr);
 777         mtspr(SPRN_DAWRX, dawrx);
 778         return 0;
 779 }
 780
 781 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 782 {
 783         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 784
 785         if (cpu_has_feature(CPU_FTR_DAWR))
 786                 set_dawr(brk);
 787         else
 788                 set_dabr(brk);
 789 }
 790
 791 void set_breakpoint(struct arch_hw_breakpoint *brk)
 792 {
 793         preempt_disable();
 794         __set_breakpoint(brk);
 795         preempt_enable();
 796 }
 797
 798 #ifdef CONFIG_PPC64
 799 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 800 #endif
 801
 802 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 803                               struct arch_hw_breakpoint *b)
 804 {
 805         if (a->address != b->address)
 806                 return false;
 807         if (a->type != b->type)
 808                 return false;
 809         if (a->len != b->len)
 810                 return false;
 811         return true;
 812 }
 813
 814 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 815 static void tm_reclaim_thread(struct thread_struct *thr,
 816                               struct thread_info *ti, uint8_t cause)
 817 {
 818         /*
 819          * Use the current MSR TM suspended bit to track if we have
 820          * checkpointed state outstanding.
 821          * On signal delivery, we'd normally reclaim the checkpointed
 822          * state to obtain stack pointer (see:get_tm_stackpointer()).
 823          * This will then directly return to userspace without going
 824          * through __switch_to(). However, if the stack frame is bad,
 825          * we need to exit this thread which calls __switch_to() which
 826          * will again attempt to reclaim the already saved tm state.
 827          * Hence we need to check that we've not already reclaimed
 828          * this state.
 829          * We do this using the current MSR, rather tracking it in
 830          * some specific thread_struct bit, as it has the additional
 831          * benefit of checking for a potential TM bad thing exception.
 832          */
 833         if (!MSR_TM_SUSPENDED(mfmsr()))
 834                 return;
 835
 836         giveup_all(container_of(thr, struct task_struct, thread));
 837
 838         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 839 }
 840
 841 void tm_reclaim_current(uint8_t cause)
 842 {
 843         tm_enable();
 844         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 845 }
 846
 847 static inline void tm_reclaim_task(struct task_struct *tsk)
 848 {
 849         /* We have to work out if we're switching from/to a task that's in the
 850          * middle of a transaction.
 851          *
 852          * In switching we need to maintain a 2nd register state as
 853          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 854          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 855          * (current) FPRs into oldtask->thread.transact_fpr[].
 856          *
 857          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 858          */
 859         struct thread_struct *thr = &tsk->thread;
 860
 861         if (!thr->regs)
 862                 return;
 863
 864         if (!MSR_TM_ACTIVE(thr->regs->msr))
 865                 goto out_and_saveregs;
 866
 867         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 868                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 869                  tsk->pid, thr->regs->nip,
 870                  thr->regs->ccr, thr->regs->msr,
 871                  thr->regs->trap);
 872
 873         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 874
 875         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 876                  tsk->pid);
 877
 878 out_and_saveregs:
 879         /* Always save the regs here, even if a transaction's not active.
 880          * This context-switches a thread's TM info SPRs.  We do it here to
 881          * be consistent with the restore path (in recheckpoint) which
 882          * cannot happen later in _switch().
 883          */
 884         tm_save_sprs(thr);
 885 }
 886
 887 extern void __tm_recheckpoint(struct thread_struct *thread,
 888                               unsigned long orig_msr);
 889
 890 void tm_recheckpoint(struct thread_struct *thread,
 891                      unsigned long orig_msr)
 892 {
 893         unsigned long flags;
 894
 895         /* We really can't be interrupted here as the TEXASR registers can't
 896          * change and later in the trecheckpoint code, we have a userspace R1.
 897          * So let's hard disable over this region.
 898          */
 899         local_irq_save(flags);
 900         hard_irq_disable();
 901
 902         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 903          * before the trecheckpoint and no explosion occurs.
 904          */
 905         tm_restore_sprs(thread);
 906
 907         __tm_recheckpoint(thread, orig_msr);
 908
 909         local_irq_restore(flags);
 910 }
 911
 912 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 913 {
 914         unsigned long msr;
 915
 916         if (!cpu_has_feature(CPU_FTR_TM))
 917                 return;
 918
 919         /* Recheckpoint the registers of the thread we're about to switch to.
 920          *
 921          * If the task was using FP, we non-lazily reload both the original and
 922          * the speculative FP register states.  This is because the kernel
 923          * doesn't see if/when a TM rollback occurs, so if we take an FP
 924          * unavailable later, we are unable to determine which set of FP regs
 925          * need to be restored.
 926          */
 927         if (!new->thread.regs)
 928                 return;
 929
 930         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 931                 tm_restore_sprs(&new->thread);
 932                 return;
 933         }
 934         msr = new->thread.ckpt_regs.msr;
 935         /* Recheckpoint to restore original checkpointed register state. */
 936         TM_DEBUG("*** tm_recheckpoint of pid %d "
 937                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 938                  new->pid, new->thread.regs->msr, msr);
 939
 940         tm_recheckpoint(&new->thread, msr);
 941
 942         /*
 943          * The checkpointed state has been restored but the live state has
 944          * not, ensure all the math functionality is turned off to trigger
 945          * restore_math() to reload.
 946          */
 947         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
 948
 949         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 950                  "(kernel msr 0x%lx)\n",
 951                  new->pid, mfmsr());
 952 }
 953
 954 static inline void __switch_to_tm(struct task_struct *prev,
 955                 struct task_struct *new)
 956 {
 957         if (cpu_has_feature(CPU_FTR_TM)) {
 958                 tm_enable();
 959                 tm_reclaim_task(prev);
 960                 tm_recheckpoint_new_task(new);
 961         }
 962 }
 963
 964 /*
 965  * This is called if we are on the way out to userspace and the
 966  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 967  * FP and/or vector state and does so if necessary.
 968  * If userspace is inside a transaction (whether active or
 969  * suspended) and FP/VMX/VSX instructions have ever been enabled
 970  * inside that transaction, then we have to keep them enabled
 971  * and keep the FP/VMX/VSX state loaded while ever the transaction
 972  * continues.  The reason is that if we didn't, and subsequently
 973  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 974  * we don't know whether it's the same transaction, and thus we
 975  * don't know which of the checkpointed state and the transactional
 976  * state to use.
 977  */
 978 void restore_tm_state(struct pt_regs *regs)
 979 {
 980         unsigned long msr_diff;
 981
 982         /*
 983          * This is the only moment we should clear TIF_RESTORE_TM as
 984          * it is here that ckpt_regs.msr and pt_regs.msr become the same
 985          * again, anything else could lead to an incorrect ckpt_msr being
 986          * saved and therefore incorrect signal contexts.
 987          */
 988         clear_thread_flag(TIF_RESTORE_TM);
 989         if (!MSR_TM_ACTIVE(regs->msr))
 990                 return;
 991
 992         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 993         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 994
 995         /* Ensure that restore_math() will restore */
 996         if (msr_diff & MSR_FP)
 997                 current->thread.load_fp = 1;
 998 #ifdef CONFIG_ALIVEC
 999         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1000                 current->thread.load_vec = 1;
1001 #endif
1002         restore_math(regs);
1003
1004         regs->msr |= msr_diff;
1005 }
1006
1007 #else
1008 #define tm_recheckpoint_new_task(new)
1009 #define __switch_to_tm(prev, new)
1010 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1011
1012 static inline void save_sprs(struct thread_struct *t)
1013 {
1014 #ifdef CONFIG_ALTIVEC
1015         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1016                 t->vrsave = mfspr(SPRN_VRSAVE);
1017 #endif
1018 #ifdef CONFIG_PPC_BOOK3S_64
1019         if (cpu_has_feature(CPU_FTR_DSCR))
1020                 t->dscr = mfspr(SPRN_DSCR);
1021
1022         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1023                 t->bescr = mfspr(SPRN_BESCR);
1024                 t->ebbhr = mfspr(SPRN_EBBHR);
1025                 t->ebbrr = mfspr(SPRN_EBBRR);
1026
1027                 t->fscr = mfspr(SPRN_FSCR);
1028
1029                 /*
1030                  * Note that the TAR is not available for use in the kernel.
1031                  * (To provide this, the TAR should be backed up/restored on
1032                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1033                  * this should be in pt_regs anyway (for debug).)
1034                  */
1035                 t->tar = mfspr(SPRN_TAR);
1036         }
1037
1038         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1039                 /* Conditionally save Load Monitor registers, if enabled */
1040                 if (t->fscr & FSCR_LM) {
1041                         t->lmrr = mfspr(SPRN_LMRR);
1042                         t->lmser = mfspr(SPRN_LMSER);
1043                 }
1044         }
1045 #endif
1046 }
1047
1048 static inline void restore_sprs(struct thread_struct *old_thread,
1049                                 struct thread_struct *new_thread)
1050 {
1051 #ifdef CONFIG_ALTIVEC
1052         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1053             old_thread->vrsave != new_thread->vrsave)
1054                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1055 #endif
1056 #ifdef CONFIG_PPC_BOOK3S_64
1057         if (cpu_has_feature(CPU_FTR_DSCR)) {
1058                 u64 dscr = get_paca()->dscr_default;
1059                 if (new_thread->dscr_inherit)
1060                         dscr = new_thread->dscr;
1061
1062                 if (old_thread->dscr != dscr)
1063                         mtspr(SPRN_DSCR, dscr);
1064         }
1065
1066         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1067                 if (old_thread->bescr != new_thread->bescr)
1068                         mtspr(SPRN_BESCR, new_thread->bescr);
1069                 if (old_thread->ebbhr != new_thread->ebbhr)
1070                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1071                 if (old_thread->ebbrr != new_thread->ebbrr)
1072                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1073
1074                 if (old_thread->fscr != new_thread->fscr)
1075                         mtspr(SPRN_FSCR, new_thread->fscr);
1076
1077                 if (old_thread->tar != new_thread->tar)
1078                         mtspr(SPRN_TAR, new_thread->tar);
1079         }
1080
1081         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1082                 /* Conditionally restore Load Monitor registers, if enabled */
1083                 if (new_thread->fscr & FSCR_LM) {
1084                         if (old_thread->lmrr != new_thread->lmrr)
1085                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1086                         if (old_thread->lmser != new_thread->lmser)
1087                                 mtspr(SPRN_LMSER, new_thread->lmser);
1088                 }
1089         }
1090 #endif
1091 }
1092
1093 struct task_struct *__switch_to(struct task_struct *prev,
1094         struct task_struct *new)
1095 {
1096         struct thread_struct *new_thread, *old_thread;
1097         struct task_struct *last;
1098 #ifdef CONFIG_PPC_BOOK3S_64
1099         struct ppc64_tlb_batch *batch;
1100 #endif
1101
1102         new_thread = &new->thread;
1103         old_thread = &current->thread;
1104
1105         WARN_ON(!irqs_disabled());
1106
1107 #ifdef CONFIG_PPC64
1108         /*
1109          * Collect processor utilization data per process
1110          */
1111         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1112                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1113                 long unsigned start_tb, current_tb;
1114                 start_tb = old_thread->start_tb;
1115                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1116                 old_thread->accum_tb += (current_tb - start_tb);
1117                 new_thread->start_tb = current_tb;
1118         }
1119 #endif /* CONFIG_PPC64 */
1120
1121 #ifdef CONFIG_PPC_STD_MMU_64
1122         batch = this_cpu_ptr(&ppc64_tlb_batch);
1123         if (batch->active) {
1124                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1125                 if (batch->index)
1126                         __flush_tlb_pending(batch);
1127                 batch->active = 0;
1128         }
1129 #endif /* CONFIG_PPC_STD_MMU_64 */
1130
1131 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1132         switch_booke_debug_regs(&new->thread.debug);
1133 #else
1134 /*
1135  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1136  * schedule DABR
1137  */
1138 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1139         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1140                 __set_breakpoint(&new->thread.hw_brk);
1141 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1142 #endif
1143
1144         /*
1145          * We need to save SPRs before treclaim/trecheckpoint as these will
1146          * change a number of them.
1147          */
1148         save_sprs(&prev->thread);
1149
1150         /* Save FPU, Altivec, VSX and SPE state */
1151         giveup_all(prev);
1152
1153         __switch_to_tm(prev, new);
1154
1155         /*
1156          * We can't take a PMU exception inside _switch() since there is a
1157          * window where the kernel stack SLB and the kernel stack are out
1158          * of sync. Hard disable here.
1159          */
1160         hard_irq_disable();
1161
1162         /*
1163          * Call restore_sprs() before calling _switch(). If we move it after
1164          * _switch() then we miss out on calling it for new tasks. The reason
1165          * for this is we manually create a stack frame for new tasks that
1166          * directly returns through ret_from_fork() or
1167          * ret_from_kernel_thread(). See copy_thread() for details.
1168          */
1169         restore_sprs(old_thread, new_thread);
1170
1171         last = _switch(old_thread, new_thread);
1172
1173 #ifdef CONFIG_PPC_STD_MMU_64
1174         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1175                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1176                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1177                 batch->active = 1;
1178         }
1179
1180         if (current_thread_info()->task->thread.regs)
1181                 restore_math(current_thread_info()->task->thread.regs);
1182 #endif /* CONFIG_PPC_STD_MMU_64 */
1183
1184         return last;
1185 }
1186
1187 static int instructions_to_print = 16;
1188
1189 static void show_instructions(struct pt_regs *regs)
1190 {
1191         int i;
1192         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1193                         sizeof(int));
1194
1195         printk("Instruction dump:");
1196
1197         for (i = 0; i < instructions_to_print; i++) {
1198                 int instr;
1199
1200                 if (!(i % 8))
1201                         printk("\n");
1202
1203 #if !defined(CONFIG_BOOKE)
1204                 /* If executing with the IMMU off, adjust pc rather
1205                  * than print XXXXXXXX.
1206                  */
1207                 if (!(regs->msr & MSR_IR))
1208                         pc = (unsigned long)phys_to_virt(pc);
1209 #endif
1210
1211                 if (!__kernel_text_address(pc) ||
1212                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1213                         printk(KERN_CONT "XXXXXXXX ");
1214                 } else {
1215                         if (regs->nip == pc)
1216                                 printk(KERN_CONT "<%08x> ", instr);
1217                         else
1218                                 printk(KERN_CONT "%08x ", instr);
1219                 }
1220
1221                 pc += sizeof(int);
1222         }
1223
1224         printk("\n");
1225 }
1226
1227 struct regbit {
1228         unsigned long bit;
1229         const char *name;
1230 };
1231
1232 static struct regbit msr_bits[] = {
1233 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1234         {MSR_SF,        "SF"},
1235         {MSR_HV,        "HV"},
1236 #endif
1237         {MSR_VEC,       "VEC"},
1238         {MSR_VSX,       "VSX"},
1239 #ifdef CONFIG_BOOKE
1240         {MSR_CE,        "CE"},
1241 #endif
1242         {MSR_EE,        "EE"},
1243         {MSR_PR,        "PR"},
1244         {MSR_FP,        "FP"},
1245         {MSR_ME,        "ME"},
1246 #ifdef CONFIG_BOOKE
1247         {MSR_DE,        "DE"},
1248 #else
1249         {MSR_SE,        "SE"},
1250         {MSR_BE,        "BE"},
1251 #endif
1252         {MSR_IR,        "IR"},
1253         {MSR_DR,        "DR"},
1254         {MSR_PMM,       "PMM"},
1255 #ifndef CONFIG_BOOKE
1256         {MSR_RI,        "RI"},
1257         {MSR_LE,        "LE"},
1258 #endif
1259         {0,             NULL}
1260 };
1261
1262 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1263 {
1264         const char *s = "";
1265
1266         for (; bits->bit; ++bits)
1267                 if (val & bits->bit) {
1268                         printk("%s%s", s, bits->name);
1269                         s = sep;
1270                 }
1271 }
1272
1273 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1274 static struct regbit msr_tm_bits[] = {
1275         {MSR_TS_T,      "T"},
1276         {MSR_TS_S,      "S"},
1277         {MSR_TM,        "E"},
1278         {0,             NULL}
1279 };
1280
1281 static void print_tm_bits(unsigned long val)
1282 {
1283 /*
1284  * This only prints something if at least one of the TM bit is set.
1285  * Inside the TM[], the output means:
1286  *   E: Enabled         (bit 32)
1287  *   S: Suspended       (bit 33)
1288  *   T: Transactional   (bit 34)
1289  */
1290         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1291                 printk(",TM[");
1292                 print_bits(val, msr_tm_bits, "");
1293                 printk("]");
1294         }
1295 }
1296 #else
1297 static void print_tm_bits(unsigned long val) {}
1298 #endif
1299
1300 static void print_msr_bits(unsigned long val)
1301 {
1302         printk("<");
1303         print_bits(val, msr_bits, ",");
1304         print_tm_bits(val);
1305         printk(">");
1306 }
1307
1308 #ifdef CONFIG_PPC64
1309 #define REG             "%016lx"
1310 #define REGS_PER_LINE   4
1311 #define LAST_VOLATILE   13
1312 #else
1313 #define REG             "%08lx"
1314 #define REGS_PER_LINE   8
1315 #define LAST_VOLATILE   12
1316 #endif
1317
1318 void show_regs(struct pt_regs * regs)
1319 {
1320         int i, trap;
1321
1322         show_regs_print_info(KERN_DEFAULT);
1323
1324         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1325                regs->nip, regs->link, regs->ctr);
1326         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1327                regs, regs->trap, print_tainted(), init_utsname()->release);
1328         printk("MSR: "REG" ", regs->msr);
1329         print_msr_bits(regs->msr);
1330         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1331         trap = TRAP(regs);
1332         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1333                 printk("CFAR: "REG" ", regs->orig_gpr3);
1334         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1335 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1336                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1337 #else
1338                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1339 #endif
1340 #ifdef CONFIG_PPC64
1341         printk("SOFTE: %ld ", regs->softe);
1342 #endif
1343 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1344         if (MSR_TM_ACTIVE(regs->msr))
1345                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1346 #endif
1347
1348         for (i = 0;  i < 32;  i++) {
1349                 if ((i % REGS_PER_LINE) == 0)
1350                         printk("\nGPR%02d: ", i);
1351                 printk(REG " ", regs->gpr[i]);
1352                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1353                         break;
1354         }
1355         printk("\n");
1356 #ifdef CONFIG_KALLSYMS
1357         /*
1358          * Lookup NIP late so we have the best change of getting the
1359          * above info out without failing
1360          */
1361         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1362         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1363 #endif
1364         show_stack(current, (unsigned long *) regs->gpr[1]);
1365         if (!user_mode(regs))
1366                 show_instructions(regs);
1367 }
1368
1369 void flush_thread(void)
1370 {
1371 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1372         flush_ptrace_hw_breakpoint(current);
1373 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1374         set_debug_reg_defaults(&current->thread);
1375 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1376 }
1377
1378 void
1379 release_thread(struct task_struct *t)
1380 {
1381 }
1382
1383 /*
1384  * this gets called so that we can store coprocessor state into memory and
1385  * copy the current task into the new thread.
1386  */
1387 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1388 {
1389         flush_all_to_thread(src);
1390         /*
1391          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1392          * flush but it removes the checkpointed state from the current CPU and
1393          * transitions the CPU out of TM mode.  Hence we need to call
1394          * tm_recheckpoint_new_task() (on the same task) to restore the
1395          * checkpointed state back and the TM mode.
1396          */
1397         __switch_to_tm(src, src);
1398
1399         *dst = *src;
1400
1401         clear_task_ebb(dst);
1402
1403         return 0;
1404 }
1405
1406 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1407 {
1408 #ifdef CONFIG_PPC_STD_MMU_64
1409         unsigned long sp_vsid;
1410         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1411
1412         if (radix_enabled())
1413                 return;
1414
1415         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1416                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1417                         << SLB_VSID_SHIFT_1T;
1418         else
1419                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1420                         << SLB_VSID_SHIFT;
1421         sp_vsid |= SLB_VSID_KERNEL | llp;
1422         p->thread.ksp_vsid = sp_vsid;
1423 #endif
1424 }
1425
1426 /*
1427  * Copy a thread..
1428  */
1429
1430 /*
1431  * Copy architecture-specific thread state
1432  */
1433 int copy_thread(unsigned long clone_flags, unsigned long usp,
1434                 unsigned long kthread_arg, struct task_struct *p)
1435 {
1436         struct pt_regs *childregs, *kregs;
1437         extern void ret_from_fork(void);
1438         extern void ret_from_kernel_thread(void);
1439         void (*f)(void);
1440         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1441         struct thread_info *ti = task_thread_info(p);
1442
1443         klp_init_thread_info(ti);
1444
1445         /* Copy registers */
1446         sp -= sizeof(struct pt_regs);
1447         childregs = (struct pt_regs *) sp;
1448         if (unlikely(p->flags & PF_KTHREAD)) {
1449                 /* kernel thread */
1450                 memset(childregs, 0, sizeof(struct pt_regs));
1451                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1452                 /* function */
1453                 if (usp)
1454                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1455 #ifdef CONFIG_PPC64
1456                 clear_tsk_thread_flag(p, TIF_32BIT);
1457                 childregs->softe = 1;
1458 #endif
1459                 childregs->gpr[15] = kthread_arg;
1460                 p->thread.regs = NULL;  /* no user register state */
1461                 ti->flags |= _TIF_RESTOREALL;
1462                 f = ret_from_kernel_thread;
1463         } else {
1464                 /* user thread */
1465                 struct pt_regs *regs = current_pt_regs();
1466                 CHECK_FULL_REGS(regs);
1467                 *childregs = *regs;
1468                 if (usp)
1469                         childregs->gpr[1] = usp;
1470                 p->thread.regs = childregs;
1471                 childregs->gpr[3] = 0;  /* Result from fork() */
1472                 if (clone_flags & CLONE_SETTLS) {
1473 #ifdef CONFIG_PPC64
1474                         if (!is_32bit_task())
1475                                 childregs->gpr[13] = childregs->gpr[6];
1476                         else
1477 #endif
1478                                 childregs->gpr[2] = childregs->gpr[6];
1479                 }
1480
1481                 f = ret_from_fork;
1482         }
1483         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1484         sp -= STACK_FRAME_OVERHEAD;
1485
1486         /*
1487          * The way this works is that at some point in the future
1488          * some task will call _switch to switch to the new task.
1489          * That will pop off the stack frame created below and start
1490          * the new task running at ret_from_fork.  The new task will
1491          * do some house keeping and then return from the fork or clone
1492          * system call, using the stack frame created above.
1493          */
1494         ((unsigned long *)sp)[0] = 0;
1495         sp -= sizeof(struct pt_regs);
1496         kregs = (struct pt_regs *) sp;
1497         sp -= STACK_FRAME_OVERHEAD;
1498         p->thread.ksp = sp;
1499 #ifdef CONFIG_PPC32
1500         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1501                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1502 #endif
1503 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1504         p->thread.ptrace_bps[0] = NULL;
1505 #endif
1506
1507         p->thread.fp_save_area = NULL;
1508 #ifdef CONFIG_ALTIVEC
1509         p->thread.vr_save_area = NULL;
1510 #endif
1511
1512         setup_ksp_vsid(p, sp);
1513
1514 #ifdef CONFIG_PPC64
1515         if (cpu_has_feature(CPU_FTR_DSCR)) {
1516                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1517                 p->thread.dscr = mfspr(SPRN_DSCR);
1518         }
1519         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1520                 p->thread.ppr = INIT_PPR;
1521 #endif
1522         kregs->nip = ppc_function_entry(f);
1523         return 0;
1524 }
1525
1526 /*
1527  * Set up a thread for executing a new program
1528  */
1529 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1530 {
1531 #ifdef CONFIG_PPC64
1532         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1533 #endif
1534
1535         /*
1536          * If we exec out of a kernel thread then thread.regs will not be
1537          * set.  Do it now.
1538          */
1539         if (!current->thread.regs) {
1540                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1541                 current->thread.regs = regs - 1;
1542         }
1543
1544 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1545         /*
1546          * Clear any transactional state, we're exec()ing. The cause is
1547          * not important as there will never be a recheckpoint so it's not
1548          * user visible.
1549          */
1550         if (MSR_TM_SUSPENDED(mfmsr()))
1551                 tm_reclaim_current(0);
1552 #endif
1553
1554         memset(regs->gpr, 0, sizeof(regs->gpr));
1555         regs->ctr = 0;
1556         regs->link = 0;
1557         regs->xer = 0;
1558         regs->ccr = 0;
1559         regs->gpr[1] = sp;
1560
1561         /*
1562          * We have just cleared all the nonvolatile GPRs, so make
1563          * FULL_REGS(regs) return true.  This is necessary to allow
1564          * ptrace to examine the thread immediately after exec.
1565          */
1566         regs->trap &= ~1UL;
1567
1568 #ifdef CONFIG_PPC32
1569         regs->mq = 0;
1570         regs->nip = start;
1571         regs->msr = MSR_USER;
1572 #else
1573         if (!is_32bit_task()) {
1574                 unsigned long entry;
1575
1576                 if (is_elf2_task()) {
1577                         /* Look ma, no function descriptors! */
1578                         entry = start;
1579
1580                         /*
1581                          * Ulrich says:
1582                          *   The latest iteration of the ABI requires that when
1583                          *   calling a function (at its global entry point),
1584                          *   the caller must ensure r12 holds the entry point
1585                          *   address (so that the function can quickly
1586                          *   establish addressability).
1587                          */
1588                         regs->gpr[12] = start;
1589                         /* Make sure that's restored on entry to userspace. */
1590                         set_thread_flag(TIF_RESTOREALL);
1591                 } else {
1592                         unsigned long toc;
1593
1594                         /* start is a relocated pointer to the function
1595                          * descriptor for the elf _start routine.  The first
1596                          * entry in the function descriptor is the entry
1597                          * address of _start and the second entry is the TOC
1598                          * value we need to use.
1599                          */
1600                         __get_user(entry, (unsigned long __user *)start);
1601                         __get_user(toc, (unsigned long __user *)start+1);
1602
1603                         /* Check whether the e_entry function descriptor entries
1604                          * need to be relocated before we can use them.
1605                          */
1606                         if (load_addr != 0) {
1607                                 entry += load_addr;
1608                                 toc   += load_addr;
1609                         }
1610                         regs->gpr[2] = toc;
1611                 }
1612                 regs->nip = entry;
1613                 regs->msr = MSR_USER64;
1614         } else {
1615                 regs->nip = start;
1616                 regs->gpr[2] = 0;
1617                 regs->msr = MSR_USER32;
1618         }
1619 #endif
1620 #ifdef CONFIG_VSX
1621         current->thread.used_vsr = 0;
1622 #endif
1623         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1624         current->thread.fp_save_area = NULL;
1625 #ifdef CONFIG_ALTIVEC
1626         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1627         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1628         current->thread.vr_save_area = NULL;
1629         current->thread.vrsave = 0;
1630         current->thread.used_vr = 0;
1631 #endif /* CONFIG_ALTIVEC */
1632 #ifdef CONFIG_SPE
1633         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1634         current->thread.acc = 0;
1635         current->thread.spefscr = 0;
1636         current->thread.used_spe = 0;
1637 #endif /* CONFIG_SPE */
1638 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1639         if (cpu_has_feature(CPU_FTR_TM))
1640                 regs->msr |= MSR_TM;
1641         current->thread.tm_tfhar = 0;
1642         current->thread.tm_texasr = 0;
1643         current->thread.tm_tfiar = 0;
1644 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1645 }
1646 EXPORT_SYMBOL(start_thread);
1647
1648 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1649                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1650
1651 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1652 {
1653         struct pt_regs *regs = tsk->thread.regs;
1654
1655         /* This is a bit hairy.  If we are an SPE enabled  processor
1656          * (have embedded fp) we store the IEEE exception enable flags in
1657          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1658          * mode (asyn, precise, disabled) for 'Classic' FP. */
1659         if (val & PR_FP_EXC_SW_ENABLE) {
1660 #ifdef CONFIG_SPE
1661                 if (cpu_has_feature(CPU_FTR_SPE)) {
1662                         /*
1663                          * When the sticky exception bits are set
1664                          * directly by userspace, it must call prctl
1665                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1666                          * in the existing prctl settings) or
1667                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1668                          * the bits being set).  <fenv.h> functions
1669                          * saving and restoring the whole
1670                          * floating-point environment need to do so
1671                          * anyway to restore the prctl settings from
1672                          * the saved environment.
1673                          */
1674                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1675                         tsk->thread.fpexc_mode = val &
1676                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1677                         return 0;
1678                 } else {
1679                         return -EINVAL;
1680                 }
1681 #else
1682                 return -EINVAL;
1683 #endif
1684         }
1685
1686         /* on a CONFIG_SPE this does not hurt us.  The bits that
1687          * __pack_fe01 use do not overlap with bits used for
1688          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1689          * on CONFIG_SPE implementations are reserved so writing to
1690          * them does not change anything */
1691         if (val > PR_FP_EXC_PRECISE)
1692                 return -EINVAL;
1693         tsk->thread.fpexc_mode = __pack_fe01(val);
1694         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1695                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1696                         | tsk->thread.fpexc_mode;
1697         return 0;
1698 }
1699
1700 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1701 {
1702         unsigned int val;
1703
1704         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1705 #ifdef CONFIG_SPE
1706                 if (cpu_has_feature(CPU_FTR_SPE)) {
1707                         /*
1708                          * When the sticky exception bits are set
1709                          * directly by userspace, it must call prctl
1710                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1711                          * in the existing prctl settings) or
1712                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1713                          * the bits being set).  <fenv.h> functions
1714                          * saving and restoring the whole
1715                          * floating-point environment need to do so
1716                          * anyway to restore the prctl settings from
1717                          * the saved environment.
1718                          */
1719                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1720                         val = tsk->thread.fpexc_mode;
1721                 } else
1722                         return -EINVAL;
1723 #else
1724                 return -EINVAL;
1725 #endif
1726         else
1727                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1728         return put_user(val, (unsigned int __user *) adr);
1729 }
1730
1731 int set_endian(struct task_struct *tsk, unsigned int val)
1732 {
1733         struct pt_regs *regs = tsk->thread.regs;
1734
1735         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1736             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1737                 return -EINVAL;
1738
1739         if (regs == NULL)
1740                 return -EINVAL;
1741
1742         if (val == PR_ENDIAN_BIG)
1743                 regs->msr &= ~MSR_LE;
1744         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1745                 regs->msr |= MSR_LE;
1746         else
1747                 return -EINVAL;
1748
1749         return 0;
1750 }
1751
1752 int get_endian(struct task_struct *tsk, unsigned long adr)
1753 {
1754         struct pt_regs *regs = tsk->thread.regs;
1755         unsigned int val;
1756
1757         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1758             !cpu_has_feature(CPU_FTR_REAL_LE))
1759                 return -EINVAL;
1760
1761         if (regs == NULL)
1762                 return -EINVAL;
1763
1764         if (regs->msr & MSR_LE) {
1765                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1766                         val = PR_ENDIAN_LITTLE;
1767                 else
1768                         val = PR_ENDIAN_PPC_LITTLE;
1769         } else
1770                 val = PR_ENDIAN_BIG;
1771
1772         return put_user(val, (unsigned int __user *)adr);
1773 }
1774
1775 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1776 {
1777         tsk->thread.align_ctl = val;
1778         return 0;
1779 }
1780
1781 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1782 {
1783         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1784 }
1785
1786 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1787                                   unsigned long nbytes)
1788 {
1789         unsigned long stack_page;
1790         unsigned long cpu = task_cpu(p);
1791
1792         /*
1793          * Avoid crashing if the stack has overflowed and corrupted
1794          * task_cpu(p), which is in the thread_info struct.
1795          */
1796         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1797                 stack_page = (unsigned long) hardirq_ctx[cpu];
1798                 if (sp >= stack_page + sizeof(struct thread_struct)
1799                     && sp <= stack_page + THREAD_SIZE - nbytes)
1800                         return 1;
1801
1802                 stack_page = (unsigned long) softirq_ctx[cpu];
1803                 if (sp >= stack_page + sizeof(struct thread_struct)
1804                     && sp <= stack_page + THREAD_SIZE - nbytes)
1805                         return 1;
1806         }
1807         return 0;
1808 }
1809
1810 int validate_sp(unsigned long sp, struct task_struct *p,
1811                        unsigned long nbytes)
1812 {
1813         unsigned long stack_page = (unsigned long)task_stack_page(p);
1814
1815         if (sp >= stack_page + sizeof(struct thread_struct)
1816             && sp <= stack_page + THREAD_SIZE - nbytes)
1817                 return 1;
1818
1819         return valid_irq_stack(sp, p, nbytes);
1820 }
1821
1822 EXPORT_SYMBOL(validate_sp);
1823
1824 unsigned long get_wchan(struct task_struct *p)
1825 {
1826         unsigned long ip, sp;
1827         int count = 0;
1828
1829         if (!p || p == current || p->state == TASK_RUNNING)
1830                 return 0;
1831
1832         sp = p->thread.ksp;
1833         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1834                 return 0;
1835
1836         do {
1837                 sp = *(unsigned long *)sp;
1838                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1839                         return 0;
1840                 if (count > 0) {
1841                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1842                         if (!in_sched_functions(ip))
1843                                 return ip;
1844                 }
1845         } while (count++ < 16);
1846         return 0;
1847 }
1848
1849 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1850
1851 void show_stack(struct task_struct *tsk, unsigned long *stack)
1852 {
1853         unsigned long sp, ip, lr, newsp;
1854         int count = 0;
1855         int firstframe = 1;
1856 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1857         int curr_frame = current->curr_ret_stack;
1858         extern void return_to_handler(void);
1859         unsigned long rth = (unsigned long)return_to_handler;
1860 #endif
1861
1862         sp = (unsigned long) stack;
1863         if (tsk == NULL)
1864                 tsk = current;
1865         if (sp == 0) {
1866                 if (tsk == current)
1867                         sp = current_stack_pointer();
1868                 else
1869                         sp = tsk->thread.ksp;
1870         }
1871
1872         lr = 0;
1873         printk("Call Trace:\n");
1874         do {
1875                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1876                         return;
1877
1878                 stack = (unsigned long *) sp;
1879                 newsp = stack[0];
1880                 ip = stack[STACK_FRAME_LR_SAVE];
1881                 if (!firstframe || ip != lr) {
1882                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1883 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1884                         if ((ip == rth) && curr_frame >= 0) {
1885                                 printk(" (%pS)",
1886                                        (void *)current->ret_stack[curr_frame].ret);
1887                                 curr_frame--;
1888                         }
1889 #endif
1890                         if (firstframe)
1891                                 printk(" (unreliable)");
1892                         printk("\n");
1893                 }
1894                 firstframe = 0;
1895
1896                 /*
1897                  * See if this is an exception frame.
1898                  * We look for the "regshere" marker in the current frame.
1899                  */
1900                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1901                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1902                         struct pt_regs *regs = (struct pt_regs *)
1903                                 (sp + STACK_FRAME_OVERHEAD);
1904                         lr = regs->link;
1905                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1906                                regs->trap, (void *)regs->nip, (void *)lr);
1907                         firstframe = 1;
1908                 }
1909
1910                 sp = newsp;
1911         } while (count++ < kstack_depth_to_print);
1912 }
1913
1914 #ifdef CONFIG_PPC64
1915 /* Called with hard IRQs off */
1916 void notrace __ppc64_runlatch_on(void)
1917 {
1918         struct thread_info *ti = current_thread_info();
1919         unsigned long ctrl;
1920
1921         ctrl = mfspr(SPRN_CTRLF);
1922         ctrl |= CTRL_RUNLATCH;
1923         mtspr(SPRN_CTRLT, ctrl);
1924
1925         ti->local_flags |= _TLF_RUNLATCH;
1926 }
1927
1928 /* Called with hard IRQs off */
1929 void notrace __ppc64_runlatch_off(void)
1930 {
1931         struct thread_info *ti = current_thread_info();
1932         unsigned long ctrl;
1933
1934         ti->local_flags &= ~_TLF_RUNLATCH;
1935
1936         ctrl = mfspr(SPRN_CTRLF);
1937         ctrl &= ~CTRL_RUNLATCH;
1938         mtspr(SPRN_CTRLT, ctrl);
1939 }
1940 #endif /* CONFIG_PPC64 */
1941
1942 unsigned long arch_align_stack(unsigned long sp)
1943 {
1944         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1945                 sp -= get_random_int() & ~PAGE_MASK;
1946         return sp & ~0xf;
1947 }
1948
1949 static inline unsigned long brk_rnd(void)
1950 {
1951         unsigned long rnd = 0;
1952
1953         /* 8MB for 32bit, 1GB for 64bit */
1954         if (is_32bit_task())
1955                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1956         else
1957                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1958
1959         return rnd << PAGE_SHIFT;
1960 }
1961
1962 unsigned long arch_randomize_brk(struct mm_struct *mm)
1963 {
1964         unsigned long base = mm->brk;
1965         unsigned long ret;
1966
1967 #ifdef CONFIG_PPC_STD_MMU_64
1968         /*
1969          * If we are using 1TB segments and we are allowed to randomise
1970          * the heap, we can put it above 1TB so it is backed by a 1TB
1971          * segment. Otherwise the heap will be in the bottom 1TB
1972          * which always uses 256MB segments and this may result in a
1973          * performance penalty. We don't need to worry about radix. For
1974          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1975          */
1976         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1977                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1978 #endif
1979
1980         ret = PAGE_ALIGN(base + brk_rnd());
1981
1982         if (ret < mm->brk)
1983                 return mm->brk;
1984
1985         return ret;
1986 }
1987