arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62
  63 #include <linux/kprobes.h>
  64 #include <linux/kdebug.h>
  65
  66 /* Transactional Memory debug */
  67 #ifdef TM_DEBUG_SW
  68 #define TM_DEBUG(x...) printk(KERN_INFO x)
  69 #else
  70 #define TM_DEBUG(x...) do { } while(0)
  71 #endif
  72
  73 extern unsigned long _get_SP(void);
  74
  75 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  76 static void check_if_tm_restore_required(struct task_struct *tsk)
  77 {
  78         /*
  79          * If we are saving the current thread's registers, and the
  80          * thread is in a transactional state, set the TIF_RESTORE_TM
  81          * bit so that we know to restore the registers before
  82          * returning to userspace.
  83          */
  84         if (tsk == current && tsk->thread.regs &&
  85             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  86             !test_thread_flag(TIF_RESTORE_TM)) {
  87                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  88                 set_thread_flag(TIF_RESTORE_TM);
  89         }
  90 }
  91 #else
  92 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
  93 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  94
  95 bool strict_msr_control;
  96 EXPORT_SYMBOL(strict_msr_control);
  97
  98 static int __init enable_strict_msr_control(char *str)
  99 {
 100         strict_msr_control = true;
 101         pr_info("Enabling strict facility control\n");
 102
 103         return 0;
 104 }
 105 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 106
 107 void msr_check_and_set(unsigned long bits)
 108 {
 109         unsigned long oldmsr = mfmsr();
 110         unsigned long newmsr;
 111
 112         newmsr = oldmsr | bits;
 113
 114 #ifdef CONFIG_VSX
 115         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 116                 newmsr |= MSR_VSX;
 117 #endif
 118
 119         if (oldmsr != newmsr)
 120                 mtmsr_isync(newmsr);
 121 }
 122
 123 void __msr_check_and_clear(unsigned long bits)
 124 {
 125         unsigned long oldmsr = mfmsr();
 126         unsigned long newmsr;
 127
 128         newmsr = oldmsr & ~bits;
 129
 130 #ifdef CONFIG_VSX
 131         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 132                 newmsr &= ~MSR_VSX;
 133 #endif
 134
 135         if (oldmsr != newmsr)
 136                 mtmsr_isync(newmsr);
 137 }
 138 EXPORT_SYMBOL(__msr_check_and_clear);
 139
 140 #ifdef CONFIG_PPC_FPU
 141 void __giveup_fpu(struct task_struct *tsk)
 142 {
 143         unsigned long msr;
 144
 145         save_fpu(tsk);
 146         msr = tsk->thread.regs->msr;
 147         msr &= ~MSR_FP;
 148 #ifdef CONFIG_VSX
 149         if (cpu_has_feature(CPU_FTR_VSX))
 150                 msr &= ~MSR_VSX;
 151 #endif
 152         tsk->thread.regs->msr = msr;
 153 }
 154
 155 void giveup_fpu(struct task_struct *tsk)
 156 {
 157         check_if_tm_restore_required(tsk);
 158
 159         msr_check_and_set(MSR_FP);
 160         __giveup_fpu(tsk);
 161         msr_check_and_clear(MSR_FP);
 162 }
 163 EXPORT_SYMBOL(giveup_fpu);
 164
 165 /*
 166  * Make sure the floating-point register state in the
 167  * the thread_struct is up to date for task tsk.
 168  */
 169 void flush_fp_to_thread(struct task_struct *tsk)
 170 {
 171         if (tsk->thread.regs) {
 172                 /*
 173                  * We need to disable preemption here because if we didn't,
 174                  * another process could get scheduled after the regs->msr
 175                  * test but before we have finished saving the FP registers
 176                  * to the thread_struct.  That process could take over the
 177                  * FPU, and then when we get scheduled again we would store
 178                  * bogus values for the remaining FP registers.
 179                  */
 180                 preempt_disable();
 181                 if (tsk->thread.regs->msr & MSR_FP) {
 182                         /*
 183                          * This should only ever be called for current or
 184                          * for a stopped child process.  Since we save away
 185                          * the FP register state on context switch,
 186                          * there is something wrong if a stopped child appears
 187                          * to still have its FP state in the CPU registers.
 188                          */
 189                         BUG_ON(tsk != current);
 190                         giveup_fpu(tsk);
 191                 }
 192                 preempt_enable();
 193         }
 194 }
 195 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 196
 197 void enable_kernel_fp(void)
 198 {
 199         WARN_ON(preemptible());
 200
 201         msr_check_and_set(MSR_FP);
 202
 203         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 204                 check_if_tm_restore_required(current);
 205                 __giveup_fpu(current);
 206         }
 207 }
 208 EXPORT_SYMBOL(enable_kernel_fp);
 209
 210 static int restore_fp(struct task_struct *tsk) {
 211         if (tsk->thread.load_fp) {
 212                 load_fp_state(&current->thread.fp_state);
 213                 current->thread.load_fp++;
 214                 return 1;
 215         }
 216         return 0;
 217 }
 218 #else
 219 static int restore_fp(struct task_struct *tsk) { return 0; }
 220 #endif /* CONFIG_PPC_FPU */
 221
 222 #ifdef CONFIG_ALTIVEC
 223 #define loadvec(thr) ((thr).load_vec)
 224
 225 static void __giveup_altivec(struct task_struct *tsk)
 226 {
 227         unsigned long msr;
 228
 229         save_altivec(tsk);
 230         msr = tsk->thread.regs->msr;
 231         msr &= ~MSR_VEC;
 232 #ifdef CONFIG_VSX
 233         if (cpu_has_feature(CPU_FTR_VSX))
 234                 msr &= ~MSR_VSX;
 235 #endif
 236         tsk->thread.regs->msr = msr;
 237 }
 238
 239 void giveup_altivec(struct task_struct *tsk)
 240 {
 241         check_if_tm_restore_required(tsk);
 242
 243         msr_check_and_set(MSR_VEC);
 244         __giveup_altivec(tsk);
 245         msr_check_and_clear(MSR_VEC);
 246 }
 247 EXPORT_SYMBOL(giveup_altivec);
 248
 249 void enable_kernel_altivec(void)
 250 {
 251         WARN_ON(preemptible());
 252
 253         msr_check_and_set(MSR_VEC);
 254
 255         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 256                 check_if_tm_restore_required(current);
 257                 __giveup_altivec(current);
 258         }
 259 }
 260 EXPORT_SYMBOL(enable_kernel_altivec);
 261
 262 /*
 263  * Make sure the VMX/Altivec register state in the
 264  * the thread_struct is up to date for task tsk.
 265  */
 266 void flush_altivec_to_thread(struct task_struct *tsk)
 267 {
 268         if (tsk->thread.regs) {
 269                 preempt_disable();
 270                 if (tsk->thread.regs->msr & MSR_VEC) {
 271                         BUG_ON(tsk != current);
 272                         giveup_altivec(tsk);
 273                 }
 274                 preempt_enable();
 275         }
 276 }
 277 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 278
 279 static int restore_altivec(struct task_struct *tsk)
 280 {
 281         if (cpu_has_feature(CPU_FTR_ALTIVEC) && tsk->thread.load_vec) {
 282                 load_vr_state(&tsk->thread.vr_state);
 283                 tsk->thread.used_vr = 1;
 284                 tsk->thread.load_vec++;
 285
 286                 return 1;
 287         }
 288         return 0;
 289 }
 290 #else
 291 #define loadvec(thr) 0
 292 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 293 #endif /* CONFIG_ALTIVEC */
 294
 295 #ifdef CONFIG_VSX
 296 static void __giveup_vsx(struct task_struct *tsk)
 297 {
 298         if (tsk->thread.regs->msr & MSR_FP)
 299                 __giveup_fpu(tsk);
 300         if (tsk->thread.regs->msr & MSR_VEC)
 301                 __giveup_altivec(tsk);
 302         tsk->thread.regs->msr &= ~MSR_VSX;
 303 }
 304
 305 static void giveup_vsx(struct task_struct *tsk)
 306 {
 307         check_if_tm_restore_required(tsk);
 308
 309         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 310         __giveup_vsx(tsk);
 311         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 312 }
 313
 314 static void save_vsx(struct task_struct *tsk)
 315 {
 316         if (tsk->thread.regs->msr & MSR_FP)
 317                 save_fpu(tsk);
 318         if (tsk->thread.regs->msr & MSR_VEC)
 319                 save_altivec(tsk);
 320 }
 321
 322 void enable_kernel_vsx(void)
 323 {
 324         WARN_ON(preemptible());
 325
 326         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 327
 328         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 329                 check_if_tm_restore_required(current);
 330                 if (current->thread.regs->msr & MSR_FP)
 331                         __giveup_fpu(current);
 332                 if (current->thread.regs->msr & MSR_VEC)
 333                         __giveup_altivec(current);
 334                 __giveup_vsx(current);
 335         }
 336 }
 337 EXPORT_SYMBOL(enable_kernel_vsx);
 338
 339 void flush_vsx_to_thread(struct task_struct *tsk)
 340 {
 341         if (tsk->thread.regs) {
 342                 preempt_disable();
 343                 if (tsk->thread.regs->msr & MSR_VSX) {
 344                         BUG_ON(tsk != current);
 345                         giveup_vsx(tsk);
 346                 }
 347                 preempt_enable();
 348         }
 349 }
 350 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 351
 352 static int restore_vsx(struct task_struct *tsk)
 353 {
 354         if (cpu_has_feature(CPU_FTR_VSX)) {
 355                 tsk->thread.used_vsr = 1;
 356                 return 1;
 357         }
 358
 359         return 0;
 360 }
 361 #else
 362 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 363 static inline void save_vsx(struct task_struct *tsk) { }
 364 #endif /* CONFIG_VSX */
 365
 366 #ifdef CONFIG_SPE
 367 void giveup_spe(struct task_struct *tsk)
 368 {
 369         check_if_tm_restore_required(tsk);
 370
 371         msr_check_and_set(MSR_SPE);
 372         __giveup_spe(tsk);
 373         msr_check_and_clear(MSR_SPE);
 374 }
 375 EXPORT_SYMBOL(giveup_spe);
 376
 377 void enable_kernel_spe(void)
 378 {
 379         WARN_ON(preemptible());
 380
 381         msr_check_and_set(MSR_SPE);
 382
 383         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 384                 check_if_tm_restore_required(current);
 385                 __giveup_spe(current);
 386         }
 387 }
 388 EXPORT_SYMBOL(enable_kernel_spe);
 389
 390 void flush_spe_to_thread(struct task_struct *tsk)
 391 {
 392         if (tsk->thread.regs) {
 393                 preempt_disable();
 394                 if (tsk->thread.regs->msr & MSR_SPE) {
 395                         BUG_ON(tsk != current);
 396                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 397                         giveup_spe(tsk);
 398                 }
 399                 preempt_enable();
 400         }
 401 }
 402 #endif /* CONFIG_SPE */
 403
 404 static unsigned long msr_all_available;
 405
 406 static int __init init_msr_all_available(void)
 407 {
 408 #ifdef CONFIG_PPC_FPU
 409         msr_all_available |= MSR_FP;
 410 #endif
 411 #ifdef CONFIG_ALTIVEC
 412         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 413                 msr_all_available |= MSR_VEC;
 414 #endif
 415 #ifdef CONFIG_VSX
 416         if (cpu_has_feature(CPU_FTR_VSX))
 417                 msr_all_available |= MSR_VSX;
 418 #endif
 419 #ifdef CONFIG_SPE
 420         if (cpu_has_feature(CPU_FTR_SPE))
 421                 msr_all_available |= MSR_SPE;
 422 #endif
 423
 424         return 0;
 425 }
 426 early_initcall(init_msr_all_available);
 427
 428 void giveup_all(struct task_struct *tsk)
 429 {
 430         unsigned long usermsr;
 431
 432         if (!tsk->thread.regs)
 433                 return;
 434
 435         usermsr = tsk->thread.regs->msr;
 436
 437         if ((usermsr & msr_all_available) == 0)
 438                 return;
 439
 440         msr_check_and_set(msr_all_available);
 441
 442 #ifdef CONFIG_PPC_FPU
 443         if (usermsr & MSR_FP)
 444                 __giveup_fpu(tsk);
 445 #endif
 446 #ifdef CONFIG_ALTIVEC
 447         if (usermsr & MSR_VEC)
 448                 __giveup_altivec(tsk);
 449 #endif
 450 #ifdef CONFIG_VSX
 451         if (usermsr & MSR_VSX)
 452                 __giveup_vsx(tsk);
 453 #endif
 454 #ifdef CONFIG_SPE
 455         if (usermsr & MSR_SPE)
 456                 __giveup_spe(tsk);
 457 #endif
 458
 459         msr_check_and_clear(msr_all_available);
 460 }
 461 EXPORT_SYMBOL(giveup_all);
 462
 463 void restore_math(struct pt_regs *regs)
 464 {
 465         unsigned long msr;
 466
 467         if (!current->thread.load_fp && !loadvec(current->thread))
 468                 return;
 469
 470         msr = regs->msr;
 471         msr_check_and_set(msr_all_available);
 472
 473         /*
 474          * Only reload if the bit is not set in the user MSR, the bit BEING set
 475          * indicates that the registers are hot
 476          */
 477         if ((!(msr & MSR_FP)) && restore_fp(current))
 478                 msr |= MSR_FP | current->thread.fpexc_mode;
 479
 480         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 481                 msr |= MSR_VEC;
 482
 483         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 484                         restore_vsx(current)) {
 485                 msr |= MSR_VSX;
 486         }
 487
 488         msr_check_and_clear(msr_all_available);
 489
 490         regs->msr = msr;
 491 }
 492
 493 void save_all(struct task_struct *tsk)
 494 {
 495         unsigned long usermsr;
 496
 497         if (!tsk->thread.regs)
 498                 return;
 499
 500         usermsr = tsk->thread.regs->msr;
 501
 502         if ((usermsr & msr_all_available) == 0)
 503                 return;
 504
 505         msr_check_and_set(msr_all_available);
 506
 507         /*
 508          * Saving the way the register space is in hardware, save_vsx boils
 509          * down to a save_fpu() and save_altivec()
 510          */
 511         if (usermsr & MSR_VSX) {
 512                 save_vsx(tsk);
 513         } else {
 514                 if (usermsr & MSR_FP)
 515                         save_fpu(tsk);
 516
 517                 if (usermsr & MSR_VEC)
 518                         save_altivec(tsk);
 519         }
 520
 521         if (usermsr & MSR_SPE)
 522                 __giveup_spe(tsk);
 523
 524         msr_check_and_clear(msr_all_available);
 525 }
 526
 527 void flush_all_to_thread(struct task_struct *tsk)
 528 {
 529         if (tsk->thread.regs) {
 530                 preempt_disable();
 531                 BUG_ON(tsk != current);
 532                 save_all(tsk);
 533
 534 #ifdef CONFIG_SPE
 535                 if (tsk->thread.regs->msr & MSR_SPE)
 536                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 537 #endif
 538
 539                 preempt_enable();
 540         }
 541 }
 542 EXPORT_SYMBOL(flush_all_to_thread);
 543
 544 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 545 void do_send_trap(struct pt_regs *regs, unsigned long address,
 546                   unsigned long error_code, int signal_code, int breakpt)
 547 {
 548         siginfo_t info;
 549
 550         current->thread.trap_nr = signal_code;
 551         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 552                         11, SIGSEGV) == NOTIFY_STOP)
 553                 return;
 554
 555         /* Deliver the signal to userspace */
 556         info.si_signo = SIGTRAP;
 557         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 558         info.si_code = signal_code;
 559         info.si_addr = (void __user *)address;
 560         force_sig_info(SIGTRAP, &info, current);
 561 }
 562 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 563 void do_break (struct pt_regs *regs, unsigned long address,
 564                     unsigned long error_code)
 565 {
 566         siginfo_t info;
 567
 568         current->thread.trap_nr = TRAP_HWBKPT;
 569         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 570                         11, SIGSEGV) == NOTIFY_STOP)
 571                 return;
 572
 573         if (debugger_break_match(regs))
 574                 return;
 575
 576         /* Clear the breakpoint */
 577         hw_breakpoint_disable();
 578
 579         /* Deliver the signal to userspace */
 580         info.si_signo = SIGTRAP;
 581         info.si_errno = 0;
 582         info.si_code = TRAP_HWBKPT;
 583         info.si_addr = (void __user *)address;
 584         force_sig_info(SIGTRAP, &info, current);
 585 }
 586 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 587
 588 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 589
 590 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 591 /*
 592  * Set the debug registers back to their default "safe" values.
 593  */
 594 static void set_debug_reg_defaults(struct thread_struct *thread)
 595 {
 596         thread->debug.iac1 = thread->debug.iac2 = 0;
 597 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 598         thread->debug.iac3 = thread->debug.iac4 = 0;
 599 #endif
 600         thread->debug.dac1 = thread->debug.dac2 = 0;
 601 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 602         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 603 #endif
 604         thread->debug.dbcr0 = 0;
 605 #ifdef CONFIG_BOOKE
 606         /*
 607          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 608          */
 609         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 610                         DBCR1_IAC3US | DBCR1_IAC4US;
 611         /*
 612          * Force Data Address Compare User/Supervisor bits to be User-only
 613          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 614          */
 615         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 616 #else
 617         thread->debug.dbcr1 = 0;
 618 #endif
 619 }
 620
 621 static void prime_debug_regs(struct debug_reg *debug)
 622 {
 623         /*
 624          * We could have inherited MSR_DE from userspace, since
 625          * it doesn't get cleared on exception entry.  Make sure
 626          * MSR_DE is clear before we enable any debug events.
 627          */
 628         mtmsr(mfmsr() & ~MSR_DE);
 629
 630         mtspr(SPRN_IAC1, debug->iac1);
 631         mtspr(SPRN_IAC2, debug->iac2);
 632 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 633         mtspr(SPRN_IAC3, debug->iac3);
 634         mtspr(SPRN_IAC4, debug->iac4);
 635 #endif
 636         mtspr(SPRN_DAC1, debug->dac1);
 637         mtspr(SPRN_DAC2, debug->dac2);
 638 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 639         mtspr(SPRN_DVC1, debug->dvc1);
 640         mtspr(SPRN_DVC2, debug->dvc2);
 641 #endif
 642         mtspr(SPRN_DBCR0, debug->dbcr0);
 643         mtspr(SPRN_DBCR1, debug->dbcr1);
 644 #ifdef CONFIG_BOOKE
 645         mtspr(SPRN_DBCR2, debug->dbcr2);
 646 #endif
 647 }
 648 /*
 649  * Unless neither the old or new thread are making use of the
 650  * debug registers, set the debug registers from the values
 651  * stored in the new thread.
 652  */
 653 void switch_booke_debug_regs(struct debug_reg *new_debug)
 654 {
 655         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 656                 || (new_debug->dbcr0 & DBCR0_IDM))
 657                         prime_debug_regs(new_debug);
 658 }
 659 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 660 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 661 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 662 static void set_debug_reg_defaults(struct thread_struct *thread)
 663 {
 664         thread->hw_brk.address = 0;
 665         thread->hw_brk.type = 0;
 666         set_breakpoint(&thread->hw_brk);
 667 }
 668 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 669 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 670
 671 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 672 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 673 {
 674         mtspr(SPRN_DAC1, dabr);
 675 #ifdef CONFIG_PPC_47x
 676         isync();
 677 #endif
 678         return 0;
 679 }
 680 #elif defined(CONFIG_PPC_BOOK3S)
 681 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 682 {
 683         mtspr(SPRN_DABR, dabr);
 684         if (cpu_has_feature(CPU_FTR_DABRX))
 685                 mtspr(SPRN_DABRX, dabrx);
 686         return 0;
 687 }
 688 #else
 689 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 690 {
 691         return -EINVAL;
 692 }
 693 #endif
 694
 695 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 696 {
 697         unsigned long dabr, dabrx;
 698
 699         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 700         dabrx = ((brk->type >> 3) & 0x7);
 701
 702         if (ppc_md.set_dabr)
 703                 return ppc_md.set_dabr(dabr, dabrx);
 704
 705         return __set_dabr(dabr, dabrx);
 706 }
 707
 708 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 709 {
 710         unsigned long dawr, dawrx, mrd;
 711
 712         dawr = brk->address;
 713
 714         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 715                                    << (63 - 58); //* read/write bits */
 716         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 717                                    << (63 - 59); //* translate */
 718         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 719                                    >> 3; //* PRIM bits */
 720         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 721            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 722            0b111111=64DW.
 723            brk->len is in bytes.
 724            This aligns up to double word size, shifts and does the bias.
 725         */
 726         mrd = ((brk->len + 7) >> 3) - 1;
 727         dawrx |= (mrd & 0x3f) << (63 - 53);
 728
 729         if (ppc_md.set_dawr)
 730                 return ppc_md.set_dawr(dawr, dawrx);
 731         mtspr(SPRN_DAWR, dawr);
 732         mtspr(SPRN_DAWRX, dawrx);
 733         return 0;
 734 }
 735
 736 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 737 {
 738         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 739
 740         if (cpu_has_feature(CPU_FTR_DAWR))
 741                 set_dawr(brk);
 742         else
 743                 set_dabr(brk);
 744 }
 745
 746 void set_breakpoint(struct arch_hw_breakpoint *brk)
 747 {
 748         preempt_disable();
 749         __set_breakpoint(brk);
 750         preempt_enable();
 751 }
 752
 753 #ifdef CONFIG_PPC64
 754 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 755 #endif
 756
 757 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 758                               struct arch_hw_breakpoint *b)
 759 {
 760         if (a->address != b->address)
 761                 return false;
 762         if (a->type != b->type)
 763                 return false;
 764         if (a->len != b->len)
 765                 return false;
 766         return true;
 767 }
 768
 769 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 770 static void tm_reclaim_thread(struct thread_struct *thr,
 771                               struct thread_info *ti, uint8_t cause)
 772 {
 773         unsigned long msr_diff = 0;
 774
 775         /*
 776          * If FP/VSX registers have been already saved to the
 777          * thread_struct, move them to the transact_fp array.
 778          * We clear the TIF_RESTORE_TM bit since after the reclaim
 779          * the thread will no longer be transactional.
 780          */
 781         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 782                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 783                 if (msr_diff & MSR_FP)
 784                         memcpy(&thr->transact_fp, &thr->fp_state,
 785                                sizeof(struct thread_fp_state));
 786                 if (msr_diff & MSR_VEC)
 787                         memcpy(&thr->transact_vr, &thr->vr_state,
 788                                sizeof(struct thread_vr_state));
 789                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 790                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 791         }
 792
 793         /*
 794          * Use the current MSR TM suspended bit to track if we have
 795          * checkpointed state outstanding.
 796          * On signal delivery, we'd normally reclaim the checkpointed
 797          * state to obtain stack pointer (see:get_tm_stackpointer()).
 798          * This will then directly return to userspace without going
 799          * through __switch_to(). However, if the stack frame is bad,
 800          * we need to exit this thread which calls __switch_to() which
 801          * will again attempt to reclaim the already saved tm state.
 802          * Hence we need to check that we've not already reclaimed
 803          * this state.
 804          * We do this using the current MSR, rather tracking it in
 805          * some specific thread_struct bit, as it has the additional
 806          * benefit of checking for a potential TM bad thing exception.
 807          */
 808         if (!MSR_TM_SUSPENDED(mfmsr()))
 809                 return;
 810
 811         tm_reclaim(thr, thr->regs->msr, cause);
 812
 813         /* Having done the reclaim, we now have the checkpointed
 814          * FP/VSX values in the registers.  These might be valid
 815          * even if we have previously called enable_kernel_fp() or
 816          * flush_fp_to_thread(), so update thr->regs->msr to
 817          * indicate their current validity.
 818          */
 819         thr->regs->msr |= msr_diff;
 820 }
 821
 822 void tm_reclaim_current(uint8_t cause)
 823 {
 824         tm_enable();
 825         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 826 }
 827
 828 static inline void tm_reclaim_task(struct task_struct *tsk)
 829 {
 830         /* We have to work out if we're switching from/to a task that's in the
 831          * middle of a transaction.
 832          *
 833          * In switching we need to maintain a 2nd register state as
 834          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 835          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 836          * (current) FPRs into oldtask->thread.transact_fpr[].
 837          *
 838          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 839          */
 840         struct thread_struct *thr = &tsk->thread;
 841
 842         if (!thr->regs)
 843                 return;
 844
 845         if (!MSR_TM_ACTIVE(thr->regs->msr))
 846                 goto out_and_saveregs;
 847
 848         /* Stash the original thread MSR, as giveup_fpu et al will
 849          * modify it.  We hold onto it to see whether the task used
 850          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 851          * ckpt_regs.msr is already set.
 852          */
 853         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 854                 thr->ckpt_regs.msr = thr->regs->msr;
 855
 856         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 857                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 858                  tsk->pid, thr->regs->nip,
 859                  thr->regs->ccr, thr->regs->msr,
 860                  thr->regs->trap);
 861
 862         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 863
 864         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 865                  tsk->pid);
 866
 867 out_and_saveregs:
 868         /* Always save the regs here, even if a transaction's not active.
 869          * This context-switches a thread's TM info SPRs.  We do it here to
 870          * be consistent with the restore path (in recheckpoint) which
 871          * cannot happen later in _switch().
 872          */
 873         tm_save_sprs(thr);
 874 }
 875
 876 extern void __tm_recheckpoint(struct thread_struct *thread,
 877                               unsigned long orig_msr);
 878
 879 void tm_recheckpoint(struct thread_struct *thread,
 880                      unsigned long orig_msr)
 881 {
 882         unsigned long flags;
 883
 884         /* We really can't be interrupted here as the TEXASR registers can't
 885          * change and later in the trecheckpoint code, we have a userspace R1.
 886          * So let's hard disable over this region.
 887          */
 888         local_irq_save(flags);
 889         hard_irq_disable();
 890
 891         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 892          * before the trecheckpoint and no explosion occurs.
 893          */
 894         tm_restore_sprs(thread);
 895
 896         __tm_recheckpoint(thread, orig_msr);
 897
 898         local_irq_restore(flags);
 899 }
 900
 901 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 902 {
 903         unsigned long msr;
 904
 905         if (!cpu_has_feature(CPU_FTR_TM))
 906                 return;
 907
 908         /* Recheckpoint the registers of the thread we're about to switch to.
 909          *
 910          * If the task was using FP, we non-lazily reload both the original and
 911          * the speculative FP register states.  This is because the kernel
 912          * doesn't see if/when a TM rollback occurs, so if we take an FP
 913          * unavoidable later, we are unable to determine which set of FP regs
 914          * need to be restored.
 915          */
 916         if (!new->thread.regs)
 917                 return;
 918
 919         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 920                 tm_restore_sprs(&new->thread);
 921                 return;
 922         }
 923         msr = new->thread.ckpt_regs.msr;
 924         /* Recheckpoint to restore original checkpointed register state. */
 925         TM_DEBUG("*** tm_recheckpoint of pid %d "
 926                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 927                  new->pid, new->thread.regs->msr, msr);
 928
 929         /* This loads the checkpointed FP/VEC state, if used */
 930         tm_recheckpoint(&new->thread, msr);
 931
 932         /* This loads the speculative FP/VEC state, if used */
 933         if (msr & MSR_FP) {
 934                 do_load_up_transact_fpu(&new->thread);
 935                 new->thread.regs->msr |=
 936                         (MSR_FP | new->thread.fpexc_mode);
 937         }
 938 #ifdef CONFIG_ALTIVEC
 939         if (msr & MSR_VEC) {
 940                 do_load_up_transact_altivec(&new->thread);
 941                 new->thread.regs->msr |= MSR_VEC;
 942         }
 943 #endif
 944         /* We may as well turn on VSX too since all the state is restored now */
 945         if (msr & MSR_VSX)
 946                 new->thread.regs->msr |= MSR_VSX;
 947
 948         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 949                  "(kernel msr 0x%lx)\n",
 950                  new->pid, mfmsr());
 951 }
 952
 953 static inline void __switch_to_tm(struct task_struct *prev)
 954 {
 955         if (cpu_has_feature(CPU_FTR_TM)) {
 956                 tm_enable();
 957                 tm_reclaim_task(prev);
 958         }
 959 }
 960
 961 /*
 962  * This is called if we are on the way out to userspace and the
 963  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 964  * FP and/or vector state and does so if necessary.
 965  * If userspace is inside a transaction (whether active or
 966  * suspended) and FP/VMX/VSX instructions have ever been enabled
 967  * inside that transaction, then we have to keep them enabled
 968  * and keep the FP/VMX/VSX state loaded while ever the transaction
 969  * continues.  The reason is that if we didn't, and subsequently
 970  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 971  * we don't know whether it's the same transaction, and thus we
 972  * don't know which of the checkpointed state and the transactional
 973  * state to use.
 974  */
 975 void restore_tm_state(struct pt_regs *regs)
 976 {
 977         unsigned long msr_diff;
 978
 979         clear_thread_flag(TIF_RESTORE_TM);
 980         if (!MSR_TM_ACTIVE(regs->msr))
 981                 return;
 982
 983         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 984         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 985
 986         restore_math(regs);
 987
 988         regs->msr |= msr_diff;
 989 }
 990
 991 #else
 992 #define tm_recheckpoint_new_task(new)
 993 #define __switch_to_tm(prev)
 994 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 995
 996 static inline void save_sprs(struct thread_struct *t)
 997 {
 998 #ifdef CONFIG_ALTIVEC
 999         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1000                 t->vrsave = mfspr(SPRN_VRSAVE);
1001 #endif
1002 #ifdef CONFIG_PPC_BOOK3S_64
1003         if (cpu_has_feature(CPU_FTR_DSCR))
1004                 t->dscr = mfspr(SPRN_DSCR);
1005
1006         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1007                 t->bescr = mfspr(SPRN_BESCR);
1008                 t->ebbhr = mfspr(SPRN_EBBHR);
1009                 t->ebbrr = mfspr(SPRN_EBBRR);
1010
1011                 t->fscr = mfspr(SPRN_FSCR);
1012
1013                 /*
1014                  * Note that the TAR is not available for use in the kernel.
1015                  * (To provide this, the TAR should be backed up/restored on
1016                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1017                  * this should be in pt_regs anyway (for debug).)
1018                  */
1019                 t->tar = mfspr(SPRN_TAR);
1020         }
1021
1022         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1023                 /* Conditionally save Load Monitor registers, if enabled */
1024                 if (t->fscr & FSCR_LM) {
1025                         t->lmrr = mfspr(SPRN_LMRR);
1026                         t->lmser = mfspr(SPRN_LMSER);
1027                 }
1028         }
1029 #endif
1030 }
1031
1032 static inline void restore_sprs(struct thread_struct *old_thread,
1033                                 struct thread_struct *new_thread)
1034 {
1035 #ifdef CONFIG_ALTIVEC
1036         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1037             old_thread->vrsave != new_thread->vrsave)
1038                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1039 #endif
1040 #ifdef CONFIG_PPC_BOOK3S_64
1041         if (cpu_has_feature(CPU_FTR_DSCR)) {
1042                 u64 dscr = get_paca()->dscr_default;
1043                 if (new_thread->dscr_inherit)
1044                         dscr = new_thread->dscr;
1045
1046                 if (old_thread->dscr != dscr)
1047                         mtspr(SPRN_DSCR, dscr);
1048         }
1049
1050         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1051                 if (old_thread->bescr != new_thread->bescr)
1052                         mtspr(SPRN_BESCR, new_thread->bescr);
1053                 if (old_thread->ebbhr != new_thread->ebbhr)
1054                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1055                 if (old_thread->ebbrr != new_thread->ebbrr)
1056                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1057
1058                 if (old_thread->fscr != new_thread->fscr)
1059                         mtspr(SPRN_FSCR, new_thread->fscr);
1060
1061                 if (old_thread->tar != new_thread->tar)
1062                         mtspr(SPRN_TAR, new_thread->tar);
1063         }
1064
1065         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1066                 /* Conditionally restore Load Monitor registers, if enabled */
1067                 if (new_thread->fscr & FSCR_LM) {
1068                         if (old_thread->lmrr != new_thread->lmrr)
1069                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1070                         if (old_thread->lmser != new_thread->lmser)
1071                                 mtspr(SPRN_LMSER, new_thread->lmser);
1072                 }
1073         }
1074 #endif
1075 }
1076
1077 struct task_struct *__switch_to(struct task_struct *prev,
1078         struct task_struct *new)
1079 {
1080         struct thread_struct *new_thread, *old_thread;
1081         struct task_struct *last;
1082 #ifdef CONFIG_PPC_BOOK3S_64
1083         struct ppc64_tlb_batch *batch;
1084 #endif
1085
1086         new_thread = &new->thread;
1087         old_thread = &current->thread;
1088
1089         WARN_ON(!irqs_disabled());
1090
1091 #ifdef CONFIG_PPC64
1092         /*
1093          * Collect processor utilization data per process
1094          */
1095         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1096                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1097                 long unsigned start_tb, current_tb;
1098                 start_tb = old_thread->start_tb;
1099                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1100                 old_thread->accum_tb += (current_tb - start_tb);
1101                 new_thread->start_tb = current_tb;
1102         }
1103 #endif /* CONFIG_PPC64 */
1104
1105 #ifdef CONFIG_PPC_STD_MMU_64
1106         batch = this_cpu_ptr(&ppc64_tlb_batch);
1107         if (batch->active) {
1108                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1109                 if (batch->index)
1110                         __flush_tlb_pending(batch);
1111                 batch->active = 0;
1112         }
1113 #endif /* CONFIG_PPC_STD_MMU_64 */
1114
1115 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1116         switch_booke_debug_regs(&new->thread.debug);
1117 #else
1118 /*
1119  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1120  * schedule DABR
1121  */
1122 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1123         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1124                 __set_breakpoint(&new->thread.hw_brk);
1125 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1126 #endif
1127
1128         /*
1129          * We need to save SPRs before treclaim/trecheckpoint as these will
1130          * change a number of them.
1131          */
1132         save_sprs(&prev->thread);
1133
1134         __switch_to_tm(prev);
1135
1136         /* Save FPU, Altivec, VSX and SPE state */
1137         giveup_all(prev);
1138
1139         /*
1140          * We can't take a PMU exception inside _switch() since there is a
1141          * window where the kernel stack SLB and the kernel stack are out
1142          * of sync. Hard disable here.
1143          */
1144         hard_irq_disable();
1145
1146         tm_recheckpoint_new_task(new);
1147
1148         /*
1149          * Call restore_sprs() before calling _switch(). If we move it after
1150          * _switch() then we miss out on calling it for new tasks. The reason
1151          * for this is we manually create a stack frame for new tasks that
1152          * directly returns through ret_from_fork() or
1153          * ret_from_kernel_thread(). See copy_thread() for details.
1154          */
1155         restore_sprs(old_thread, new_thread);
1156
1157         last = _switch(old_thread, new_thread);
1158
1159 #ifdef CONFIG_PPC_STD_MMU_64
1160         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1161                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1162                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1163                 batch->active = 1;
1164         }
1165
1166         if (current_thread_info()->task->thread.regs)
1167                 restore_math(current_thread_info()->task->thread.regs);
1168 #endif /* CONFIG_PPC_STD_MMU_64 */
1169
1170         return last;
1171 }
1172
1173 static int instructions_to_print = 16;
1174
1175 static void show_instructions(struct pt_regs *regs)
1176 {
1177         int i;
1178         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1179                         sizeof(int));
1180
1181         printk("Instruction dump:");
1182
1183         for (i = 0; i < instructions_to_print; i++) {
1184                 int instr;
1185
1186                 if (!(i % 8))
1187                         printk("\n");
1188
1189 #if !defined(CONFIG_BOOKE)
1190                 /* If executing with the IMMU off, adjust pc rather
1191                  * than print XXXXXXXX.
1192                  */
1193                 if (!(regs->msr & MSR_IR))
1194                         pc = (unsigned long)phys_to_virt(pc);
1195 #endif
1196
1197                 if (!__kernel_text_address(pc) ||
1198                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1199                         printk(KERN_CONT "XXXXXXXX ");
1200                 } else {
1201                         if (regs->nip == pc)
1202                                 printk(KERN_CONT "<%08x> ", instr);
1203                         else
1204                                 printk(KERN_CONT "%08x ", instr);
1205                 }
1206
1207                 pc += sizeof(int);
1208         }
1209
1210         printk("\n");
1211 }
1212
1213 struct regbit {
1214         unsigned long bit;
1215         const char *name;
1216 };
1217
1218 static struct regbit msr_bits[] = {
1219 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1220         {MSR_SF,        "SF"},
1221         {MSR_HV,        "HV"},
1222 #endif
1223         {MSR_VEC,       "VEC"},
1224         {MSR_VSX,       "VSX"},
1225 #ifdef CONFIG_BOOKE
1226         {MSR_CE,        "CE"},
1227 #endif
1228         {MSR_EE,        "EE"},
1229         {MSR_PR,        "PR"},
1230         {MSR_FP,        "FP"},
1231         {MSR_ME,        "ME"},
1232 #ifdef CONFIG_BOOKE
1233         {MSR_DE,        "DE"},
1234 #else
1235         {MSR_SE,        "SE"},
1236         {MSR_BE,        "BE"},
1237 #endif
1238         {MSR_IR,        "IR"},
1239         {MSR_DR,        "DR"},
1240         {MSR_PMM,       "PMM"},
1241 #ifndef CONFIG_BOOKE
1242         {MSR_RI,        "RI"},
1243         {MSR_LE,        "LE"},
1244 #endif
1245         {0,             NULL}
1246 };
1247
1248 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1249 {
1250         const char *s = "";
1251
1252         for (; bits->bit; ++bits)
1253                 if (val & bits->bit) {
1254                         printk("%s%s", s, bits->name);
1255                         s = sep;
1256                 }
1257 }
1258
1259 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1260 static struct regbit msr_tm_bits[] = {
1261         {MSR_TS_T,      "T"},
1262         {MSR_TS_S,      "S"},
1263         {MSR_TM,        "E"},
1264         {0,             NULL}
1265 };
1266
1267 static void print_tm_bits(unsigned long val)
1268 {
1269 /*
1270  * This only prints something if at least one of the TM bit is set.
1271  * Inside the TM[], the output means:
1272  *   E: Enabled         (bit 32)
1273  *   S: Suspended       (bit 33)
1274  *   T: Transactional   (bit 34)
1275  */
1276         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1277                 printk(",TM[");
1278                 print_bits(val, msr_tm_bits, "");
1279                 printk("]");
1280         }
1281 }
1282 #else
1283 static void print_tm_bits(unsigned long val) {}
1284 #endif
1285
1286 static void print_msr_bits(unsigned long val)
1287 {
1288         printk("<");
1289         print_bits(val, msr_bits, ",");
1290         print_tm_bits(val);
1291         printk(">");
1292 }
1293
1294 #ifdef CONFIG_PPC64
1295 #define REG             "%016lx"
1296 #define REGS_PER_LINE   4
1297 #define LAST_VOLATILE   13
1298 #else
1299 #define REG             "%08lx"
1300 #define REGS_PER_LINE   8
1301 #define LAST_VOLATILE   12
1302 #endif
1303
1304 void show_regs(struct pt_regs * regs)
1305 {
1306         int i, trap;
1307
1308         show_regs_print_info(KERN_DEFAULT);
1309
1310         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1311                regs->nip, regs->link, regs->ctr);
1312         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1313                regs, regs->trap, print_tainted(), init_utsname()->release);
1314         printk("MSR: "REG" ", regs->msr);
1315         print_msr_bits(regs->msr);
1316         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1317         trap = TRAP(regs);
1318         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1319                 printk("CFAR: "REG" ", regs->orig_gpr3);
1320         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1321 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1322                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1323 #else
1324                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1325 #endif
1326 #ifdef CONFIG_PPC64
1327         printk("SOFTE: %ld ", regs->softe);
1328 #endif
1329 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1330         if (MSR_TM_ACTIVE(regs->msr))
1331                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1332 #endif
1333
1334         for (i = 0;  i < 32;  i++) {
1335                 if ((i % REGS_PER_LINE) == 0)
1336                         printk("\nGPR%02d: ", i);
1337                 printk(REG " ", regs->gpr[i]);
1338                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1339                         break;
1340         }
1341         printk("\n");
1342 #ifdef CONFIG_KALLSYMS
1343         /*
1344          * Lookup NIP late so we have the best change of getting the
1345          * above info out without failing
1346          */
1347         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1348         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1349 #endif
1350         show_stack(current, (unsigned long *) regs->gpr[1]);
1351         if (!user_mode(regs))
1352                 show_instructions(regs);
1353 }
1354
1355 void flush_thread(void)
1356 {
1357 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1358         flush_ptrace_hw_breakpoint(current);
1359 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1360         set_debug_reg_defaults(&current->thread);
1361 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1362 }
1363
1364 void
1365 release_thread(struct task_struct *t)
1366 {
1367 }
1368
1369 /*
1370  * this gets called so that we can store coprocessor state into memory and
1371  * copy the current task into the new thread.
1372  */
1373 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1374 {
1375         flush_all_to_thread(src);
1376         /*
1377          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1378          * flush but it removes the checkpointed state from the current CPU and
1379          * transitions the CPU out of TM mode.  Hence we need to call
1380          * tm_recheckpoint_new_task() (on the same task) to restore the
1381          * checkpointed state back and the TM mode.
1382          */
1383         __switch_to_tm(src);
1384         tm_recheckpoint_new_task(src);
1385
1386         *dst = *src;
1387
1388         clear_task_ebb(dst);
1389
1390         return 0;
1391 }
1392
1393 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1394 {
1395 #ifdef CONFIG_PPC_STD_MMU_64
1396         unsigned long sp_vsid;
1397         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1398
1399         if (radix_enabled())
1400                 return;
1401
1402         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1403                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1404                         << SLB_VSID_SHIFT_1T;
1405         else
1406                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1407                         << SLB_VSID_SHIFT;
1408         sp_vsid |= SLB_VSID_KERNEL | llp;
1409         p->thread.ksp_vsid = sp_vsid;
1410 #endif
1411 }
1412
1413 /*
1414  * Copy a thread..
1415  */
1416
1417 /*
1418  * Copy architecture-specific thread state
1419  */
1420 int copy_thread(unsigned long clone_flags, unsigned long usp,
1421                 unsigned long kthread_arg, struct task_struct *p)
1422 {
1423         struct pt_regs *childregs, *kregs;
1424         extern void ret_from_fork(void);
1425         extern void ret_from_kernel_thread(void);
1426         void (*f)(void);
1427         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1428         struct thread_info *ti = task_thread_info(p);
1429
1430         klp_init_thread_info(ti);
1431
1432         /* Copy registers */
1433         sp -= sizeof(struct pt_regs);
1434         childregs = (struct pt_regs *) sp;
1435         if (unlikely(p->flags & PF_KTHREAD)) {
1436                 /* kernel thread */
1437                 memset(childregs, 0, sizeof(struct pt_regs));
1438                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1439                 /* function */
1440                 if (usp)
1441                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1442 #ifdef CONFIG_PPC64
1443                 clear_tsk_thread_flag(p, TIF_32BIT);
1444                 childregs->softe = 1;
1445 #endif
1446                 childregs->gpr[15] = kthread_arg;
1447                 p->thread.regs = NULL;  /* no user register state */
1448                 ti->flags |= _TIF_RESTOREALL;
1449                 f = ret_from_kernel_thread;
1450         } else {
1451                 /* user thread */
1452                 struct pt_regs *regs = current_pt_regs();
1453                 CHECK_FULL_REGS(regs);
1454                 *childregs = *regs;
1455                 if (usp)
1456                         childregs->gpr[1] = usp;
1457                 p->thread.regs = childregs;
1458                 childregs->gpr[3] = 0;  /* Result from fork() */
1459                 if (clone_flags & CLONE_SETTLS) {
1460 #ifdef CONFIG_PPC64
1461                         if (!is_32bit_task())
1462                                 childregs->gpr[13] = childregs->gpr[6];
1463                         else
1464 #endif
1465                                 childregs->gpr[2] = childregs->gpr[6];
1466                 }
1467
1468                 f = ret_from_fork;
1469         }
1470         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1471         sp -= STACK_FRAME_OVERHEAD;
1472
1473         /*
1474          * The way this works is that at some point in the future
1475          * some task will call _switch to switch to the new task.
1476          * That will pop off the stack frame created below and start
1477          * the new task running at ret_from_fork.  The new task will
1478          * do some house keeping and then return from the fork or clone
1479          * system call, using the stack frame created above.
1480          */
1481         ((unsigned long *)sp)[0] = 0;
1482         sp -= sizeof(struct pt_regs);
1483         kregs = (struct pt_regs *) sp;
1484         sp -= STACK_FRAME_OVERHEAD;
1485         p->thread.ksp = sp;
1486 #ifdef CONFIG_PPC32
1487         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1488                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1489 #endif
1490 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1491         p->thread.ptrace_bps[0] = NULL;
1492 #endif
1493
1494         p->thread.fp_save_area = NULL;
1495 #ifdef CONFIG_ALTIVEC
1496         p->thread.vr_save_area = NULL;
1497 #endif
1498
1499         setup_ksp_vsid(p, sp);
1500
1501 #ifdef CONFIG_PPC64
1502         if (cpu_has_feature(CPU_FTR_DSCR)) {
1503                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1504                 p->thread.dscr = mfspr(SPRN_DSCR);
1505         }
1506         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1507                 p->thread.ppr = INIT_PPR;
1508 #endif
1509         kregs->nip = ppc_function_entry(f);
1510         return 0;
1511 }
1512
1513 /*
1514  * Set up a thread for executing a new program
1515  */
1516 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1517 {
1518 #ifdef CONFIG_PPC64
1519         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1520 #endif
1521
1522         /*
1523          * If we exec out of a kernel thread then thread.regs will not be
1524          * set.  Do it now.
1525          */
1526         if (!current->thread.regs) {
1527                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1528                 current->thread.regs = regs - 1;
1529         }
1530
1531 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1532         /*
1533          * Clear any transactional state, we're exec()ing. The cause is
1534          * not important as there will never be a recheckpoint so it's not
1535          * user visible.
1536          */
1537         if (MSR_TM_SUSPENDED(mfmsr()))
1538                 tm_reclaim_current(0);
1539 #endif
1540
1541         memset(regs->gpr, 0, sizeof(regs->gpr));
1542         regs->ctr = 0;
1543         regs->link = 0;
1544         regs->xer = 0;
1545         regs->ccr = 0;
1546         regs->gpr[1] = sp;
1547
1548         /*
1549          * We have just cleared all the nonvolatile GPRs, so make
1550          * FULL_REGS(regs) return true.  This is necessary to allow
1551          * ptrace to examine the thread immediately after exec.
1552          */
1553         regs->trap &= ~1UL;
1554
1555 #ifdef CONFIG_PPC32
1556         regs->mq = 0;
1557         regs->nip = start;
1558         regs->msr = MSR_USER;
1559 #else
1560         if (!is_32bit_task()) {
1561                 unsigned long entry;
1562
1563                 if (is_elf2_task()) {
1564                         /* Look ma, no function descriptors! */
1565                         entry = start;
1566
1567                         /*
1568                          * Ulrich says:
1569                          *   The latest iteration of the ABI requires that when
1570                          *   calling a function (at its global entry point),
1571                          *   the caller must ensure r12 holds the entry point
1572                          *   address (so that the function can quickly
1573                          *   establish addressability).
1574                          */
1575                         regs->gpr[12] = start;
1576                         /* Make sure that's restored on entry to userspace. */
1577                         set_thread_flag(TIF_RESTOREALL);
1578                 } else {
1579                         unsigned long toc;
1580
1581                         /* start is a relocated pointer to the function
1582                          * descriptor for the elf _start routine.  The first
1583                          * entry in the function descriptor is the entry
1584                          * address of _start and the second entry is the TOC
1585                          * value we need to use.
1586                          */
1587                         __get_user(entry, (unsigned long __user *)start);
1588                         __get_user(toc, (unsigned long __user *)start+1);
1589
1590                         /* Check whether the e_entry function descriptor entries
1591                          * need to be relocated before we can use them.
1592                          */
1593                         if (load_addr != 0) {
1594                                 entry += load_addr;
1595                                 toc   += load_addr;
1596                         }
1597                         regs->gpr[2] = toc;
1598                 }
1599                 regs->nip = entry;
1600                 regs->msr = MSR_USER64;
1601         } else {
1602                 regs->nip = start;
1603                 regs->gpr[2] = 0;
1604                 regs->msr = MSR_USER32;
1605         }
1606 #endif
1607 #ifdef CONFIG_VSX
1608         current->thread.used_vsr = 0;
1609 #endif
1610         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1611         current->thread.fp_save_area = NULL;
1612 #ifdef CONFIG_ALTIVEC
1613         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1614         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1615         current->thread.vr_save_area = NULL;
1616         current->thread.vrsave = 0;
1617         current->thread.used_vr = 0;
1618 #endif /* CONFIG_ALTIVEC */
1619 #ifdef CONFIG_SPE
1620         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1621         current->thread.acc = 0;
1622         current->thread.spefscr = 0;
1623         current->thread.used_spe = 0;
1624 #endif /* CONFIG_SPE */
1625 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1626         if (cpu_has_feature(CPU_FTR_TM))
1627                 regs->msr |= MSR_TM;
1628         current->thread.tm_tfhar = 0;
1629         current->thread.tm_texasr = 0;
1630         current->thread.tm_tfiar = 0;
1631 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1632 }
1633 EXPORT_SYMBOL(start_thread);
1634
1635 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1636                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1637
1638 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1639 {
1640         struct pt_regs *regs = tsk->thread.regs;
1641
1642         /* This is a bit hairy.  If we are an SPE enabled  processor
1643          * (have embedded fp) we store the IEEE exception enable flags in
1644          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1645          * mode (asyn, precise, disabled) for 'Classic' FP. */
1646         if (val & PR_FP_EXC_SW_ENABLE) {
1647 #ifdef CONFIG_SPE
1648                 if (cpu_has_feature(CPU_FTR_SPE)) {
1649                         /*
1650                          * When the sticky exception bits are set
1651                          * directly by userspace, it must call prctl
1652                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1653                          * in the existing prctl settings) or
1654                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1655                          * the bits being set).  <fenv.h> functions
1656                          * saving and restoring the whole
1657                          * floating-point environment need to do so
1658                          * anyway to restore the prctl settings from
1659                          * the saved environment.
1660                          */
1661                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1662                         tsk->thread.fpexc_mode = val &
1663                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1664                         return 0;
1665                 } else {
1666                         return -EINVAL;
1667                 }
1668 #else
1669                 return -EINVAL;
1670 #endif
1671         }
1672
1673         /* on a CONFIG_SPE this does not hurt us.  The bits that
1674          * __pack_fe01 use do not overlap with bits used for
1675          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1676          * on CONFIG_SPE implementations are reserved so writing to
1677          * them does not change anything */
1678         if (val > PR_FP_EXC_PRECISE)
1679                 return -EINVAL;
1680         tsk->thread.fpexc_mode = __pack_fe01(val);
1681         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1682                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1683                         | tsk->thread.fpexc_mode;
1684         return 0;
1685 }
1686
1687 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1688 {
1689         unsigned int val;
1690
1691         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1692 #ifdef CONFIG_SPE
1693                 if (cpu_has_feature(CPU_FTR_SPE)) {
1694                         /*
1695                          * When the sticky exception bits are set
1696                          * directly by userspace, it must call prctl
1697                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1698                          * in the existing prctl settings) or
1699                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1700                          * the bits being set).  <fenv.h> functions
1701                          * saving and restoring the whole
1702                          * floating-point environment need to do so
1703                          * anyway to restore the prctl settings from
1704                          * the saved environment.
1705                          */
1706                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1707                         val = tsk->thread.fpexc_mode;
1708                 } else
1709                         return -EINVAL;
1710 #else
1711                 return -EINVAL;
1712 #endif
1713         else
1714                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1715         return put_user(val, (unsigned int __user *) adr);
1716 }
1717
1718 int set_endian(struct task_struct *tsk, unsigned int val)
1719 {
1720         struct pt_regs *regs = tsk->thread.regs;
1721
1722         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1723             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1724                 return -EINVAL;
1725
1726         if (regs == NULL)
1727                 return -EINVAL;
1728
1729         if (val == PR_ENDIAN_BIG)
1730                 regs->msr &= ~MSR_LE;
1731         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1732                 regs->msr |= MSR_LE;
1733         else
1734                 return -EINVAL;
1735
1736         return 0;
1737 }
1738
1739 int get_endian(struct task_struct *tsk, unsigned long adr)
1740 {
1741         struct pt_regs *regs = tsk->thread.regs;
1742         unsigned int val;
1743
1744         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1745             !cpu_has_feature(CPU_FTR_REAL_LE))
1746                 return -EINVAL;
1747
1748         if (regs == NULL)
1749                 return -EINVAL;
1750
1751         if (regs->msr & MSR_LE) {
1752                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1753                         val = PR_ENDIAN_LITTLE;
1754                 else
1755                         val = PR_ENDIAN_PPC_LITTLE;
1756         } else
1757                 val = PR_ENDIAN_BIG;
1758
1759         return put_user(val, (unsigned int __user *)adr);
1760 }
1761
1762 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1763 {
1764         tsk->thread.align_ctl = val;
1765         return 0;
1766 }
1767
1768 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1769 {
1770         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1771 }
1772
1773 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1774                                   unsigned long nbytes)
1775 {
1776         unsigned long stack_page;
1777         unsigned long cpu = task_cpu(p);
1778
1779         /*
1780          * Avoid crashing if the stack has overflowed and corrupted
1781          * task_cpu(p), which is in the thread_info struct.
1782          */
1783         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1784                 stack_page = (unsigned long) hardirq_ctx[cpu];
1785                 if (sp >= stack_page + sizeof(struct thread_struct)
1786                     && sp <= stack_page + THREAD_SIZE - nbytes)
1787                         return 1;
1788
1789                 stack_page = (unsigned long) softirq_ctx[cpu];
1790                 if (sp >= stack_page + sizeof(struct thread_struct)
1791                     && sp <= stack_page + THREAD_SIZE - nbytes)
1792                         return 1;
1793         }
1794         return 0;
1795 }
1796
1797 int validate_sp(unsigned long sp, struct task_struct *p,
1798                        unsigned long nbytes)
1799 {
1800         unsigned long stack_page = (unsigned long)task_stack_page(p);
1801
1802         if (sp >= stack_page + sizeof(struct thread_struct)
1803             && sp <= stack_page + THREAD_SIZE - nbytes)
1804                 return 1;
1805
1806         return valid_irq_stack(sp, p, nbytes);
1807 }
1808
1809 EXPORT_SYMBOL(validate_sp);
1810
1811 unsigned long get_wchan(struct task_struct *p)
1812 {
1813         unsigned long ip, sp;
1814         int count = 0;
1815
1816         if (!p || p == current || p->state == TASK_RUNNING)
1817                 return 0;
1818
1819         sp = p->thread.ksp;
1820         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1821                 return 0;
1822
1823         do {
1824                 sp = *(unsigned long *)sp;
1825                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1826                         return 0;
1827                 if (count > 0) {
1828                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1829                         if (!in_sched_functions(ip))
1830                                 return ip;
1831                 }
1832         } while (count++ < 16);
1833         return 0;
1834 }
1835
1836 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1837
1838 void show_stack(struct task_struct *tsk, unsigned long *stack)
1839 {
1840         unsigned long sp, ip, lr, newsp;
1841         int count = 0;
1842         int firstframe = 1;
1843 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1844         int curr_frame = current->curr_ret_stack;
1845         extern void return_to_handler(void);
1846         unsigned long rth = (unsigned long)return_to_handler;
1847 #endif
1848
1849         sp = (unsigned long) stack;
1850         if (tsk == NULL)
1851                 tsk = current;
1852         if (sp == 0) {
1853                 if (tsk == current)
1854                         sp = current_stack_pointer();
1855                 else
1856                         sp = tsk->thread.ksp;
1857         }
1858
1859         lr = 0;
1860         printk("Call Trace:\n");
1861         do {
1862                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1863                         return;
1864
1865                 stack = (unsigned long *) sp;
1866                 newsp = stack[0];
1867                 ip = stack[STACK_FRAME_LR_SAVE];
1868                 if (!firstframe || ip != lr) {
1869                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1870 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1871                         if ((ip == rth) && curr_frame >= 0) {
1872                                 printk(" (%pS)",
1873                                        (void *)current->ret_stack[curr_frame].ret);
1874                                 curr_frame--;
1875                         }
1876 #endif
1877                         if (firstframe)
1878                                 printk(" (unreliable)");
1879                         printk("\n");
1880                 }
1881                 firstframe = 0;
1882
1883                 /*
1884                  * See if this is an exception frame.
1885                  * We look for the "regshere" marker in the current frame.
1886                  */
1887                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1888                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1889                         struct pt_regs *regs = (struct pt_regs *)
1890                                 (sp + STACK_FRAME_OVERHEAD);
1891                         lr = regs->link;
1892                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1893                                regs->trap, (void *)regs->nip, (void *)lr);
1894                         firstframe = 1;
1895                 }
1896
1897                 sp = newsp;
1898         } while (count++ < kstack_depth_to_print);
1899 }
1900
1901 #ifdef CONFIG_PPC64
1902 /* Called with hard IRQs off */
1903 void notrace __ppc64_runlatch_on(void)
1904 {
1905         struct thread_info *ti = current_thread_info();
1906         unsigned long ctrl;
1907
1908         ctrl = mfspr(SPRN_CTRLF);
1909         ctrl |= CTRL_RUNLATCH;
1910         mtspr(SPRN_CTRLT, ctrl);
1911
1912         ti->local_flags |= _TLF_RUNLATCH;
1913 }
1914
1915 /* Called with hard IRQs off */
1916 void notrace __ppc64_runlatch_off(void)
1917 {
1918         struct thread_info *ti = current_thread_info();
1919         unsigned long ctrl;
1920
1921         ti->local_flags &= ~_TLF_RUNLATCH;
1922
1923         ctrl = mfspr(SPRN_CTRLF);
1924         ctrl &= ~CTRL_RUNLATCH;
1925         mtspr(SPRN_CTRLT, ctrl);
1926 }
1927 #endif /* CONFIG_PPC64 */
1928
1929 unsigned long arch_align_stack(unsigned long sp)
1930 {
1931         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1932                 sp -= get_random_int() & ~PAGE_MASK;
1933         return sp & ~0xf;
1934 }
1935
1936 static inline unsigned long brk_rnd(void)
1937 {
1938         unsigned long rnd = 0;
1939
1940         /* 8MB for 32bit, 1GB for 64bit */
1941         if (is_32bit_task())
1942                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1943         else
1944                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1945
1946         return rnd << PAGE_SHIFT;
1947 }
1948
1949 unsigned long arch_randomize_brk(struct mm_struct *mm)
1950 {
1951         unsigned long base = mm->brk;
1952         unsigned long ret;
1953
1954 #ifdef CONFIG_PPC_STD_MMU_64
1955         /*
1956          * If we are using 1TB segments and we are allowed to randomise
1957          * the heap, we can put it above 1TB so it is backed by a 1TB
1958          * segment. Otherwise the heap will be in the bottom 1TB
1959          * which always uses 256MB segments and this may result in a
1960          * performance penalty. We don't need to worry about radix. For
1961          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1962          */
1963         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1964                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1965 #endif
1966
1967         ret = PAGE_ALIGN(base + brk_rnd());
1968
1969         if (ret < mm->brk)
1970                 return mm->brk;
1971
1972         return ret;
1973 }
1974