arch/powerpc/kernel/setup_64.c

   1 /*
   2  *
   3  * Common boot and setup code.
   4  *
   5  * Copyright (C) 2001 PPC64 Team, IBM Corp
   6  *
   7  *      This program is free software; you can redistribute it and/or
   8  *      modify it under the terms of the GNU General Public License
   9  *      as published by the Free Software Foundation; either version
  10  *      2 of the License, or (at your option) any later version.
  11  */
  12
  13 #define DEBUG
  14
  15 #include <linux/export.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/reboot.h>
  21 #include <linux/delay.h>
  22 #include <linux/initrd.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/ioport.h>
  25 #include <linux/console.h>
  26 #include <linux/utsname.h>
  27 #include <linux/tty.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/notifier.h>
  30 #include <linux/cpu.h>
  31 #include <linux/unistd.h>
  32 #include <linux/serial.h>
  33 #include <linux/serial_8250.h>
  34 #include <linux/bootmem.h>
  35 #include <linux/pci.h>
  36 #include <linux/lockdep.h>
  37 #include <linux/memblock.h>
  38 #include <linux/hugetlb.h>
  39 #include <linux/memory.h>
  40 #include <linux/nmi.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/kdump.h>
  44 #include <asm/prom.h>
  45 #include <asm/processor.h>
  46 #include <asm/pgtable.h>
  47 #include <asm/smp.h>
  48 #include <asm/elf.h>
  49 #include <asm/machdep.h>
  50 #include <asm/paca.h>
  51 #include <asm/time.h>
  52 #include <asm/cputable.h>
  53 #include <asm/sections.h>
  54 #include <asm/btext.h>
  55 #include <asm/nvram.h>
  56 #include <asm/setup.h>
  57 #include <asm/rtas.h>
  58 #include <asm/iommu.h>
  59 #include <asm/serial.h>
  60 #include <asm/cache.h>
  61 #include <asm/page.h>
  62 #include <asm/mmu.h>
  63 #include <asm/firmware.h>
  64 #include <asm/xmon.h>
  65 #include <asm/udbg.h>
  66 #include <asm/kexec.h>
  67 #include <asm/mmu_context.h>
  68 #include <asm/code-patching.h>
  69 #include <asm/kvm_ppc.h>
  70 #include <asm/hugetlb.h>
  71 #include <asm/epapr_hcalls.h>
  72 #include <asm/livepatch.h>
  73
  74 #ifdef DEBUG
  75 #define DBG(fmt...) udbg_printf(fmt)
  76 #else
  77 #define DBG(fmt...)
  78 #endif
  79
  80 int spinning_secondaries;
  81 u64 ppc64_pft_size;
  82
  83 /* Pick defaults since we might want to patch instructions
  84  * before we've read this from the device tree.
  85  */
  86 struct ppc64_caches ppc64_caches = {
  87         .dline_size = 0x40,
  88         .log_dline_size = 6,
  89         .iline_size = 0x40,
  90         .log_iline_size = 6
  91 };
  92 EXPORT_SYMBOL_GPL(ppc64_caches);
  93
  94 /*
  95  * These are used in binfmt_elf.c to put aux entries on the stack
  96  * for each elf executable being started.
  97  */
  98 int dcache_bsize;
  99 int icache_bsize;
 100 int ucache_bsize;
 101
 102 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
 103 static void setup_tlb_core_data(void)
 104 {
 105         int cpu;
 106
 107         BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
 108
 109         for_each_possible_cpu(cpu) {
 110                 int first = cpu_first_thread_sibling(cpu);
 111
 112                 /*
 113                  * If we boot via kdump on a non-primary thread,
 114                  * make sure we point at the thread that actually
 115                  * set up this TLB.
 116                  */
 117                 if (cpu_first_thread_sibling(boot_cpuid) == first)
 118                         first = boot_cpuid;
 119
 120                 paca[cpu].tcd_ptr = &paca[first].tcd;
 121
 122                 /*
 123                  * If we have threads, we need either tlbsrx.
 124                  * or e6500 tablewalk mode, or else TLB handlers
 125                  * will be racy and could produce duplicate entries.
 126                  */
 127                 if (smt_enabled_at_boot >= 2 &&
 128                     !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
 129                     book3e_htw_mode != PPC_HTW_E6500) {
 130                         /* Should we panic instead? */
 131                         WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
 132                                   __func__);
 133                 }
 134         }
 135 }
 136 #else
 137 static void setup_tlb_core_data(void)
 138 {
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_SMP
 143
 144 static char *smt_enabled_cmdline;
 145
 146 /* Look for ibm,smt-enabled OF option */
 147 static void check_smt_enabled(void)
 148 {
 149         struct device_node *dn;
 150         const char *smt_option;
 151
 152         /* Default to enabling all threads */
 153         smt_enabled_at_boot = threads_per_core;
 154
 155         /* Allow the command line to overrule the OF option */
 156         if (smt_enabled_cmdline) {
 157                 if (!strcmp(smt_enabled_cmdline, "on"))
 158                         smt_enabled_at_boot = threads_per_core;
 159                 else if (!strcmp(smt_enabled_cmdline, "off"))
 160                         smt_enabled_at_boot = 0;
 161                 else {
 162                         int smt;
 163                         int rc;
 164
 165                         rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
 166                         if (!rc)
 167                                 smt_enabled_at_boot =
 168                                         min(threads_per_core, smt);
 169                 }
 170         } else {
 171                 dn = of_find_node_by_path("/options");
 172                 if (dn) {
 173                         smt_option = of_get_property(dn, "ibm,smt-enabled",
 174                                                      NULL);
 175
 176                         if (smt_option) {
 177                                 if (!strcmp(smt_option, "on"))
 178                                         smt_enabled_at_boot = threads_per_core;
 179                                 else if (!strcmp(smt_option, "off"))
 180                                         smt_enabled_at_boot = 0;
 181                         }
 182
 183                         of_node_put(dn);
 184                 }
 185         }
 186 }
 187
 188 /* Look for smt-enabled= cmdline option */
 189 static int __init early_smt_enabled(char *p)
 190 {
 191         smt_enabled_cmdline = p;
 192         return 0;
 193 }
 194 early_param("smt-enabled", early_smt_enabled);
 195
 196 #else
 197 #define check_smt_enabled()
 198 #endif /* CONFIG_SMP */
 199
 200 /** Fix up paca fields required for the boot cpu */
 201 static void fixup_boot_paca(void)
 202 {
 203         /* The boot cpu is started */
 204         get_paca()->cpu_start = 1;
 205         /* Allow percpu accesses to work until we setup percpu data */
 206         get_paca()->data_offset = 0;
 207 }
 208
 209 static void cpu_ready_for_interrupts(void)
 210 {
 211         /* Set IR and DR in PACA MSR */
 212         get_paca()->kernel_msr = MSR_KERNEL;
 213
 214         /*
 215          * Enable AIL if supported, and we are in hypervisor mode. If we are
 216          * not in hypervisor mode, we enable relocation-on interrupts later
 217          * in pSeries_setup_arch() using the H_SET_MODE hcall.
 218          */
 219         if (cpu_has_feature(CPU_FTR_HVMODE) &&
 220             cpu_has_feature(CPU_FTR_ARCH_207S)) {
 221                 unsigned long lpcr = mfspr(SPRN_LPCR);
 222                 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
 223         }
 224 }
 225
 226 /*
 227  * Early initialization entry point. This is called by head.S
 228  * with MMU translation disabled. We rely on the "feature" of
 229  * the CPU that ignores the top 2 bits of the address in real
 230  * mode so we can access kernel globals normally provided we
 231  * only toy with things in the RMO region. From here, we do
 232  * some early parsing of the device-tree to setup out MEMBLOCK
 233  * data structures, and allocate & initialize the hash table
 234  * and segment tables so we can start running with translation
 235  * enabled.
 236  *
 237  * It is this function which will call the probe() callback of
 238  * the various platform types and copy the matching one to the
 239  * global ppc_md structure. Your platform can eventually do
 240  * some very early initializations from the probe() routine, but
 241  * this is not recommended, be very careful as, for example, the
 242  * device-tree is not accessible via normal means at this point.
 243  */
 244
 245 void __init early_setup(unsigned long dt_ptr)
 246 {
 247         static __initdata struct paca_struct boot_paca;
 248
 249         /* -------- printk is _NOT_ safe to use here ! ------- */
 250
 251         /* Identify CPU type */
 252         identify_cpu(0, mfspr(SPRN_PVR));
 253
 254         /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
 255         initialise_paca(&boot_paca, 0);
 256         setup_paca(&boot_paca);
 257         fixup_boot_paca();
 258
 259         /* Initialize lockdep early or else spinlocks will blow */
 260         lockdep_init();
 261
 262         /* -------- printk is now safe to use ------- */
 263
 264         /* Enable early debugging if any specified (see udbg.h) */
 265         udbg_early_init();
 266
 267         DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
 268
 269         /*
 270          * Do early initialization using the flattened device
 271          * tree, such as retrieving the physical memory map or
 272          * calculating/retrieving the hash table size.
 273          */
 274         early_init_devtree(__va(dt_ptr));
 275
 276         epapr_paravirt_early_init();
 277
 278         /* Now we know the logical id of our boot cpu, setup the paca. */
 279         setup_paca(&paca[boot_cpuid]);
 280         fixup_boot_paca();
 281
 282         /* Probe the machine type */
 283         probe_machine();
 284
 285         setup_kdump_trampoline();
 286
 287         DBG("Found, Initializing memory management...\n");
 288
 289         /* Initialize the hash table or TLB handling */
 290         early_init_mmu();
 291
 292         /*
 293          * At this point, we can let interrupts switch to virtual mode
 294          * (the MMU has been setup), so adjust the MSR in the PACA to
 295          * have IR and DR set and enable AIL if it exists
 296          */
 297         cpu_ready_for_interrupts();
 298
 299         /* Reserve large chunks of memory for use by CMA for KVM */
 300         kvm_cma_reserve();
 301
 302         /*
 303          * Reserve any gigantic pages requested on the command line.
 304          * memblock needs to have been initialized by the time this is
 305          * called since this will reserve memory.
 306          */
 307         reserve_hugetlb_gpages();
 308
 309         DBG(" <- early_setup()\n");
 310
 311 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
 312         /*
 313          * This needs to be done *last* (after the above DBG() even)
 314          *
 315          * Right after we return from this function, we turn on the MMU
 316          * which means the real-mode access trick that btext does will
 317          * no longer work, it needs to switch to using a real MMU
 318          * mapping. This call will ensure that it does
 319          */
 320         btext_map();
 321 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
 322 }
 323
 324 #ifdef CONFIG_SMP
 325 void early_setup_secondary(void)
 326 {
 327         /* Mark interrupts enabled in PACA */
 328         get_paca()->soft_enabled = 0;
 329
 330         /* Initialize the hash table or TLB handling */
 331         early_init_mmu_secondary();
 332
 333         /*
 334          * At this point, we can let interrupts switch to virtual mode
 335          * (the MMU has been setup), so adjust the MSR in the PACA to
 336          * have IR and DR set.
 337          */
 338         cpu_ready_for_interrupts();
 339 }
 340
 341 #endif /* CONFIG_SMP */
 342
 343 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 344 static bool use_spinloop(void)
 345 {
 346         if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
 347                 return true;
 348
 349         /*
 350          * When book3e boots from kexec, the ePAPR spin table does
 351          * not get used.
 352          */
 353         return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
 354 }
 355
 356 void smp_release_cpus(void)
 357 {
 358         unsigned long *ptr;
 359         int i;
 360
 361         if (!use_spinloop())
 362                 return;
 363
 364         DBG(" -> smp_release_cpus()\n");
 365
 366         /* All secondary cpus are spinning on a common spinloop, release them
 367          * all now so they can start to spin on their individual paca
 368          * spinloops. For non SMP kernels, the secondary cpus never get out
 369          * of the common spinloop.
 370          */
 371
 372         ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
 373                         - PHYSICAL_START);
 374         *ptr = ppc_function_entry(generic_secondary_smp_init);
 375
 376         /* And wait a bit for them to catch up */
 377         for (i = 0; i < 100000; i++) {
 378                 mb();
 379                 HMT_low();
 380                 if (spinning_secondaries == 0)
 381                         break;
 382                 udelay(1);
 383         }
 384         DBG("spinning_secondaries = %d\n", spinning_secondaries);
 385
 386         DBG(" <- smp_release_cpus()\n");
 387 }
 388 #endif /* CONFIG_SMP || CONFIG_KEXEC */
 389
 390 /*
 391  * Initialize some remaining members of the ppc64_caches and systemcfg
 392  * structures
 393  * (at least until we get rid of them completely). This is mostly some
 394  * cache informations about the CPU that will be used by cache flush
 395  * routines and/or provided to userland
 396  */
 397 static void __init initialize_cache_info(void)
 398 {
 399         struct device_node *np;
 400         unsigned long num_cpus = 0;
 401
 402         DBG(" -> initialize_cache_info()\n");
 403
 404         for_each_node_by_type(np, "cpu") {
 405                 num_cpus += 1;
 406
 407                 /*
 408                  * We're assuming *all* of the CPUs have the same
 409                  * d-cache and i-cache sizes... -Peter
 410                  */
 411                 if (num_cpus == 1) {
 412                         const __be32 *sizep, *lsizep;
 413                         u32 size, lsize;
 414
 415                         size = 0;
 416                         lsize = cur_cpu_spec->dcache_bsize;
 417                         sizep = of_get_property(np, "d-cache-size", NULL);
 418                         if (sizep != NULL)
 419                                 size = be32_to_cpu(*sizep);
 420                         lsizep = of_get_property(np, "d-cache-block-size",
 421                                                  NULL);
 422                         /* fallback if block size missing */
 423                         if (lsizep == NULL)
 424                                 lsizep = of_get_property(np,
 425                                                          "d-cache-line-size",
 426                                                          NULL);
 427                         if (lsizep != NULL)
 428                                 lsize = be32_to_cpu(*lsizep);
 429                         if (sizep == NULL || lsizep == NULL)
 430                                 DBG("Argh, can't find dcache properties ! "
 431                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 432
 433                         ppc64_caches.dsize = size;
 434                         ppc64_caches.dline_size = lsize;
 435                         ppc64_caches.log_dline_size = __ilog2(lsize);
 436                         ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
 437
 438                         size = 0;
 439                         lsize = cur_cpu_spec->icache_bsize;
 440                         sizep = of_get_property(np, "i-cache-size", NULL);
 441                         if (sizep != NULL)
 442                                 size = be32_to_cpu(*sizep);
 443                         lsizep = of_get_property(np, "i-cache-block-size",
 444                                                  NULL);
 445                         if (lsizep == NULL)
 446                                 lsizep = of_get_property(np,
 447                                                          "i-cache-line-size",
 448                                                          NULL);
 449                         if (lsizep != NULL)
 450                                 lsize = be32_to_cpu(*lsizep);
 451                         if (sizep == NULL || lsizep == NULL)
 452                                 DBG("Argh, can't find icache properties ! "
 453                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 454
 455                         ppc64_caches.isize = size;
 456                         ppc64_caches.iline_size = lsize;
 457                         ppc64_caches.log_iline_size = __ilog2(lsize);
 458                         ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
 459                 }
 460         }
 461
 462         DBG(" <- initialize_cache_info()\n");
 463 }
 464
 465
 466 /*
 467  * Do some initial setup of the system.  The parameters are those which
 468  * were passed in from the bootloader.
 469  */
 470 void __init setup_system(void)
 471 {
 472         DBG(" -> setup_system()\n");
 473
 474         /* Apply the CPUs-specific and firmware specific fixups to kernel
 475          * text (nop out sections not relevant to this CPU or this firmware)
 476          */
 477         do_feature_fixups(cur_cpu_spec->cpu_features,
 478                           &__start___ftr_fixup, &__stop___ftr_fixup);
 479         do_feature_fixups(cur_cpu_spec->mmu_features,
 480                           &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
 481         do_feature_fixups(powerpc_firmware_features,
 482                           &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
 483         do_lwsync_fixups(cur_cpu_spec->cpu_features,
 484                          &__start___lwsync_fixup, &__stop___lwsync_fixup);
 485         do_final_fixups();
 486
 487         /*
 488          * Unflatten the device-tree passed by prom_init or kexec
 489          */
 490         unflatten_device_tree();
 491
 492         /*
 493          * Fill the ppc64_caches & systemcfg structures with informations
 494          * retrieved from the device-tree.
 495          */
 496         initialize_cache_info();
 497
 498 #ifdef CONFIG_PPC_RTAS
 499         /*
 500          * Initialize RTAS if available
 501          */
 502         rtas_initialize();
 503 #endif /* CONFIG_PPC_RTAS */
 504
 505         /*
 506          * Check if we have an initrd provided via the device-tree
 507          */
 508         check_for_initrd();
 509
 510         /*
 511          * Do some platform specific early initializations, that includes
 512          * setting up the hash table pointers. It also sets up some interrupt-mapping
 513          * related options that will be used by finish_device_tree()
 514          */
 515         if (ppc_md.init_early)
 516                 ppc_md.init_early();
 517
 518         /*
 519          * We can discover serial ports now since the above did setup the
 520          * hash table management for us, thus ioremap works. We do that early
 521          * so that further code can be debugged
 522          */
 523         find_legacy_serial_ports();
 524
 525         /*
 526          * Register early console
 527          */
 528         register_early_udbg_console();
 529
 530         /*
 531          * Initialize xmon
 532          */
 533         xmon_setup();
 534
 535         smp_setup_cpu_maps();
 536         check_smt_enabled();
 537         setup_tlb_core_data();
 538
 539         /*
 540          * Freescale Book3e parts spin in a loop provided by firmware,
 541          * so smp_release_cpus() does nothing for them
 542          */
 543 #if defined(CONFIG_SMP)
 544         /* Release secondary cpus out of their spinloops at 0x60 now that
 545          * we can map physical -> logical CPU ids
 546          */
 547         smp_release_cpus();
 548 #endif
 549
 550         pr_info("Starting Linux %s %s\n", init_utsname()->machine,
 551                  init_utsname()->version);
 552
 553         pr_info("-----------------------------------------------------\n");
 554         pr_info("ppc64_pft_size    = 0x%llx\n", ppc64_pft_size);
 555         pr_info("phys_mem_size     = 0x%llx\n", memblock_phys_mem_size());
 556
 557         if (ppc64_caches.dline_size != 0x80)
 558                 pr_info("dcache_line_size  = 0x%x\n", ppc64_caches.dline_size);
 559         if (ppc64_caches.iline_size != 0x80)
 560                 pr_info("icache_line_size  = 0x%x\n", ppc64_caches.iline_size);
 561
 562         pr_info("cpu_features      = 0x%016lx\n", cur_cpu_spec->cpu_features);
 563         pr_info("  possible        = 0x%016lx\n", CPU_FTRS_POSSIBLE);
 564         pr_info("  always          = 0x%016lx\n", CPU_FTRS_ALWAYS);
 565         pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
 566                 cur_cpu_spec->cpu_user_features2);
 567         pr_info("mmu_features      = 0x%08x\n", cur_cpu_spec->mmu_features);
 568         pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
 569
 570 #ifdef CONFIG_PPC_STD_MMU_64
 571         if (htab_address)
 572                 pr_info("htab_address      = 0x%p\n", htab_address);
 573
 574         pr_info("htab_hash_mask    = 0x%lx\n", htab_hash_mask);
 575 #endif
 576
 577         if (PHYSICAL_START > 0)
 578                 pr_info("physical_start    = 0x%llx\n",
 579                        (unsigned long long)PHYSICAL_START);
 580         pr_info("-----------------------------------------------------\n");
 581
 582         DBG(" <- setup_system()\n");
 583 }
 584
 585 /* This returns the limit below which memory accesses to the linear
 586  * mapping are guarnateed not to cause a TLB or SLB miss. This is
 587  * used to allocate interrupt or emergency stacks for which our
 588  * exception entry path doesn't deal with being interrupted.
 589  */
 590 static u64 safe_stack_limit(void)
 591 {
 592 #ifdef CONFIG_PPC_BOOK3E
 593         /* Freescale BookE bolts the entire linear mapping */
 594         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 595                 return linear_map_top;
 596         /* Other BookE, we assume the first GB is bolted */
 597         return 1ul << 30;
 598 #else
 599         /* BookS, the first segment is bolted */
 600         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
 601                 return 1UL << SID_SHIFT_1T;
 602         return 1UL << SID_SHIFT;
 603 #endif
 604 }
 605
 606 static void __init irqstack_early_init(void)
 607 {
 608         u64 limit = safe_stack_limit();
 609         unsigned int i;
 610
 611         /*
 612          * Interrupt stacks must be in the first segment since we
 613          * cannot afford to take SLB misses on them.
 614          */
 615         for_each_possible_cpu(i) {
 616                 softirq_ctx[i] = (struct thread_info *)
 617                         __va(memblock_alloc_base(THREAD_SIZE,
 618                                             THREAD_SIZE, limit));
 619                 hardirq_ctx[i] = (struct thread_info *)
 620                         __va(memblock_alloc_base(THREAD_SIZE,
 621                                             THREAD_SIZE, limit));
 622         }
 623 }
 624
 625 #ifdef CONFIG_PPC_BOOK3E
 626 static void __init exc_lvl_early_init(void)
 627 {
 628         unsigned int i;
 629         unsigned long sp;
 630
 631         for_each_possible_cpu(i) {
 632                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 633                 critirq_ctx[i] = (struct thread_info *)__va(sp);
 634                 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
 635
 636                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 637                 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
 638                 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
 639
 640                 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
 641                 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
 642                 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
 643         }
 644
 645         if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 646                 patch_exception(0x040, exc_debug_debug_book3e);
 647 }
 648 #else
 649 #define exc_lvl_early_init()
 650 #endif
 651
 652 /*
 653  * Stack space used when we detect a bad kernel stack pointer, and
 654  * early in SMP boots before relocation is enabled. Exclusive emergency
 655  * stack for machine checks.
 656  */
 657 static void __init emergency_stack_init(void)
 658 {
 659         u64 limit;
 660         unsigned int i;
 661
 662         /*
 663          * Emergency stacks must be under 256MB, we cannot afford to take
 664          * SLB misses on them. The ABI also requires them to be 128-byte
 665          * aligned.
 666          *
 667          * Since we use these as temporary stacks during secondary CPU
 668          * bringup, we need to get at them in real mode. This means they
 669          * must also be within the RMO region.
 670          */
 671         limit = min(safe_stack_limit(), ppc64_rma_size);
 672
 673         for_each_possible_cpu(i) {
 674                 struct thread_info *ti;
 675                 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
 676                 klp_init_thread_info(ti);
 677                 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
 678
 679 #ifdef CONFIG_PPC_BOOK3S_64
 680                 /* emergency stack for machine check exception handling. */
 681                 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
 682                 klp_init_thread_info(ti);
 683                 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
 684 #endif
 685         }
 686 }
 687
 688 /*
 689  * Called into from start_kernel this initializes memblock, which is used
 690  * to manage page allocation until mem_init is called.
 691  */
 692 void __init setup_arch(char **cmdline_p)
 693 {
 694         *cmdline_p = boot_command_line;
 695
 696         /*
 697          * Set cache line size based on type of cpu as a default.
 698          * Systems with OF can look in the properties on the cpu node(s)
 699          * for a possibly more accurate value.
 700          */
 701         dcache_bsize = ppc64_caches.dline_size;
 702         icache_bsize = ppc64_caches.iline_size;
 703
 704         if (ppc_md.panic)
 705                 setup_panic();
 706
 707         klp_init_thread_info(&init_thread_info);
 708
 709         init_mm.start_code = (unsigned long)_stext;
 710         init_mm.end_code = (unsigned long) _etext;
 711         init_mm.end_data = (unsigned long) _edata;
 712         init_mm.brk = klimit;
 713 #ifdef CONFIG_PPC_64K_PAGES
 714         init_mm.context.pte_frag = NULL;
 715 #endif
 716 #ifdef CONFIG_SPAPR_TCE_IOMMU
 717         mm_iommu_init(&init_mm.context);
 718 #endif
 719         irqstack_early_init();
 720         exc_lvl_early_init();
 721         emergency_stack_init();
 722
 723         initmem_init();
 724
 725 #ifdef CONFIG_DUMMY_CONSOLE
 726         conswitchp = &dummy_con;
 727 #endif
 728
 729         if (ppc_md.setup_arch)
 730                 ppc_md.setup_arch();
 731
 732         paging_init();
 733
 734         /* Initialize the MMU context management stuff */
 735         mmu_context_init();
 736
 737         /* Interrupt code needs to be 64K-aligned */
 738         if ((unsigned long)_stext & 0xffff)
 739                 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
 740                       (unsigned long)_stext);
 741 }
 742
 743 #ifdef CONFIG_SMP
 744 #define PCPU_DYN_SIZE           ()
 745
 746 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
 747 {
 748         return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
 749                                     __pa(MAX_DMA_ADDRESS));
 750 }
 751
 752 static void __init pcpu_fc_free(void *ptr, size_t size)
 753 {
 754         free_bootmem(__pa(ptr), size);
 755 }
 756
 757 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
 758 {
 759         if (cpu_to_node(from) == cpu_to_node(to))
 760                 return LOCAL_DISTANCE;
 761         else
 762                 return REMOTE_DISTANCE;
 763 }
 764
 765 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
 766 EXPORT_SYMBOL(__per_cpu_offset);
 767
 768 void __init setup_per_cpu_areas(void)
 769 {
 770         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
 771         size_t atom_size;
 772         unsigned long delta;
 773         unsigned int cpu;
 774         int rc;
 775
 776         /*
 777          * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
 778          * to group units.  For larger mappings, use 1M atom which
 779          * should be large enough to contain a number of units.
 780          */
 781         if (mmu_linear_psize == MMU_PAGE_4K)
 782                 atom_size = PAGE_SIZE;
 783         else
 784                 atom_size = 1 << 20;
 785
 786         rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
 787                                     pcpu_fc_alloc, pcpu_fc_free);
 788         if (rc < 0)
 789                 panic("cannot initialize percpu area (err=%d)", rc);
 790
 791         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
 792         for_each_possible_cpu(cpu) {
 793                 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
 794                 paca[cpu].data_offset = __per_cpu_offset[cpu];
 795         }
 796 }
 797 #endif
 798
 799 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
 800 unsigned long memory_block_size_bytes(void)
 801 {
 802         if (ppc_md.memory_block_size)
 803                 return ppc_md.memory_block_size();
 804
 805         return MIN_MEMORY_BLOCK_SIZE;
 806 }
 807 #endif
 808
 809 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
 810 struct ppc_pci_io ppc_pci_io;
 811 EXPORT_SYMBOL(ppc_pci_io);
 812 #endif
 813
 814 #ifdef CONFIG_HARDLOCKUP_DETECTOR
 815 u64 hw_nmi_get_sample_period(int watchdog_thresh)
 816 {
 817         return ppc_proc_freq * watchdog_thresh;
 818 }
 819
 820 /*
 821  * The hardlockup detector breaks PMU event based branches and is likely
 822  * to get false positives in KVM guests, so disable it by default.
 823  */
 824 static int __init disable_hardlockup_detector(void)
 825 {
 826         hardlockup_detector_disable();
 827
 828         return 0;
 829 }
 830 early_initcall(disable_hardlockup_detector);
 831 #endif