2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
62 #include <asm/debug.h>
63 #include <asm/asm-prototypes.h>
64 #include <sysdev/fsl_pci.h>
66 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
67 int (*__debugger)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
71 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
75 EXPORT_SYMBOL(__debugger);
76 EXPORT_SYMBOL(__debugger_ipi);
77 EXPORT_SYMBOL(__debugger_bpt);
78 EXPORT_SYMBOL(__debugger_sstep);
79 EXPORT_SYMBOL(__debugger_iabr_match);
80 EXPORT_SYMBOL(__debugger_break_match);
81 EXPORT_SYMBOL(__debugger_fault_handler);
84 /* Transactional Memory trap debug */
86 #define TM_DEBUG(x...) printk(KERN_INFO x)
88 #define TM_DEBUG(x...) do { } while(0)
92 * Trap & Exception support
95 #ifdef CONFIG_PMAC_BACKLIGHT
96 static void pmac_backlight_unblank(void)
98 mutex_lock(&pmac_backlight_mutex);
100 struct backlight_properties *props;
102 props = &pmac_backlight->props;
103 props->brightness = props->max_brightness;
104 props->power = FB_BLANK_UNBLANK;
105 backlight_update_status(pmac_backlight);
107 mutex_unlock(&pmac_backlight_mutex);
110 static inline void pmac_backlight_unblank(void) { }
113 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
114 static int die_owner = -1;
115 static unsigned int die_nest_count;
116 static int die_counter;
118 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
128 /* racy, but better than risking deadlock. */
129 raw_local_irq_save(flags);
130 cpu = smp_processor_id();
131 if (!arch_spin_trylock(&die_lock)) {
132 if (cpu == die_owner)
133 /* nested oops. should stop eventually */;
135 arch_spin_lock(&die_lock);
141 if (machine_is(powermac))
142 pmac_backlight_unblank();
146 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
151 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
156 /* Nest count reaches zero, release the lock. */
157 arch_spin_unlock(&die_lock);
158 raw_local_irq_restore(flags);
160 crash_fadump(regs, "die oops");
163 * A system reset (0x100) is a request to dump, so we always send
164 * it through the crashdump code.
166 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
170 * We aren't the primary crash CPU. We need to send it
171 * to a holding pattern to avoid it ending up in the panic
174 crash_kexec_secondary(regs);
181 * While our oops output is serialised by a spinlock, output
182 * from panic() called below can race and corrupt it. If we
183 * know we are going to panic, delay for 1 second so we have a
184 * chance to get clean backtraces from all CPUs that are oopsing.
186 if (in_interrupt() || panic_on_oops || !current->pid ||
187 is_global_init(current)) {
188 mdelay(MSEC_PER_SEC);
192 panic("Fatal exception in interrupt");
194 panic("Fatal exception");
198 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
200 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
201 #ifdef CONFIG_PREEMPT
205 printk("SMP NR_CPUS=%d ", NR_CPUS);
207 if (debug_pagealloc_enabled())
208 printk("DEBUG_PAGEALLOC ");
212 printk("%s\n", ppc_md.name ? ppc_md.name : "");
214 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
223 void die(const char *str, struct pt_regs *regs, long err)
225 unsigned long flags = oops_begin(regs);
227 if (__die(str, regs, err))
229 oops_end(flags, regs, err);
232 void user_single_step_siginfo(struct task_struct *tsk,
233 struct pt_regs *regs, siginfo_t *info)
235 memset(info, 0, sizeof(*info));
236 info->si_signo = SIGTRAP;
237 info->si_code = TRAP_TRACE;
238 info->si_addr = (void __user *)regs->nip;
241 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
244 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
245 "at %08lx nip %08lx lr %08lx code %x\n";
246 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
247 "at %016lx nip %016lx lr %016lx code %x\n";
249 if (!user_mode(regs)) {
250 die("Exception in kernel mode", regs, signr);
254 if (show_unhandled_signals && unhandled_signal(current, signr)) {
255 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
256 current->comm, current->pid, signr,
257 addr, regs->nip, regs->link, code);
260 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
263 current->thread.trap_nr = code;
264 memset(&info, 0, sizeof(info));
265 info.si_signo = signr;
267 info.si_addr = (void __user *) addr;
268 force_sig_info(signr, &info, current);
272 void system_reset_exception(struct pt_regs *regs)
274 /* See if any machine dependent calls */
275 if (ppc_md.system_reset_exception) {
276 if (ppc_md.system_reset_exception(regs))
280 die("System Reset", regs, SIGABRT);
282 /* Must die if the interrupt is not recoverable */
283 if (!(regs->msr & MSR_RI))
284 panic("Unrecoverable System Reset");
286 /* What should we do here? We could issue a shutdown or hard reset. */
290 * This function is called in real mode. Strictly no printk's please.
292 * regs->nip and regs->msr contains srr0 and ssr1.
294 long machine_check_early(struct pt_regs *regs)
298 __this_cpu_inc(irq_stat.mce_exceptions);
300 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
302 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
303 handled = cur_cpu_spec->machine_check_early(regs);
307 long hmi_exception_realmode(struct pt_regs *regs)
309 __this_cpu_inc(irq_stat.hmi_exceptions);
311 if (ppc_md.hmi_exception_early)
312 ppc_md.hmi_exception_early(regs);
320 * I/O accesses can cause machine checks on powermacs.
321 * Check if the NIP corresponds to the address of a sync
322 * instruction for which there is an entry in the exception
324 * Note that the 601 only takes a machine check on TEA
325 * (transfer error ack) signal assertion, and does not
326 * set any of the top 16 bits of SRR1.
329 static inline int check_io_access(struct pt_regs *regs)
332 unsigned long msr = regs->msr;
333 const struct exception_table_entry *entry;
334 unsigned int *nip = (unsigned int *)regs->nip;
336 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
337 && (entry = search_exception_tables(regs->nip)) != NULL) {
339 * Check that it's a sync instruction, or somewhere
340 * in the twi; isync; nop sequence that inb/inw/inl uses.
341 * As the address is in the exception table
342 * we should be able to read the instr there.
343 * For the debug message, we look at the preceding
346 if (*nip == 0x60000000) /* nop */
348 else if (*nip == 0x4c00012c) /* isync */
350 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
355 rb = (*nip >> 11) & 0x1f;
356 printk(KERN_DEBUG "%s bad port %lx at %p\n",
357 (*nip & 0x100)? "OUT to": "IN from",
358 regs->gpr[rb] - _IO_BASE, nip);
360 regs->nip = entry->fixup;
364 #endif /* CONFIG_PPC32 */
368 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
369 /* On 4xx, the reason for the machine check or program exception
371 #define get_reason(regs) ((regs)->dsisr)
372 #ifndef CONFIG_FSL_BOOKE
373 #define get_mc_reason(regs) ((regs)->dsisr)
375 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
377 #define REASON_FP ESR_FP
378 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
379 #define REASON_PRIVILEGED ESR_PPR
380 #define REASON_TRAP ESR_PTR
382 /* single-step stuff */
383 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
384 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
387 /* On non-4xx, the reason for the machine check or program
388 exception is in the MSR. */
389 #define get_reason(regs) ((regs)->msr)
390 #define get_mc_reason(regs) ((regs)->msr)
391 #define REASON_TM 0x200000
392 #define REASON_FP 0x100000
393 #define REASON_ILLEGAL 0x80000
394 #define REASON_PRIVILEGED 0x40000
395 #define REASON_TRAP 0x20000
397 #define single_stepping(regs) ((regs)->msr & MSR_SE)
398 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
401 #if defined(CONFIG_4xx)
402 int machine_check_4xx(struct pt_regs *regs)
404 unsigned long reason = get_mc_reason(regs);
406 if (reason & ESR_IMCP) {
407 printk("Instruction");
408 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
411 printk(" machine check in kernel mode.\n");
416 int machine_check_440A(struct pt_regs *regs)
418 unsigned long reason = get_mc_reason(regs);
420 printk("Machine check in kernel mode.\n");
421 if (reason & ESR_IMCP){
422 printk("Instruction Synchronous Machine Check exception\n");
423 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
426 u32 mcsr = mfspr(SPRN_MCSR);
428 printk("Instruction Read PLB Error\n");
430 printk("Data Read PLB Error\n");
432 printk("Data Write PLB Error\n");
433 if (mcsr & MCSR_TLBP)
434 printk("TLB Parity Error\n");
435 if (mcsr & MCSR_ICP){
436 flush_instruction_cache();
437 printk("I-Cache Parity Error\n");
439 if (mcsr & MCSR_DCSP)
440 printk("D-Cache Search Parity Error\n");
441 if (mcsr & MCSR_DCFP)
442 printk("D-Cache Flush Parity Error\n");
443 if (mcsr & MCSR_IMPE)
444 printk("Machine Check exception is imprecise\n");
447 mtspr(SPRN_MCSR, mcsr);
452 int machine_check_47x(struct pt_regs *regs)
454 unsigned long reason = get_mc_reason(regs);
457 printk(KERN_ERR "Machine check in kernel mode.\n");
458 if (reason & ESR_IMCP) {
460 "Instruction Synchronous Machine Check exception\n");
461 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
464 mcsr = mfspr(SPRN_MCSR);
466 printk(KERN_ERR "Instruction Read PLB Error\n");
468 printk(KERN_ERR "Data Read PLB Error\n");
470 printk(KERN_ERR "Data Write PLB Error\n");
471 if (mcsr & MCSR_TLBP)
472 printk(KERN_ERR "TLB Parity Error\n");
473 if (mcsr & MCSR_ICP) {
474 flush_instruction_cache();
475 printk(KERN_ERR "I-Cache Parity Error\n");
477 if (mcsr & MCSR_DCSP)
478 printk(KERN_ERR "D-Cache Search Parity Error\n");
479 if (mcsr & PPC47x_MCSR_GPR)
480 printk(KERN_ERR "GPR Parity Error\n");
481 if (mcsr & PPC47x_MCSR_FPR)
482 printk(KERN_ERR "FPR Parity Error\n");
483 if (mcsr & PPC47x_MCSR_IPR)
484 printk(KERN_ERR "Machine Check exception is imprecise\n");
487 mtspr(SPRN_MCSR, mcsr);
491 #elif defined(CONFIG_E500)
492 int machine_check_e500mc(struct pt_regs *regs)
494 unsigned long mcsr = mfspr(SPRN_MCSR);
495 unsigned long reason = mcsr;
498 if (reason & MCSR_LD) {
499 recoverable = fsl_rio_mcheck_exception(regs);
500 if (recoverable == 1)
504 printk("Machine check in kernel mode.\n");
505 printk("Caused by (from MCSR=%lx): ", reason);
507 if (reason & MCSR_MCP)
508 printk("Machine Check Signal\n");
510 if (reason & MCSR_ICPERR) {
511 printk("Instruction Cache Parity Error\n");
514 * This is recoverable by invalidating the i-cache.
516 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
517 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
521 * This will generally be accompanied by an instruction
522 * fetch error report -- only treat MCSR_IF as fatal
523 * if it wasn't due to an L1 parity error.
528 if (reason & MCSR_DCPERR_MC) {
529 printk("Data Cache Parity Error\n");
532 * In write shadow mode we auto-recover from the error, but it
533 * may still get logged and cause a machine check. We should
534 * only treat the non-write shadow case as non-recoverable.
536 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
540 if (reason & MCSR_L2MMU_MHIT) {
541 printk("Hit on multiple TLB entries\n");
545 if (reason & MCSR_NMI)
546 printk("Non-maskable interrupt\n");
548 if (reason & MCSR_IF) {
549 printk("Instruction Fetch Error Report\n");
553 if (reason & MCSR_LD) {
554 printk("Load Error Report\n");
558 if (reason & MCSR_ST) {
559 printk("Store Error Report\n");
563 if (reason & MCSR_LDG) {
564 printk("Guarded Load Error Report\n");
568 if (reason & MCSR_TLBSYNC)
569 printk("Simultaneous tlbsync operations\n");
571 if (reason & MCSR_BSL2_ERR) {
572 printk("Level 2 Cache Error\n");
576 if (reason & MCSR_MAV) {
579 addr = mfspr(SPRN_MCAR);
580 addr |= (u64)mfspr(SPRN_MCARU) << 32;
582 printk("Machine Check %s Address: %#llx\n",
583 reason & MCSR_MEA ? "Effective" : "Physical", addr);
587 mtspr(SPRN_MCSR, mcsr);
588 return mfspr(SPRN_MCSR) == 0 && recoverable;
591 int machine_check_e500(struct pt_regs *regs)
593 unsigned long reason = get_mc_reason(regs);
595 if (reason & MCSR_BUS_RBERR) {
596 if (fsl_rio_mcheck_exception(regs))
598 if (fsl_pci_mcheck_exception(regs))
602 printk("Machine check in kernel mode.\n");
603 printk("Caused by (from MCSR=%lx): ", reason);
605 if (reason & MCSR_MCP)
606 printk("Machine Check Signal\n");
607 if (reason & MCSR_ICPERR)
608 printk("Instruction Cache Parity Error\n");
609 if (reason & MCSR_DCP_PERR)
610 printk("Data Cache Push Parity Error\n");
611 if (reason & MCSR_DCPERR)
612 printk("Data Cache Parity Error\n");
613 if (reason & MCSR_BUS_IAERR)
614 printk("Bus - Instruction Address Error\n");
615 if (reason & MCSR_BUS_RAERR)
616 printk("Bus - Read Address Error\n");
617 if (reason & MCSR_BUS_WAERR)
618 printk("Bus - Write Address Error\n");
619 if (reason & MCSR_BUS_IBERR)
620 printk("Bus - Instruction Data Error\n");
621 if (reason & MCSR_BUS_RBERR)
622 printk("Bus - Read Data Bus Error\n");
623 if (reason & MCSR_BUS_WBERR)
624 printk("Bus - Write Data Bus Error\n");
625 if (reason & MCSR_BUS_IPERR)
626 printk("Bus - Instruction Parity Error\n");
627 if (reason & MCSR_BUS_RPERR)
628 printk("Bus - Read Parity Error\n");
633 int machine_check_generic(struct pt_regs *regs)
637 #elif defined(CONFIG_E200)
638 int machine_check_e200(struct pt_regs *regs)
640 unsigned long reason = get_mc_reason(regs);
642 printk("Machine check in kernel mode.\n");
643 printk("Caused by (from MCSR=%lx): ", reason);
645 if (reason & MCSR_MCP)
646 printk("Machine Check Signal\n");
647 if (reason & MCSR_CP_PERR)
648 printk("Cache Push Parity Error\n");
649 if (reason & MCSR_CPERR)
650 printk("Cache Parity Error\n");
651 if (reason & MCSR_EXCP_ERR)
652 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
653 if (reason & MCSR_BUS_IRERR)
654 printk("Bus - Read Bus Error on instruction fetch\n");
655 if (reason & MCSR_BUS_DRERR)
656 printk("Bus - Read Bus Error on data load\n");
657 if (reason & MCSR_BUS_WRERR)
658 printk("Bus - Write Bus Error on buffered store or cache line push\n");
663 int machine_check_generic(struct pt_regs *regs)
665 unsigned long reason = get_mc_reason(regs);
667 printk("Machine check in kernel mode.\n");
668 printk("Caused by (from SRR1=%lx): ", reason);
669 switch (reason & 0x601F0000) {
671 printk("Machine check signal\n");
673 case 0: /* for 601 */
675 case 0x140000: /* 7450 MSS error and TEA */
676 printk("Transfer error ack signal\n");
679 printk("Data parity error signal\n");
682 printk("Address parity error signal\n");
685 printk("L1 Data Cache error\n");
688 printk("L1 Instruction Cache error\n");
691 printk("L2 data cache parity error\n");
694 printk("Unknown values in msr\n");
698 #endif /* everything else */
700 void machine_check_exception(struct pt_regs *regs)
702 enum ctx_state prev_state = exception_enter();
705 __this_cpu_inc(irq_stat.mce_exceptions);
707 /* See if any machine dependent calls. In theory, we would want
708 * to call the CPU first, and call the ppc_md. one if the CPU
709 * one returns a positive number. However there is existing code
710 * that assumes the board gets a first chance, so let's keep it
711 * that way for now and fix things later. --BenH.
713 if (ppc_md.machine_check_exception)
714 recover = ppc_md.machine_check_exception(regs);
715 else if (cur_cpu_spec->machine_check)
716 recover = cur_cpu_spec->machine_check(regs);
721 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
722 /* the qspan pci read routines can cause machine checks -- Cort
724 * yuck !!! that totally needs to go away ! There are better ways
725 * to deal with that than having a wart in the mcheck handler.
728 bad_page_fault(regs, regs->dar, SIGBUS);
732 if (debugger_fault_handler(regs))
735 if (check_io_access(regs))
738 die("Machine check", regs, SIGBUS);
740 /* Must die if the interrupt is not recoverable */
741 if (!(regs->msr & MSR_RI))
742 panic("Unrecoverable Machine check");
745 exception_exit(prev_state);
748 void SMIException(struct pt_regs *regs)
750 die("System Management Interrupt", regs, SIGABRT);
753 void handle_hmi_exception(struct pt_regs *regs)
755 struct pt_regs *old_regs;
757 old_regs = set_irq_regs(regs);
760 if (ppc_md.handle_hmi_exception)
761 ppc_md.handle_hmi_exception(regs);
764 set_irq_regs(old_regs);
767 void unknown_exception(struct pt_regs *regs)
769 enum ctx_state prev_state = exception_enter();
771 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
772 regs->nip, regs->msr, regs->trap);
774 _exception(SIGTRAP, regs, 0, 0);
776 exception_exit(prev_state);
779 void instruction_breakpoint_exception(struct pt_regs *regs)
781 enum ctx_state prev_state = exception_enter();
783 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
784 5, SIGTRAP) == NOTIFY_STOP)
786 if (debugger_iabr_match(regs))
788 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
791 exception_exit(prev_state);
794 void RunModeException(struct pt_regs *regs)
796 _exception(SIGTRAP, regs, 0, 0);
799 void __kprobes single_step_exception(struct pt_regs *regs)
801 enum ctx_state prev_state = exception_enter();
803 clear_single_step(regs);
805 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
806 5, SIGTRAP) == NOTIFY_STOP)
808 if (debugger_sstep(regs))
811 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
814 exception_exit(prev_state);
818 * After we have successfully emulated an instruction, we have to
819 * check if the instruction was being single-stepped, and if so,
820 * pretend we got a single-step exception. This was pointed out
821 * by Kumar Gala. -- paulus
823 static void emulate_single_step(struct pt_regs *regs)
825 if (single_stepping(regs))
826 single_step_exception(regs);
829 static inline int __parse_fpscr(unsigned long fpscr)
833 /* Invalid operation */
834 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
838 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
842 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
846 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
850 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
856 static void parse_fpe(struct pt_regs *regs)
860 flush_fp_to_thread(current);
862 code = __parse_fpscr(current->thread.fp_state.fpscr);
864 _exception(SIGFPE, regs, code, regs->nip);
868 * Illegal instruction emulation support. Originally written to
869 * provide the PVR to user applications using the mfspr rd, PVR.
870 * Return non-zero if we can't emulate, or -EFAULT if the associated
871 * memory access caused an access fault. Return zero on success.
873 * There are a couple of ways to do this, either "decode" the instruction
874 * or directly match lots of bits. In this case, matching lots of
875 * bits is faster and easier.
878 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
880 u8 rT = (instword >> 21) & 0x1f;
881 u8 rA = (instword >> 16) & 0x1f;
882 u8 NB_RB = (instword >> 11) & 0x1f;
887 /* Early out if we are an invalid form of lswx */
888 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
889 if ((rT == rA) || (rT == NB_RB))
892 EA = (rA == 0) ? 0 : regs->gpr[rA];
894 switch (instword & PPC_INST_STRING_MASK) {
898 num_bytes = regs->xer & 0x7f;
902 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
908 while (num_bytes != 0)
911 u32 shift = 8 * (3 - (pos & 0x3));
913 /* if process is 32-bit, clear upper 32 bits of EA */
914 if ((regs->msr & MSR_64BIT) == 0)
917 switch ((instword & PPC_INST_STRING_MASK)) {
920 if (get_user(val, (u8 __user *)EA))
922 /* first time updating this reg,
926 regs->gpr[rT] |= val << shift;
930 val = regs->gpr[rT] >> shift;
931 if (put_user(val, (u8 __user *)EA))
935 /* move EA to next address */
939 /* manage our position within the register */
950 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
955 ra = (instword >> 16) & 0x1f;
956 rs = (instword >> 21) & 0x1f;
959 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
960 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
961 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
967 static int emulate_isel(struct pt_regs *regs, u32 instword)
969 u8 rT = (instword >> 21) & 0x1f;
970 u8 rA = (instword >> 16) & 0x1f;
971 u8 rB = (instword >> 11) & 0x1f;
972 u8 BC = (instword >> 6) & 0x1f;
976 tmp = (rA == 0) ? 0 : regs->gpr[rA];
977 bit = (regs->ccr >> (31 - BC)) & 0x1;
979 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
984 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
985 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
987 /* If we're emulating a load/store in an active transaction, we cannot
988 * emulate it as the kernel operates in transaction suspended context.
989 * We need to abort the transaction. This creates a persistent TM
990 * abort so tell the user what caused it with a new code.
992 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1000 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1006 static int emulate_instruction(struct pt_regs *regs)
1011 if (!user_mode(regs))
1013 CHECK_FULL_REGS(regs);
1015 if (get_user(instword, (u32 __user *)(regs->nip)))
1018 /* Emulate the mfspr rD, PVR. */
1019 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1020 PPC_WARN_EMULATED(mfpvr, regs);
1021 rd = (instword >> 21) & 0x1f;
1022 regs->gpr[rd] = mfspr(SPRN_PVR);
1026 /* Emulating the dcba insn is just a no-op. */
1027 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1028 PPC_WARN_EMULATED(dcba, regs);
1032 /* Emulate the mcrxr insn. */
1033 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1034 int shift = (instword >> 21) & 0x1c;
1035 unsigned long msk = 0xf0000000UL >> shift;
1037 PPC_WARN_EMULATED(mcrxr, regs);
1038 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1039 regs->xer &= ~0xf0000000UL;
1043 /* Emulate load/store string insn. */
1044 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1045 if (tm_abort_check(regs,
1046 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1048 PPC_WARN_EMULATED(string, regs);
1049 return emulate_string_inst(regs, instword);
1052 /* Emulate the popcntb (Population Count Bytes) instruction. */
1053 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1054 PPC_WARN_EMULATED(popcntb, regs);
1055 return emulate_popcntb_inst(regs, instword);
1058 /* Emulate isel (Integer Select) instruction */
1059 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1060 PPC_WARN_EMULATED(isel, regs);
1061 return emulate_isel(regs, instword);
1064 /* Emulate sync instruction variants */
1065 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1066 PPC_WARN_EMULATED(sync, regs);
1067 asm volatile("sync");
1072 /* Emulate the mfspr rD, DSCR. */
1073 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1074 PPC_INST_MFSPR_DSCR_USER) ||
1075 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1076 PPC_INST_MFSPR_DSCR)) &&
1077 cpu_has_feature(CPU_FTR_DSCR)) {
1078 PPC_WARN_EMULATED(mfdscr, regs);
1079 rd = (instword >> 21) & 0x1f;
1080 regs->gpr[rd] = mfspr(SPRN_DSCR);
1083 /* Emulate the mtspr DSCR, rD. */
1084 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1085 PPC_INST_MTSPR_DSCR_USER) ||
1086 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1087 PPC_INST_MTSPR_DSCR)) &&
1088 cpu_has_feature(CPU_FTR_DSCR)) {
1089 PPC_WARN_EMULATED(mtdscr, regs);
1090 rd = (instword >> 21) & 0x1f;
1091 current->thread.dscr = regs->gpr[rd];
1092 current->thread.dscr_inherit = 1;
1093 mtspr(SPRN_DSCR, current->thread.dscr);
1101 int is_valid_bugaddr(unsigned long addr)
1103 return is_kernel_addr(addr);
1106 #ifdef CONFIG_MATH_EMULATION
1107 static int emulate_math(struct pt_regs *regs)
1110 extern int do_mathemu(struct pt_regs *regs);
1112 ret = do_mathemu(regs);
1114 PPC_WARN_EMULATED(math, regs);
1118 emulate_single_step(regs);
1122 code = __parse_fpscr(current->thread.fp_state.fpscr);
1123 _exception(SIGFPE, regs, code, regs->nip);
1127 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1134 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1137 void __kprobes program_check_exception(struct pt_regs *regs)
1139 enum ctx_state prev_state = exception_enter();
1140 unsigned int reason = get_reason(regs);
1142 /* We can now get here via a FP Unavailable exception if the core
1143 * has no FPU, in that case the reason flags will be 0 */
1145 if (reason & REASON_FP) {
1146 /* IEEE FP exception */
1150 if (reason & REASON_TRAP) {
1151 unsigned long bugaddr;
1152 /* Debugger is first in line to stop recursive faults in
1153 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1154 if (debugger_bpt(regs))
1157 /* trap exception */
1158 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1162 bugaddr = regs->nip;
1164 * Fixup bugaddr for BUG_ON() in real mode
1166 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1167 bugaddr += PAGE_OFFSET;
1169 if (!(regs->msr & MSR_PR) && /* not user-mode */
1170 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1174 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1177 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1178 if (reason & REASON_TM) {
1179 /* This is a TM "Bad Thing Exception" program check.
1181 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1182 * transition in TM states.
1183 * - A trechkpt is attempted when transactional.
1184 * - A treclaim is attempted when non transactional.
1185 * - A tend is illegally attempted.
1186 * - writing a TM SPR when transactional.
1188 if (!user_mode(regs) &&
1189 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1193 /* If usermode caused this, it's done something illegal and
1194 * gets a SIGILL slap on the wrist. We call it an illegal
1195 * operand to distinguish from the instruction just being bad
1196 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1197 * illegal /placement/ of a valid instruction.
1199 if (user_mode(regs)) {
1200 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1203 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1204 "at %lx (msr 0x%x)\n", regs->nip, reason);
1205 die("Unrecoverable exception", regs, SIGABRT);
1211 * If we took the program check in the kernel skip down to sending a
1212 * SIGILL. The subsequent cases all relate to emulating instructions
1213 * which we should only do for userspace. We also do not want to enable
1214 * interrupts for kernel faults because that might lead to further
1215 * faults, and loose the context of the original exception.
1217 if (!user_mode(regs))
1220 /* We restore the interrupt state now */
1221 if (!arch_irq_disabled_regs(regs))
1224 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1225 * but there seems to be a hardware bug on the 405GP (RevD)
1226 * that means ESR is sometimes set incorrectly - either to
1227 * ESR_DST (!?) or 0. In the process of chasing this with the
1228 * hardware people - not sure if it can happen on any illegal
1229 * instruction or only on FP instructions, whether there is a
1230 * pattern to occurrences etc. -dgibson 31/Mar/2003
1232 if (!emulate_math(regs))
1235 /* Try to emulate it if we should. */
1236 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1237 switch (emulate_instruction(regs)) {
1240 emulate_single_step(regs);
1243 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1249 if (reason & REASON_PRIVILEGED)
1250 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1252 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1255 exception_exit(prev_state);
1259 * This occurs when running in hypervisor mode on POWER6 or later
1260 * and an illegal instruction is encountered.
1262 void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1264 regs->msr |= REASON_ILLEGAL;
1265 program_check_exception(regs);
1268 void alignment_exception(struct pt_regs *regs)
1270 enum ctx_state prev_state = exception_enter();
1271 int sig, code, fixed = 0;
1273 /* We restore the interrupt state now */
1274 if (!arch_irq_disabled_regs(regs))
1277 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1280 /* we don't implement logging of alignment exceptions */
1281 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1282 fixed = fix_alignment(regs);
1285 regs->nip += 4; /* skip over emulated instruction */
1286 emulate_single_step(regs);
1290 /* Operand address was bad */
1291 if (fixed == -EFAULT) {
1298 if (user_mode(regs))
1299 _exception(sig, regs, code, regs->dar);
1301 bad_page_fault(regs, regs->dar, sig);
1304 exception_exit(prev_state);
1307 void StackOverflow(struct pt_regs *regs)
1309 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1310 current, regs->gpr[1]);
1313 panic("kernel stack overflow");
1316 void nonrecoverable_exception(struct pt_regs *regs)
1318 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1319 regs->nip, regs->msr);
1321 die("nonrecoverable exception", regs, SIGKILL);
1324 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1326 enum ctx_state prev_state = exception_enter();
1328 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1329 "%lx at %lx\n", regs->trap, regs->nip);
1330 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1332 exception_exit(prev_state);
1335 void altivec_unavailable_exception(struct pt_regs *regs)
1337 enum ctx_state prev_state = exception_enter();
1339 if (user_mode(regs)) {
1340 /* A user program has executed an altivec instruction,
1341 but this kernel doesn't support altivec. */
1342 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1346 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1347 "%lx at %lx\n", regs->trap, regs->nip);
1348 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1351 exception_exit(prev_state);
1354 void vsx_unavailable_exception(struct pt_regs *regs)
1356 if (user_mode(regs)) {
1357 /* A user program has executed an vsx instruction,
1358 but this kernel doesn't support vsx. */
1359 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1363 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1364 "%lx at %lx\n", regs->trap, regs->nip);
1365 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1369 void facility_unavailable_exception(struct pt_regs *regs)
1371 static char *facility_strings[] = {
1372 [FSCR_FP_LG] = "FPU",
1373 [FSCR_VECVSX_LG] = "VMX/VSX",
1374 [FSCR_DSCR_LG] = "DSCR",
1375 [FSCR_PM_LG] = "PMU SPRs",
1376 [FSCR_BHRB_LG] = "BHRB",
1377 [FSCR_TM_LG] = "TM",
1378 [FSCR_EBB_LG] = "EBB",
1379 [FSCR_TAR_LG] = "TAR",
1380 [FSCR_LM_LG] = "LM",
1382 char *facility = "unknown";
1388 hv = (regs->trap == 0xf80);
1390 value = mfspr(SPRN_HFSCR);
1392 value = mfspr(SPRN_FSCR);
1394 status = value >> 56;
1395 if (status == FSCR_DSCR_LG) {
1397 * User is accessing the DSCR register using the problem
1398 * state only SPR number (0x03) either through a mfspr or
1399 * a mtspr instruction. If it is a write attempt through
1400 * a mtspr, then we set the inherit bit. This also allows
1401 * the user to write or read the register directly in the
1402 * future by setting via the FSCR DSCR bit. But in case it
1403 * is a read DSCR attempt through a mfspr instruction, we
1404 * just emulate the instruction instead. This code path will
1405 * always emulate all the mfspr instructions till the user
1406 * has attempted at least one mtspr instruction. This way it
1407 * preserves the same behaviour when the user is accessing
1408 * the DSCR through privilege level only SPR number (0x11)
1409 * which is emulated through illegal instruction exception.
1410 * We always leave HFSCR DSCR set.
1412 if (get_user(instword, (u32 __user *)(regs->nip))) {
1413 pr_err("Failed to fetch the user instruction\n");
1417 /* Write into DSCR (mtspr 0x03, RS) */
1418 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1419 == PPC_INST_MTSPR_DSCR_USER) {
1420 rd = (instword >> 21) & 0x1f;
1421 current->thread.dscr = regs->gpr[rd];
1422 current->thread.dscr_inherit = 1;
1423 current->thread.fscr |= FSCR_DSCR;
1424 mtspr(SPRN_FSCR, current->thread.fscr);
1427 /* Read from DSCR (mfspr RT, 0x03) */
1428 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1429 == PPC_INST_MFSPR_DSCR_USER) {
1430 if (emulate_instruction(regs)) {
1431 pr_err("DSCR based mfspr emulation failed\n");
1435 emulate_single_step(regs);
1438 } else if ((status == FSCR_LM_LG) && cpu_has_feature(CPU_FTR_ARCH_300)) {
1440 * This process has touched LM, so turn it on forever
1443 current->thread.fscr |= FSCR_LM;
1444 mtspr(SPRN_FSCR, current->thread.fscr);
1448 if ((status < ARRAY_SIZE(facility_strings)) &&
1449 facility_strings[status])
1450 facility = facility_strings[status];
1452 /* We restore the interrupt state now */
1453 if (!arch_irq_disabled_regs(regs))
1457 "%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1458 hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
1460 if (user_mode(regs)) {
1461 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1465 die("Unexpected facility unavailable exception", regs, SIGABRT);
1469 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1471 void fp_unavailable_tm(struct pt_regs *regs)
1473 /* Note: This does not handle any kind of FP laziness. */
1475 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1476 regs->nip, regs->msr);
1478 /* We can only have got here if the task started using FP after
1479 * beginning the transaction. So, the transactional regs are just a
1480 * copy of the checkpointed ones. But, we still need to recheckpoint
1481 * as we're enabling FP for the process; it will return, abort the
1482 * transaction, and probably retry but now with FP enabled. So the
1483 * checkpointed FP registers need to be loaded.
1485 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1486 /* Reclaim didn't save out any FPRs to transact_fprs. */
1488 /* Enable FP for the task: */
1489 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1491 /* This loads and recheckpoints the FP registers from
1492 * thread.fpr[]. They will remain in registers after the
1493 * checkpoint so we don't need to reload them after.
1494 * If VMX is in use, the VRs now hold checkpointed values,
1495 * so we don't want to load the VRs from the thread_struct.
1497 tm_recheckpoint(¤t->thread, MSR_FP);
1499 /* If VMX is in use, get the transactional values back */
1500 if (regs->msr & MSR_VEC) {
1501 do_load_up_transact_altivec(¤t->thread);
1502 /* At this point all the VSX state is loaded, so enable it */
1503 regs->msr |= MSR_VSX;
1507 void altivec_unavailable_tm(struct pt_regs *regs)
1509 /* See the comments in fp_unavailable_tm(). This function operates
1513 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1515 regs->nip, regs->msr);
1516 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1517 regs->msr |= MSR_VEC;
1518 tm_recheckpoint(¤t->thread, MSR_VEC);
1519 current->thread.used_vr = 1;
1521 if (regs->msr & MSR_FP) {
1522 do_load_up_transact_fpu(¤t->thread);
1523 regs->msr |= MSR_VSX;
1527 void vsx_unavailable_tm(struct pt_regs *regs)
1529 unsigned long orig_msr = regs->msr;
1531 /* See the comments in fp_unavailable_tm(). This works similarly,
1532 * though we're loading both FP and VEC registers in here.
1534 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1535 * regs. Either way, set MSR_VSX.
1538 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1540 regs->nip, regs->msr);
1542 current->thread.used_vsr = 1;
1544 /* If FP and VMX are already loaded, we have all the state we need */
1545 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
1546 regs->msr |= MSR_VSX;
1550 /* This reclaims FP and/or VR regs if they're already enabled */
1551 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1553 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1556 /* This loads & recheckpoints FP and VRs; but we have
1557 * to be sure not to overwrite previously-valid state.
1559 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr);
1561 if (orig_msr & MSR_FP)
1562 do_load_up_transact_fpu(¤t->thread);
1563 if (orig_msr & MSR_VEC)
1564 do_load_up_transact_altivec(¤t->thread);
1566 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1568 void performance_monitor_exception(struct pt_regs *regs)
1570 __this_cpu_inc(irq_stat.pmu_irqs);
1576 void SoftwareEmulation(struct pt_regs *regs)
1578 CHECK_FULL_REGS(regs);
1580 if (!user_mode(regs)) {
1582 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1586 if (!emulate_math(regs))
1589 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1591 #endif /* CONFIG_8xx */
1593 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1594 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1598 * Determine the cause of the debug event, clear the
1599 * event flags and send a trap to the handler. Torez
1601 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1602 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1603 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1604 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1606 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1609 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1610 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1611 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1614 } else if (debug_status & DBSR_IAC1) {
1615 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1616 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1617 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1620 } else if (debug_status & DBSR_IAC2) {
1621 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1622 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1625 } else if (debug_status & DBSR_IAC3) {
1626 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1627 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1628 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1631 } else if (debug_status & DBSR_IAC4) {
1632 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1633 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1638 * At the point this routine was called, the MSR(DE) was turned off.
1639 * Check all other debug flags and see if that bit needs to be turned
1642 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1643 current->thread.debug.dbcr1))
1644 regs->msr |= MSR_DE;
1646 /* Make sure the IDM flag is off */
1647 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1650 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1653 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1655 current->thread.debug.dbsr = debug_status;
1657 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1658 * on server, it stops on the target of the branch. In order to simulate
1659 * the server behaviour, we thus restart right away with a single step
1660 * instead of stopping here when hitting a BT
1662 if (debug_status & DBSR_BT) {
1663 regs->msr &= ~MSR_DE;
1666 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1667 /* Clear the BT event */
1668 mtspr(SPRN_DBSR, DBSR_BT);
1670 /* Do the single step trick only when coming from userspace */
1671 if (user_mode(regs)) {
1672 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1673 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1674 regs->msr |= MSR_DE;
1678 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1679 5, SIGTRAP) == NOTIFY_STOP) {
1682 if (debugger_sstep(regs))
1684 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1685 regs->msr &= ~MSR_DE;
1687 /* Disable instruction completion */
1688 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1689 /* Clear the instruction completion event */
1690 mtspr(SPRN_DBSR, DBSR_IC);
1692 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1693 5, SIGTRAP) == NOTIFY_STOP) {
1697 if (debugger_sstep(regs))
1700 if (user_mode(regs)) {
1701 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1702 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1703 current->thread.debug.dbcr1))
1704 regs->msr |= MSR_DE;
1706 /* Make sure the IDM bit is off */
1707 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1710 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1712 handle_debug(regs, debug_status);
1714 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1716 #if !defined(CONFIG_TAU_INT)
1717 void TAUException(struct pt_regs *regs)
1719 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1720 regs->nip, regs->msr, regs->trap, print_tainted());
1722 #endif /* CONFIG_INT_TAU */
1724 #ifdef CONFIG_ALTIVEC
1725 void altivec_assist_exception(struct pt_regs *regs)
1729 if (!user_mode(regs)) {
1730 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1731 " at %lx\n", regs->nip);
1732 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1735 flush_altivec_to_thread(current);
1737 PPC_WARN_EMULATED(altivec, regs);
1738 err = emulate_altivec(regs);
1740 regs->nip += 4; /* skip emulated instruction */
1741 emulate_single_step(regs);
1745 if (err == -EFAULT) {
1746 /* got an error reading the instruction */
1747 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1749 /* didn't recognize the instruction */
1750 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1751 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1752 "in %s at %lx\n", current->comm, regs->nip);
1753 current->thread.vr_state.vscr.u[3] |= 0x10000;
1756 #endif /* CONFIG_ALTIVEC */
1758 #ifdef CONFIG_FSL_BOOKE
1759 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1760 unsigned long error_code)
1762 /* We treat cache locking instructions from the user
1763 * as priv ops, in the future we could try to do
1766 if (error_code & (ESR_DLK|ESR_ILK))
1767 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1770 #endif /* CONFIG_FSL_BOOKE */
1773 void SPEFloatingPointException(struct pt_regs *regs)
1775 extern int do_spe_mathemu(struct pt_regs *regs);
1776 unsigned long spefscr;
1781 flush_spe_to_thread(current);
1783 spefscr = current->thread.spefscr;
1784 fpexc_mode = current->thread.fpexc_mode;
1786 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1789 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1792 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1794 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1797 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1800 err = do_spe_mathemu(regs);
1802 regs->nip += 4; /* skip emulated instruction */
1803 emulate_single_step(regs);
1807 if (err == -EFAULT) {
1808 /* got an error reading the instruction */
1809 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1810 } else if (err == -EINVAL) {
1811 /* didn't recognize the instruction */
1812 printk(KERN_ERR "unrecognized spe instruction "
1813 "in %s at %lx\n", current->comm, regs->nip);
1815 _exception(SIGFPE, regs, code, regs->nip);
1821 void SPEFloatingPointRoundException(struct pt_regs *regs)
1823 extern int speround_handler(struct pt_regs *regs);
1827 if (regs->msr & MSR_SPE)
1828 giveup_spe(current);
1832 err = speround_handler(regs);
1834 regs->nip += 4; /* skip emulated instruction */
1835 emulate_single_step(regs);
1839 if (err == -EFAULT) {
1840 /* got an error reading the instruction */
1841 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1842 } else if (err == -EINVAL) {
1843 /* didn't recognize the instruction */
1844 printk(KERN_ERR "unrecognized spe instruction "
1845 "in %s at %lx\n", current->comm, regs->nip);
1847 _exception(SIGFPE, regs, 0, regs->nip);
1854 * We enter here if we get an unrecoverable exception, that is, one
1855 * that happened at a point where the RI (recoverable interrupt) bit
1856 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1857 * we therefore lost state by taking this exception.
1859 void unrecoverable_exception(struct pt_regs *regs)
1861 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1862 regs->trap, regs->nip);
1863 die("Unrecoverable exception", regs, SIGABRT);
1866 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1868 * Default handler for a Watchdog exception,
1869 * spins until a reboot occurs
1871 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1873 /* Generic WatchdogHandler, implement your own */
1874 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1878 void WatchdogException(struct pt_regs *regs)
1880 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1881 WatchdogHandler(regs);
1886 * We enter here if we discover during exception entry that we are
1887 * running in supervisor mode with a userspace value in the stack pointer.
1889 void kernel_bad_stack(struct pt_regs *regs)
1891 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1892 regs->gpr[1], regs->nip);
1893 die("Bad kernel stack pointer", regs, SIGABRT);
1896 void __init trap_init(void)
1901 #ifdef CONFIG_PPC_EMULATED_STATS
1903 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1905 struct ppc_emulated ppc_emulated = {
1906 #ifdef CONFIG_ALTIVEC
1907 WARN_EMULATED_SETUP(altivec),
1909 WARN_EMULATED_SETUP(dcba),
1910 WARN_EMULATED_SETUP(dcbz),
1911 WARN_EMULATED_SETUP(fp_pair),
1912 WARN_EMULATED_SETUP(isel),
1913 WARN_EMULATED_SETUP(mcrxr),
1914 WARN_EMULATED_SETUP(mfpvr),
1915 WARN_EMULATED_SETUP(multiple),
1916 WARN_EMULATED_SETUP(popcntb),
1917 WARN_EMULATED_SETUP(spe),
1918 WARN_EMULATED_SETUP(string),
1919 WARN_EMULATED_SETUP(sync),
1920 WARN_EMULATED_SETUP(unaligned),
1921 #ifdef CONFIG_MATH_EMULATION
1922 WARN_EMULATED_SETUP(math),
1925 WARN_EMULATED_SETUP(vsx),
1928 WARN_EMULATED_SETUP(mfdscr),
1929 WARN_EMULATED_SETUP(mtdscr),
1930 WARN_EMULATED_SETUP(lq_stq),
1934 u32 ppc_warn_emulated;
1936 void ppc_warn_emulated_print(const char *type)
1938 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1942 static int __init ppc_warn_emulated_init(void)
1944 struct dentry *dir, *d;
1946 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1948 if (!powerpc_debugfs_root)
1951 dir = debugfs_create_dir("emulated_instructions",
1952 powerpc_debugfs_root);
1956 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1957 &ppc_warn_emulated);
1961 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1962 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1963 (u32 *)&entries[i].val.counter);
1971 debugfs_remove_recursive(dir);
1975 device_initcall(ppc_warn_emulated_init);
1977 #endif /* CONFIG_PPC_EMULATED_STATS */