2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
9 #include <linux/types.h>
10 #include <linux/string.h>
11 #include <linux/kvm.h>
12 #include <linux/kvm_host.h>
13 #include <linux/hugetlb.h>
14 #include <linux/module.h>
16 #include <asm/tlbflush.h>
17 #include <asm/kvm_ppc.h>
18 #include <asm/kvm_book3s.h>
19 #include <asm/mmu-hash64.h>
20 #include <asm/hvcall.h>
21 #include <asm/synch.h>
22 #include <asm/ppc-opcode.h>
24 /* Translate address of a vmalloc'd thing to a linear map address */
25 static void *real_vmalloc_addr(void *x)
27 unsigned long addr = (unsigned long) x;
30 p = find_linux_pte(swapper_pg_dir, addr);
31 if (!p || !pte_present(*p))
33 /* assume we don't have huge pages in vmalloc space... */
34 addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
38 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
39 static int global_invalidates(struct kvm *kvm, unsigned long flags)
44 * If there is only one vcore, and it's currently running,
45 * we can use tlbiel as long as we mark all other physical
46 * cores as potentially having stale TLB entries for this lpid.
47 * If we're not using MMU notifiers, we never take pages away
48 * from the guest, so we can use tlbiel if requested.
49 * Otherwise, don't use tlbiel.
51 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcore)
53 else if (kvm->arch.using_mmu_notifiers)
56 global = !(flags & H_LOCAL);
59 /* any other core might now have stale TLB entries... */
61 cpumask_setall(&kvm->arch.need_tlb_flush);
62 cpumask_clear_cpu(local_paca->kvm_hstate.kvm_vcore->pcpu,
63 &kvm->arch.need_tlb_flush);
70 * Add this HPTE into the chain for the real page.
71 * Must be called with the chain locked; it unlocks the chain.
73 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
74 unsigned long *rmap, long pte_index, int realmode)
76 struct revmap_entry *head, *tail;
79 if (*rmap & KVMPPC_RMAP_PRESENT) {
80 i = *rmap & KVMPPC_RMAP_INDEX;
81 head = &kvm->arch.revmap[i];
83 head = real_vmalloc_addr(head);
84 tail = &kvm->arch.revmap[head->back];
86 tail = real_vmalloc_addr(tail);
88 rev->back = head->back;
89 tail->forw = pte_index;
90 head->back = pte_index;
92 rev->forw = rev->back = pte_index;
93 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
94 pte_index | KVMPPC_RMAP_PRESENT;
98 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
100 /* Remove this HPTE from the chain for a real page */
101 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
102 struct revmap_entry *rev,
103 unsigned long hpte_v, unsigned long hpte_r)
105 struct revmap_entry *next, *prev;
106 unsigned long gfn, ptel, head;
107 struct kvm_memory_slot *memslot;
109 unsigned long rcbits;
111 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
112 ptel = rev->guest_rpte |= rcbits;
113 gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
114 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
118 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
121 head = *rmap & KVMPPC_RMAP_INDEX;
122 next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]);
123 prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]);
124 next->back = rev->back;
125 prev->forw = rev->forw;
126 if (head == pte_index) {
128 if (head == pte_index)
129 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
131 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
133 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
137 static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
138 int writing, unsigned long *pte_sizep)
141 unsigned long ps = *pte_sizep;
144 ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
148 *pte_sizep = 1ul << shift;
150 *pte_sizep = PAGE_SIZE;
153 if (!pte_present(*ptep))
155 return kvmppc_read_update_linux_pte(ptep, writing);
158 static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
160 asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
164 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
165 long pte_index, unsigned long pteh, unsigned long ptel,
166 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
168 unsigned long i, pa, gpa, gfn, psize;
169 unsigned long slot_fn, hva;
171 struct revmap_entry *rev;
172 unsigned long g_ptel;
173 struct kvm_memory_slot *memslot;
174 unsigned long *physp, pte_size;
178 unsigned int writing;
179 unsigned long mmu_seq;
180 unsigned long rcbits;
182 psize = hpte_page_size(pteh, ptel);
185 writing = hpte_is_writable(ptel);
186 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
187 ptel &= ~HPTE_GR_RESERVED;
190 /* used later to detect if we might have been invalidated */
191 mmu_seq = kvm->mmu_notifier_seq;
194 /* Find the memslot (if any) for this address */
195 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
196 gfn = gpa >> PAGE_SHIFT;
197 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
201 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
202 /* PPC970 can't do emulated MMIO */
203 if (!cpu_has_feature(CPU_FTR_ARCH_206))
205 /* Emulated MMIO - mark this with key=31 */
206 pteh |= HPTE_V_ABSENT;
207 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
211 /* Check if the requested page fits entirely in the memslot. */
212 if (!slot_is_aligned(memslot, psize))
214 slot_fn = gfn - memslot->base_gfn;
215 rmap = &memslot->arch.rmap[slot_fn];
217 if (!kvm->arch.using_mmu_notifiers) {
218 physp = memslot->arch.slot_phys;
223 physp = real_vmalloc_addr(physp);
227 is_io = pa & (HPTE_R_I | HPTE_R_W);
228 pte_size = PAGE_SIZE << (pa & KVMPPC_PAGE_ORDER_MASK);
231 /* Translate to host virtual address */
232 hva = __gfn_to_hva_memslot(memslot, gfn);
234 /* Look up the Linux PTE for the backing page */
236 pte = lookup_linux_pte(pgdir, hva, writing, &pte_size);
237 if (pte_present(pte)) {
238 if (writing && !pte_write(pte))
239 /* make the actual HPTE be read-only */
240 ptel = hpte_make_readonly(ptel);
241 is_io = hpte_cache_bits(pte_val(pte));
242 pa = pte_pfn(pte) << PAGE_SHIFT;
246 if (pte_size < psize)
248 if (pa && pte_size > psize)
249 pa |= gpa & (pte_size - 1);
251 ptel &= ~(HPTE_R_PP0 - psize);
255 pteh |= HPTE_V_VALID;
257 pteh |= HPTE_V_ABSENT;
260 if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) {
264 * Allow guest to map emulated device memory as
265 * uncacheable, but actually make it cacheable.
267 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
271 /* Find and lock the HPTEG slot to use */
273 if (pte_index >= kvm->arch.hpt_npte)
275 if (likely((flags & H_EXACT) == 0)) {
277 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
278 for (i = 0; i < 8; ++i) {
279 if ((*hpte & HPTE_V_VALID) == 0 &&
280 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
287 * Since try_lock_hpte doesn't retry (not even stdcx.
288 * failures), it could be that there is a free slot
289 * but we transiently failed to lock it. Try again,
290 * actually locking each slot and checking it.
293 for (i = 0; i < 8; ++i) {
294 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
296 if (!(*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)))
298 *hpte &= ~HPTE_V_HVLOCK;
306 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
307 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
309 /* Lock the slot and check again */
310 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
312 if (*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
313 *hpte &= ~HPTE_V_HVLOCK;
319 /* Save away the guest's idea of the second HPTE dword */
320 rev = &kvm->arch.revmap[pte_index];
322 rev = real_vmalloc_addr(rev);
324 rev->guest_rpte = g_ptel;
325 note_hpte_modification(kvm, rev);
328 /* Link HPTE into reverse-map chain */
329 if (pteh & HPTE_V_VALID) {
331 rmap = real_vmalloc_addr(rmap);
333 /* Check for pending invalidations under the rmap chain lock */
334 if (kvm->arch.using_mmu_notifiers &&
335 mmu_notifier_retry(kvm, mmu_seq)) {
336 /* inval in progress, write a non-present HPTE */
337 pteh |= HPTE_V_ABSENT;
338 pteh &= ~HPTE_V_VALID;
341 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
343 /* Only set R/C in real HPTE if already set in *rmap */
344 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
345 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
351 /* Write the first HPTE dword, unlocking the HPTE and making it valid */
354 asm volatile("ptesync" : : : "memory");
356 *pte_idx_ret = pte_index;
359 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
361 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
362 long pte_index, unsigned long pteh, unsigned long ptel)
364 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
365 vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]);
368 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
370 static inline int try_lock_tlbie(unsigned int *lock)
372 unsigned int tmp, old;
373 unsigned int token = LOCK_TOKEN;
375 asm volatile("1:lwarx %1,0,%2\n"
382 : "=&r" (tmp), "=&r" (old)
383 : "r" (lock), "r" (token)
388 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
389 unsigned long pte_index, unsigned long avpn,
390 unsigned long *hpret)
393 unsigned long v, r, rb;
394 struct revmap_entry *rev;
396 if (pte_index >= kvm->arch.hpt_npte)
398 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
399 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
401 if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
402 ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
403 ((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
404 hpte[0] &= ~HPTE_V_HVLOCK;
408 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
409 v = hpte[0] & ~HPTE_V_HVLOCK;
410 if (v & HPTE_V_VALID) {
411 hpte[0] &= ~HPTE_V_VALID;
412 rb = compute_tlbie_rb(v, hpte[1], pte_index);
413 if (global_invalidates(kvm, flags)) {
414 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
416 asm volatile("ptesync" : : : "memory");
417 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
418 : : "r" (rb), "r" (kvm->arch.lpid));
419 asm volatile("ptesync" : : : "memory");
420 kvm->arch.tlbie_lock = 0;
422 asm volatile("ptesync" : : : "memory");
423 asm volatile("tlbiel %0" : : "r" (rb));
424 asm volatile("ptesync" : : : "memory");
426 /* Read PTE low word after tlbie to get final R/C values */
427 remove_revmap_chain(kvm, pte_index, rev, v, hpte[1]);
429 r = rev->guest_rpte & ~HPTE_GR_RESERVED;
430 note_hpte_modification(kvm, rev);
431 unlock_hpte(hpte, 0);
437 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
439 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
440 unsigned long pte_index, unsigned long avpn)
442 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
446 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
448 struct kvm *kvm = vcpu->kvm;
449 unsigned long *args = &vcpu->arch.gpr[4];
450 unsigned long *hp, *hptes[4], tlbrb[4];
451 long int i, j, k, n, found, indexes[4];
452 unsigned long flags, req, pte_index, rcbits;
454 long int ret = H_SUCCESS;
455 struct revmap_entry *rev, *revs[4];
457 if (atomic_read(&kvm->online_vcpus) == 1)
459 for (i = 0; i < 4 && ret == H_SUCCESS; ) {
464 flags = pte_index >> 56;
465 pte_index &= ((1ul << 56) - 1);
468 if (req == 3) { /* no more requests */
472 if (req != 1 || flags == 3 ||
473 pte_index >= kvm->arch.hpt_npte) {
474 /* parameter error */
475 args[j] = ((0xa0 | flags) << 56) + pte_index;
479 hp = (unsigned long *)
480 (kvm->arch.hpt_virt + (pte_index << 4));
481 /* to avoid deadlock, don't spin except for first */
482 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
485 while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
489 if (hp[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) {
491 case 0: /* absolute */
494 case 1: /* andcond */
495 if (!(hp[0] & args[j + 1]))
499 if ((hp[0] & ~0x7fUL) == args[j + 1])
505 hp[0] &= ~HPTE_V_HVLOCK;
506 args[j] = ((0x90 | flags) << 56) + pte_index;
510 args[j] = ((0x80 | flags) << 56) + pte_index;
511 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
512 note_hpte_modification(kvm, rev);
514 if (!(hp[0] & HPTE_V_VALID)) {
515 /* insert R and C bits from PTE */
516 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
517 args[j] |= rcbits << (56 - 5);
522 hp[0] &= ~HPTE_V_VALID; /* leave it locked */
523 tlbrb[n] = compute_tlbie_rb(hp[0], hp[1], pte_index);
533 /* Now that we've collected a batch, do the tlbies */
535 while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
537 asm volatile("ptesync" : : : "memory");
538 for (k = 0; k < n; ++k)
539 asm volatile(PPC_TLBIE(%1,%0) : :
541 "r" (kvm->arch.lpid));
542 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
543 kvm->arch.tlbie_lock = 0;
545 asm volatile("ptesync" : : : "memory");
546 for (k = 0; k < n; ++k)
547 asm volatile("tlbiel %0" : : "r" (tlbrb[k]));
548 asm volatile("ptesync" : : : "memory");
551 /* Read PTE low words after tlbie to get final R/C values */
552 for (k = 0; k < n; ++k) {
554 pte_index = args[j] & ((1ul << 56) - 1);
557 remove_revmap_chain(kvm, pte_index, rev, hp[0], hp[1]);
558 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
559 args[j] |= rcbits << (56 - 5);
567 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
568 unsigned long pte_index, unsigned long avpn,
571 struct kvm *kvm = vcpu->kvm;
573 struct revmap_entry *rev;
574 unsigned long v, r, rb, mask, bits;
576 if (pte_index >= kvm->arch.hpt_npte)
579 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
580 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
582 if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
583 ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
584 hpte[0] &= ~HPTE_V_HVLOCK;
589 bits = (flags << 55) & HPTE_R_PP0;
590 bits |= (flags << 48) & HPTE_R_KEY_HI;
591 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
593 /* Update guest view of 2nd HPTE dword */
594 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
595 HPTE_R_KEY_HI | HPTE_R_KEY_LO;
596 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
598 r = (rev->guest_rpte & ~mask) | bits;
600 note_hpte_modification(kvm, rev);
602 r = (hpte[1] & ~mask) | bits;
605 if (v & HPTE_V_VALID) {
606 rb = compute_tlbie_rb(v, r, pte_index);
607 hpte[0] = v & ~HPTE_V_VALID;
608 if (global_invalidates(kvm, flags)) {
609 while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
611 asm volatile("ptesync" : : : "memory");
612 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
613 : : "r" (rb), "r" (kvm->arch.lpid));
614 asm volatile("ptesync" : : : "memory");
615 kvm->arch.tlbie_lock = 0;
617 asm volatile("ptesync" : : : "memory");
618 asm volatile("tlbiel %0" : : "r" (rb));
619 asm volatile("ptesync" : : : "memory");
622 * If the host has this page as readonly but the guest
623 * wants to make it read/write, reduce the permissions.
624 * Checking the host permissions involves finding the
625 * memslot and then the Linux PTE for the page.
627 if (hpte_is_writable(r) && kvm->arch.using_mmu_notifiers) {
628 unsigned long psize, gfn, hva;
629 struct kvm_memory_slot *memslot;
630 pgd_t *pgdir = vcpu->arch.pgdir;
633 psize = hpte_page_size(v, r);
634 gfn = ((r & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
635 memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
637 hva = __gfn_to_hva_memslot(memslot, gfn);
638 pte = lookup_linux_pte(pgdir, hva, 1, &psize);
639 if (pte_present(pte) && !pte_write(pte))
640 r = hpte_make_readonly(r);
646 hpte[0] = v & ~HPTE_V_HVLOCK;
647 asm volatile("ptesync" : : : "memory");
651 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
652 unsigned long pte_index)
654 struct kvm *kvm = vcpu->kvm;
655 unsigned long *hpte, v, r;
657 struct revmap_entry *rev = NULL;
659 if (pte_index >= kvm->arch.hpt_npte)
661 if (flags & H_READ_4) {
665 rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
666 for (i = 0; i < n; ++i, ++pte_index) {
667 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
668 v = hpte[0] & ~HPTE_V_HVLOCK;
670 if (v & HPTE_V_ABSENT) {
674 if (v & HPTE_V_VALID) {
675 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
676 r &= ~HPTE_GR_RESERVED;
678 vcpu->arch.gpr[4 + i * 2] = v;
679 vcpu->arch.gpr[5 + i * 2] = r;
684 void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
685 unsigned long pte_index)
689 hptep[0] &= ~HPTE_V_VALID;
690 rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
691 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
693 asm volatile("ptesync" : : : "memory");
694 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
695 : : "r" (rb), "r" (kvm->arch.lpid));
696 asm volatile("ptesync" : : : "memory");
697 kvm->arch.tlbie_lock = 0;
699 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
701 void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
702 unsigned long pte_index)
707 rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
708 rbyte = (hptep[1] & ~HPTE_R_R) >> 8;
709 /* modify only the second-last byte, which contains the ref bit */
710 *((char *)hptep + 14) = rbyte;
711 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
713 asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
714 : : "r" (rb), "r" (kvm->arch.lpid));
715 asm volatile("ptesync" : : : "memory");
716 kvm->arch.tlbie_lock = 0;
718 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
720 static int slb_base_page_shift[4] = {
724 20, /* 1M, unsupported */
727 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
732 unsigned long somask;
733 unsigned long vsid, hash;
736 unsigned long mask, val;
739 /* Get page shift, work out hash and AVPN etc. */
740 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
743 if (slb_v & SLB_VSID_L) {
744 mask |= HPTE_V_LARGE;
746 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
748 if (slb_v & SLB_VSID_B_1T) {
749 somask = (1UL << 40) - 1;
750 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
753 somask = (1UL << 28) - 1;
754 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
756 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvm->arch.hpt_mask;
757 avpn = slb_v & ~(somask >> 16); /* also includes B */
758 avpn |= (eaddr & somask) >> 16;
761 avpn &= ~((1UL << (pshift - 16)) - 1);
767 hpte = (unsigned long *)(kvm->arch.hpt_virt + (hash << 7));
769 for (i = 0; i < 16; i += 2) {
770 /* Read the PTE racily */
771 v = hpte[i] & ~HPTE_V_HVLOCK;
773 /* Check valid/absent, hash, segment size and AVPN */
774 if (!(v & valid) || (v & mask) != val)
777 /* Lock the PTE and read it under the lock */
778 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
780 v = hpte[i] & ~HPTE_V_HVLOCK;
784 * Check the HPTE again, including large page size
785 * Since we don't currently allow any MPSS (mixed
786 * page-size segment) page sizes, it is sufficient
787 * to check against the actual page size.
789 if ((v & valid) && (v & mask) == val &&
790 hpte_page_size(v, r) == (1ul << pshift))
791 /* Return with the HPTE still locked */
792 return (hash << 3) + (i >> 1);
794 /* Unlock and move on */
798 if (val & HPTE_V_SECONDARY)
800 val |= HPTE_V_SECONDARY;
801 hash = hash ^ kvm->arch.hpt_mask;
805 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
808 * Called in real mode to check whether an HPTE not found fault
809 * is due to accessing a paged-out page or an emulated MMIO page,
810 * or if a protection fault is due to accessing a page that the
811 * guest wanted read/write access to but which we made read-only.
812 * Returns a possibly modified status (DSISR) value if not
813 * (i.e. pass the interrupt to the guest),
814 * -1 to pass the fault up to host kernel mode code, -2 to do that
815 * and also load the instruction word (for MMIO emulation),
816 * or 0 if we should make the guest retry the access.
818 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
819 unsigned long slb_v, unsigned int status, bool data)
821 struct kvm *kvm = vcpu->kvm;
823 unsigned long v, r, gr;
826 struct revmap_entry *rev;
827 unsigned long pp, key;
829 /* For protection fault, expect to find a valid HPTE */
830 valid = HPTE_V_VALID;
831 if (status & DSISR_NOHPTE)
832 valid |= HPTE_V_ABSENT;
834 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
836 if (status & DSISR_NOHPTE)
837 return status; /* there really was no HPTE */
838 return 0; /* for prot fault, HPTE disappeared */
840 hpte = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
841 v = hpte[0] & ~HPTE_V_HVLOCK;
843 rev = real_vmalloc_addr(&kvm->arch.revmap[index]);
844 gr = rev->guest_rpte;
846 unlock_hpte(hpte, v);
848 /* For not found, if the HPTE is valid by now, retry the instruction */
849 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
852 /* Check access permissions to the page */
853 pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
854 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
855 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
857 if (gr & (HPTE_R_N | HPTE_R_G))
858 return status | SRR1_ISI_N_OR_G;
859 if (!hpte_read_permission(pp, slb_v & key))
860 return status | SRR1_ISI_PROT;
861 } else if (status & DSISR_ISSTORE) {
862 /* check write permission */
863 if (!hpte_write_permission(pp, slb_v & key))
864 return status | DSISR_PROTFAULT;
866 if (!hpte_read_permission(pp, slb_v & key))
867 return status | DSISR_PROTFAULT;
870 /* Check storage key, if applicable */
871 if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
872 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
873 if (status & DSISR_ISSTORE)
876 return status | DSISR_KEYFAULT;
879 /* Save HPTE info for virtual-mode handler */
880 vcpu->arch.pgfault_addr = addr;
881 vcpu->arch.pgfault_index = index;
882 vcpu->arch.pgfault_hpte[0] = v;
883 vcpu->arch.pgfault_hpte[1] = r;
885 /* Check the storage key to see if it is possibly emulated MMIO */
886 if (data && (vcpu->arch.shregs.msr & MSR_IR) &&
887 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
888 (HPTE_R_KEY_HI | HPTE_R_KEY_LO))
889 return -2; /* MMIO emulation - load instr word */
891 return -1; /* send fault up to host kernel mode */