2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
34 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
36 /* Values in HSTATE_NAPPING(r13) */
37 #define NAPPING_CEDE 1
38 #define NAPPING_NOVCPU 2
41 * Call kvmppc_hv_entry in real mode.
42 * Must be called with interrupts hard-disabled.
46 * LR = return address to continue at after eventually re-enabling MMU
48 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
50 std r0, PPC_LR_STKOFF(r1)
53 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
58 mtmsrd r0,1 /* clear RI in MSR */
64 ld r4, HSTATE_KVM_VCPU(r13)
67 /* Back from guest - restore host state and return to caller */
70 /* Restore host DABR and DABRX */
71 ld r5,HSTATE_DABR(r13)
75 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
78 ld r3,PACA_SPRG_VDSO(r13)
79 mtspr SPRN_SPRG_VDSO_WRITE,r3
81 /* Reload the host's PMU registers */
82 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
83 lbz r4, LPPACA_PMCINUSE(r3)
85 beq 23f /* skip if not */
87 ld r3, HSTATE_MMCR0(r13)
88 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
91 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
92 lwz r3, HSTATE_PMC1(r13)
93 lwz r4, HSTATE_PMC2(r13)
94 lwz r5, HSTATE_PMC3(r13)
95 lwz r6, HSTATE_PMC4(r13)
96 lwz r8, HSTATE_PMC5(r13)
97 lwz r9, HSTATE_PMC6(r13)
104 ld r3, HSTATE_MMCR0(r13)
105 ld r4, HSTATE_MMCR1(r13)
106 ld r5, HSTATE_MMCRA(r13)
107 ld r6, HSTATE_SIAR(r13)
108 ld r7, HSTATE_SDAR(r13)
114 ld r8, HSTATE_MMCR2(r13)
115 ld r9, HSTATE_SIER(r13)
118 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
124 * Reload DEC. HDEC interrupts were disabled when
125 * we reloaded the host's LPCR value.
127 ld r3, HSTATE_DECEXP(r13)
132 /* hwthread_req may have got set by cede or no vcpu, so clear it */
134 stb r0, HSTATE_HWTHREAD_REQ(r13)
137 * For external and machine check interrupts, we need
138 * to call the Linux handler to process the interrupt.
139 * We do that by jumping to absolute address 0x500 for
140 * external interrupts, or the machine_check_fwnmi label
141 * for machine checks (since firmware might have patched
142 * the vector area at 0x200). The [h]rfid at the end of the
143 * handler will return to the book3s_hv_interrupts.S code.
144 * For other interrupts we do the rfid to get back
145 * to the book3s_hv_interrupts.S code here.
147 ld r8, 112+PPC_LR_STKOFF(r1)
149 ld r7, HSTATE_HOST_MSR(r13)
151 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
152 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
154 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
155 beq 15f /* Invoke the H_DOORBELL handler */
156 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
157 beq cr2, 14f /* HMI check */
159 /* RFI into the highmem handler, or branch to interrupt handler */
163 mtmsrd r6, 1 /* Clear RI in MSR */
166 beq cr1, 13f /* machine check */
169 /* On POWER7, we have external interrupts set to use HSRR0/1 */
170 11: mtspr SPRN_HSRR0, r8
174 13: b machine_check_fwnmi
176 14: mtspr SPRN_HSRR0, r8
178 b hmi_exception_after_realmode
180 15: mtspr SPRN_HSRR0, r8
184 kvmppc_primary_no_guest:
185 /* We handle this much like a ceded vcpu */
186 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
190 * Make sure the primary has finished the MMU switch.
191 * We should never get here on a secondary thread, but
192 * check it for robustness' sake.
194 ld r5, HSTATE_KVM_VCORE(r13)
195 65: lbz r0, VCORE_IN_GUEST(r5)
202 /* set our bit in napping_threads */
203 ld r5, HSTATE_KVM_VCORE(r13)
204 lbz r7, HSTATE_PTID(r13)
207 addi r6, r5, VCORE_NAPPING_THREADS
212 /* order napping_threads update vs testing entry_exit_map */
215 lwz r7, VCORE_ENTRY_EXIT(r5)
217 bge kvm_novcpu_exit /* another thread already exiting */
218 li r3, NAPPING_NOVCPU
219 stb r3, HSTATE_NAPPING(r13)
221 li r3, 0 /* Don't wake on privileged (OS) doorbell */
225 ld r1, HSTATE_HOST_R1(r13)
226 ld r5, HSTATE_KVM_VCORE(r13)
228 stb r0, HSTATE_NAPPING(r13)
230 /* check the wake reason */
231 bl kvmppc_check_wake_reason
233 /* see if any other thread is already exiting */
234 lwz r0, VCORE_ENTRY_EXIT(r5)
238 /* clear our bit in napping_threads */
239 lbz r7, HSTATE_PTID(r13)
242 addi r6, r5, VCORE_NAPPING_THREADS
248 /* See if the wake reason means we need to exit */
252 /* See if our timeslice has expired (HDEC is negative) */
254 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
258 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
259 ld r4, HSTATE_KVM_VCPU(r13)
261 beq kvmppc_primary_no_guest
263 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
264 addi r3, r4, VCPU_TB_RMENTRY
265 bl kvmhv_start_timing
270 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
271 ld r4, HSTATE_KVM_VCPU(r13)
274 addi r3, r4, VCPU_TB_RMEXIT
275 bl kvmhv_accumulate_time
279 bl kvmhv_commence_exit
282 b kvmhv_switch_to_host
285 * We come in here when wakened from nap mode.
286 * Relocation is off and most register values are lost.
287 * r13 points to the PACA.
289 .globl kvm_start_guest
292 /* Set runlatch bit the minute you wake up from nap */
299 li r0,KVM_HWTHREAD_IN_KVM
300 stb r0,HSTATE_HWTHREAD_STATE(r13)
302 /* NV GPR values from power7_idle() will no longer be valid */
304 stb r0,PACA_NAPSTATELOST(r13)
306 /* were we napping due to cede? */
307 lbz r0,HSTATE_NAPPING(r13)
308 cmpwi r0,NAPPING_CEDE
310 cmpwi r0,NAPPING_NOVCPU
311 beq kvm_novcpu_wakeup
313 ld r1,PACAEMERGSP(r13)
314 subi r1,r1,STACK_FRAME_OVERHEAD
317 * We weren't napping due to cede, so this must be a secondary
318 * thread being woken up to run a guest, or being woken up due
319 * to a stray IPI. (Or due to some machine check or hypervisor
320 * maintenance interrupt while the core is in KVM.)
323 /* Check the wake reason in SRR1 to see why we got here */
324 bl kvmppc_check_wake_reason
328 /* get vcore pointer, NULL if we have nothing to run */
329 ld r5,HSTATE_KVM_VCORE(r13)
331 /* if we have no vcore to run, go back to sleep */
334 kvm_secondary_got_guest:
336 /* Set HSTATE_DSCR(r13) to something sensible */
337 ld r6, PACA_DSCR_DEFAULT(r13)
338 std r6, HSTATE_DSCR(r13)
340 /* On thread 0 of a subcore, set HDEC to max */
341 lbz r4, HSTATE_PTID(r13)
347 /* and set per-LPAR registers, if doing dynamic micro-threading */
348 ld r6, HSTATE_SPLIT_MODE(r13)
351 ld r0, KVM_SPLIT_RPR(r6)
353 ld r0, KVM_SPLIT_PMMAR(r6)
355 ld r0, KVM_SPLIT_LDBAR(r6)
359 /* Order load of vcpu after load of vcore */
361 ld r4, HSTATE_KVM_VCPU(r13)
364 /* Back from the guest, go back to nap */
365 /* Clear our vcpu and vcore pointers so we don't come back in early */
367 std r0, HSTATE_KVM_VCPU(r13)
369 * Once we clear HSTATE_KVM_VCORE(r13), the code in
370 * kvmppc_run_core() is going to assume that all our vcpu
371 * state is visible in memory. This lwsync makes sure
375 std r0, HSTATE_KVM_VCORE(r13)
378 * All secondaries exiting guest will fall through this path.
379 * Before proceeding, just check for HMI interrupt and
380 * invoke opal hmi handler. By now we are sure that the
381 * primary thread on this core/subcore has already made partition
382 * switch/TB resync and we are good to call opal hmi handler.
384 cmpwi r12, BOOK3S_INTERRUPT_HMI
387 li r3,0 /* NULL argument */
388 bl hmi_exception_realmode
390 * At this point we have finished executing in the guest.
391 * We need to wait for hwthread_req to become zero, since
392 * we may not turn on the MMU while hwthread_req is non-zero.
393 * While waiting we also need to check if we get given a vcpu to run.
396 lbz r3, HSTATE_HWTHREAD_REQ(r13)
400 li r0, KVM_HWTHREAD_IN_KERNEL
401 stb r0, HSTATE_HWTHREAD_STATE(r13)
402 /* need to recheck hwthread_req after a barrier, to avoid race */
404 lbz r3, HSTATE_HWTHREAD_REQ(r13)
408 * We jump to pnv_wakeup_loss, which will return to the caller
409 * of power7_nap in the powernv cpu offline loop. The value we
410 * put in r3 becomes the return value for power7_nap.
414 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
420 ld r5, HSTATE_KVM_VCORE(r13)
423 ld r3, HSTATE_SPLIT_MODE(r13)
426 lbz r0, KVM_SPLIT_DO_NAP(r3)
432 b kvm_secondary_got_guest
434 54: li r0, KVM_HWTHREAD_IN_KVM
435 stb r0, HSTATE_HWTHREAD_STATE(r13)
439 * Here the primary thread is trying to return the core to
440 * whole-core mode, so we need to nap.
444 * When secondaries are napping in kvm_unsplit_nap() with
445 * hwthread_req = 1, HMI goes ignored even though subcores are
446 * already exited the guest. Hence HMI keeps waking up secondaries
447 * from nap in a loop and secondaries always go back to nap since
448 * no vcore is assigned to them. This makes impossible for primary
449 * thread to get hold of secondary threads resulting into a soft
450 * lockup in KVM path.
452 * Let us check if HMI is pending and handle it before we go to nap.
454 cmpwi r12, BOOK3S_INTERRUPT_HMI
456 li r3, 0 /* NULL argument */
457 bl hmi_exception_realmode
460 * Ensure that secondary doesn't nap when it has
461 * its vcore pointer set.
463 sync /* matches smp_mb() before setting split_info.do_nap */
464 ld r0, HSTATE_KVM_VCORE(r13)
467 /* clear any pending message */
469 lis r6, (PPC_DBELL_SERVER << (63-36))@h
471 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
472 /* Set kvm_split_mode.napped[tid] = 1 */
473 ld r3, HSTATE_SPLIT_MODE(r13)
475 lhz r4, PACAPACAINDEX(r13)
476 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
477 addi r4, r4, KVM_SPLIT_NAPPED
479 /* Check the do_nap flag again after setting napped[] */
481 lbz r0, KVM_SPLIT_DO_NAP(r3)
484 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
486 rlwimi r4, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
489 std r0, HSTATE_SCRATCH0(r13)
491 ld r0, HSTATE_SCRATCH0(r13)
501 /******************************************************************************
505 *****************************************************************************/
507 .global kvmppc_hv_entry
512 * R4 = vcpu pointer (or NULL)
517 * all other volatile GPRS = free
520 std r0, PPC_LR_STKOFF(r1)
523 /* Save R1 in the PACA */
524 std r1, HSTATE_HOST_R1(r13)
526 li r6, KVM_GUEST_MODE_HOST_HV
527 stb r6, HSTATE_IN_GUEST(r13)
529 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
530 /* Store initial timestamp */
533 addi r3, r4, VCPU_TB_RMENTRY
534 bl kvmhv_start_timing
544 * POWER7/POWER8 host -> guest partition switch code.
545 * We don't have to lock against concurrent tlbies,
546 * but we do have to coordinate across hardware threads.
548 /* Set bit in entry map iff exit map is zero. */
549 ld r5, HSTATE_KVM_VCORE(r13)
551 lbz r6, HSTATE_PTID(r13)
553 addi r9, r5, VCORE_ENTRY_EXIT
555 cmpwi r3, 0x100 /* any threads starting to exit? */
556 bge secondary_too_late /* if so we're too late to the party */
561 /* Primary thread switches to guest partition. */
562 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
567 li r0,LPID_RSVD /* switch to reserved LPID */
570 mtspr SPRN_SDR1,r6 /* switch to partition page table */
574 /* See if we need to flush the TLB */
575 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
576 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
577 srdi r6,r6,6 /* doubleword number */
578 sldi r6,r6,3 /* address offset */
580 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
586 23: ldarx r7,0,r6 /* if set, clear the bit */
590 /* Flush the TLB of any entries for this LPID */
591 /* use arch 2.07S as a proxy for POWER8 */
593 li r6,512 /* POWER8 has 512 sets */
595 li r6,128 /* POWER7 has 128 sets */
596 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
598 li r7,0x800 /* IS field = 0b10 */
605 /* Add timebase offset onto timebase */
606 22: ld r8,VCORE_TB_OFFSET(r5)
609 mftb r6 /* current host timebase */
611 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
612 mftb r7 /* check if lower 24 bits overflowed */
617 addis r8,r8,0x100 /* if so, increment upper 40 bits */
620 /* Load guest PCR value to select appropriate compat mode */
621 37: ld r7, VCORE_PCR(r5)
628 /* DPDES is shared between threads */
629 ld r8, VCORE_DPDES(r5)
631 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
633 /* Mark the subcore state as inside guest */
634 bl kvmppc_subcore_enter_guest
636 ld r5, HSTATE_KVM_VCORE(r13)
637 ld r4, HSTATE_KVM_VCPU(r13)
639 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
641 /* Do we have a guest vcpu to run? */
643 beq kvmppc_primary_no_guest
646 /* Load up guest SLB entries */
647 lwz r5,VCPU_SLB_MAX(r4)
652 1: ld r8,VCPU_SLB_E(r6)
655 addi r6,r6,VCPU_SLB_SIZE
658 /* Increment yield count if they have a VPA */
662 li r6, LPPACA_YIELDCOUNT
667 stb r6, VCPU_VPA_DIRTY(r4)
670 /* Save purr/spurr */
673 std r5,HSTATE_PURR(r13)
674 std r6,HSTATE_SPURR(r13)
681 /* Set partition DABR */
682 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
683 lwz r5,VCPU_DABRX(r4)
688 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
690 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
693 END_FTR_SECTION_IFSET(CPU_FTR_TM)
696 /* Load guest PMU registers */
697 /* R4 is live here (vcpu pointer) */
699 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
700 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
704 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
707 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
708 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
709 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
710 lwz r6, VCPU_PMC + 8(r4)
711 lwz r7, VCPU_PMC + 12(r4)
712 lwz r8, VCPU_PMC + 16(r4)
713 lwz r9, VCPU_PMC + 20(r4)
721 ld r5, VCPU_MMCR + 8(r4)
722 ld r6, VCPU_MMCR + 16(r4)
730 ld r5, VCPU_MMCR + 24(r4)
732 lwz r7, VCPU_PMC + 24(r4)
733 lwz r8, VCPU_PMC + 28(r4)
734 ld r9, VCPU_MMCR + 32(r4)
740 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
744 /* Load up FP, VMX and VSX registers */
747 ld r14, VCPU_GPR(R14)(r4)
748 ld r15, VCPU_GPR(R15)(r4)
749 ld r16, VCPU_GPR(R16)(r4)
750 ld r17, VCPU_GPR(R17)(r4)
751 ld r18, VCPU_GPR(R18)(r4)
752 ld r19, VCPU_GPR(R19)(r4)
753 ld r20, VCPU_GPR(R20)(r4)
754 ld r21, VCPU_GPR(R21)(r4)
755 ld r22, VCPU_GPR(R22)(r4)
756 ld r23, VCPU_GPR(R23)(r4)
757 ld r24, VCPU_GPR(R24)(r4)
758 ld r25, VCPU_GPR(R25)(r4)
759 ld r26, VCPU_GPR(R26)(r4)
760 ld r27, VCPU_GPR(R27)(r4)
761 ld r28, VCPU_GPR(R28)(r4)
762 ld r29, VCPU_GPR(R29)(r4)
763 ld r30, VCPU_GPR(R30)(r4)
764 ld r31, VCPU_GPR(R31)(r4)
766 /* Switch DSCR to guest value */
771 /* Skip next section on POWER7 */
773 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
774 /* Load up POWER8-specific registers */
776 lwz r6, VCPU_PSPB(r4)
782 ld r6, VCPU_DAWRX(r4)
783 ld r7, VCPU_CIABR(r4)
793 ld r8, VCPU_EBBHR(r4)
795 ld r5, VCPU_EBBRR(r4)
796 ld r6, VCPU_BESCR(r4)
797 ld r7, VCPU_CSIGR(r4)
803 ld r5, VCPU_TCSCR(r4)
805 lwz r7, VCPU_GUEST_PID(r4)
814 * Set the decrementer to the guest decrementer.
816 ld r8,VCPU_DEC_EXPIRES(r4)
817 /* r8 is a host timebase value here, convert to guest TB */
818 ld r5,HSTATE_KVM_VCORE(r13)
819 ld r6,VCORE_TB_OFFSET(r5)
826 ld r5, VCPU_SPRG0(r4)
827 ld r6, VCPU_SPRG1(r4)
828 ld r7, VCPU_SPRG2(r4)
829 ld r8, VCPU_SPRG3(r4)
835 /* Load up DAR and DSISR */
837 lwz r6, VCPU_DSISR(r4)
841 /* Restore AMR and UAMOR, set AMOR to all 1s */
849 /* Restore state of CTRL run bit; assume 1 on entry */
857 /* Secondary threads wait for primary to have done partition switch */
858 ld r5, HSTATE_KVM_VCORE(r13)
859 lbz r6, HSTATE_PTID(r13)
862 lbz r0, VCORE_IN_GUEST(r5)
866 20: lwz r3, VCORE_ENTRY_EXIT(r5)
869 lbz r0, VCORE_IN_GUEST(r5)
879 /* Check if HDEC expires soon */
881 cmpwi r3, 512 /* 1 microsecond */
890 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
898 deliver_guest_interrupt:
899 /* r11 = vcpu->arch.msr & ~MSR_HV */
900 rldicl r11, r11, 63 - MSR_HV_LG, 1
901 rotldi r11, r11, 1 + MSR_HV_LG
904 /* Check if we can deliver an external or decrementer interrupt now */
905 ld r0, VCPU_PENDING_EXC(r4)
906 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
908 andi. r8, r11, MSR_EE
910 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
911 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
915 li r0, BOOK3S_INTERRUPT_EXTERNAL
919 li r0, BOOK3S_INTERRUPT_DECREMENTER
922 12: mtspr SPRN_SRR0, r10
926 bl kvmppc_msr_interrupt
932 * R10: value for HSRR0
933 * R11: value for HSRR1
938 stb r0,VCPU_CEDED(r4) /* cancel cede */
942 /* Activate guest mode, so faults get handled by KVM */
943 li r9, KVM_GUEST_MODE_GUEST_HV
944 stb r9, HSTATE_IN_GUEST(r13)
946 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
947 /* Accumulate timing */
948 addi r3, r4, VCPU_TB_GUEST
949 bl kvmhv_accumulate_time
957 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
960 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
967 ld r1, VCPU_GPR(R1)(r4)
968 ld r2, VCPU_GPR(R2)(r4)
969 ld r3, VCPU_GPR(R3)(r4)
970 ld r5, VCPU_GPR(R5)(r4)
971 ld r6, VCPU_GPR(R6)(r4)
972 ld r7, VCPU_GPR(R7)(r4)
973 ld r8, VCPU_GPR(R8)(r4)
974 ld r9, VCPU_GPR(R9)(r4)
975 ld r10, VCPU_GPR(R10)(r4)
976 ld r11, VCPU_GPR(R11)(r4)
977 ld r12, VCPU_GPR(R12)(r4)
978 ld r13, VCPU_GPR(R13)(r4)
982 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
983 ld r0, VCPU_GPR(R0)(r4)
984 ld r4, VCPU_GPR(R4)(r4)
993 stw r12, VCPU_TRAP(r4)
994 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
995 addi r3, r4, VCPU_TB_RMEXIT
996 bl kvmhv_accumulate_time
998 11: b kvmhv_switch_to_host
1005 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1006 12: stw r12, VCPU_TRAP(r4)
1008 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1009 addi r3, r4, VCPU_TB_RMEXIT
1010 bl kvmhv_accumulate_time
1014 /******************************************************************************
1018 *****************************************************************************/
1021 * We come here from the first-level interrupt handlers.
1023 .globl kvmppc_interrupt_hv
1024 kvmppc_interrupt_hv:
1026 * Register contents:
1027 * R12 = interrupt vector
1029 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1030 * guest R13 saved in SPRN_SCRATCH0
1032 std r9, HSTATE_SCRATCH2(r13)
1034 lbz r9, HSTATE_IN_GUEST(r13)
1035 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1036 beq kvmppc_bad_host_intr
1037 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1038 cmpwi r9, KVM_GUEST_MODE_GUEST
1039 ld r9, HSTATE_SCRATCH2(r13)
1040 beq kvmppc_interrupt_pr
1042 /* We're now back in the host but in guest MMU context */
1043 li r9, KVM_GUEST_MODE_HOST_HV
1044 stb r9, HSTATE_IN_GUEST(r13)
1046 ld r9, HSTATE_KVM_VCPU(r13)
1048 /* Save registers */
1050 std r0, VCPU_GPR(R0)(r9)
1051 std r1, VCPU_GPR(R1)(r9)
1052 std r2, VCPU_GPR(R2)(r9)
1053 std r3, VCPU_GPR(R3)(r9)
1054 std r4, VCPU_GPR(R4)(r9)
1055 std r5, VCPU_GPR(R5)(r9)
1056 std r6, VCPU_GPR(R6)(r9)
1057 std r7, VCPU_GPR(R7)(r9)
1058 std r8, VCPU_GPR(R8)(r9)
1059 ld r0, HSTATE_SCRATCH2(r13)
1060 std r0, VCPU_GPR(R9)(r9)
1061 std r10, VCPU_GPR(R10)(r9)
1062 std r11, VCPU_GPR(R11)(r9)
1063 ld r3, HSTATE_SCRATCH0(r13)
1064 lwz r4, HSTATE_SCRATCH1(r13)
1065 std r3, VCPU_GPR(R12)(r9)
1068 ld r3, HSTATE_CFAR(r13)
1069 std r3, VCPU_CFAR(r9)
1070 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1072 ld r4, HSTATE_PPR(r13)
1073 std r4, VCPU_PPR(r9)
1074 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1076 /* Restore R1/R2 so we can handle faults */
1077 ld r1, HSTATE_HOST_R1(r13)
1080 mfspr r10, SPRN_SRR0
1081 mfspr r11, SPRN_SRR1
1082 std r10, VCPU_SRR0(r9)
1083 std r11, VCPU_SRR1(r9)
1084 andi. r0, r12, 2 /* need to read HSRR0/1? */
1086 mfspr r10, SPRN_HSRR0
1087 mfspr r11, SPRN_HSRR1
1089 1: std r10, VCPU_PC(r9)
1090 std r11, VCPU_MSR(r9)
1094 std r3, VCPU_GPR(R13)(r9)
1097 stw r12,VCPU_TRAP(r9)
1099 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1100 addi r3, r9, VCPU_TB_RMINTR
1102 bl kvmhv_accumulate_time
1103 ld r5, VCPU_GPR(R5)(r9)
1104 ld r6, VCPU_GPR(R6)(r9)
1105 ld r7, VCPU_GPR(R7)(r9)
1106 ld r8, VCPU_GPR(R8)(r9)
1109 /* Save HEIR (HV emulation assist reg) in emul_inst
1110 if this is an HEI (HV emulation interrupt, e40) */
1111 li r3,KVM_INST_FETCH_FAILED
1112 stw r3,VCPU_LAST_INST(r9)
1113 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1116 11: stw r3,VCPU_HEIR(r9)
1118 /* these are volatile across C function calls */
1121 std r3, VCPU_CTR(r9)
1122 std r4, VCPU_XER(r9)
1124 /* If this is a page table miss then see if it's theirs or ours */
1125 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1127 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1130 /* See if this is a leftover HDEC interrupt */
1131 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1136 bge fast_guest_return
1138 /* See if this is an hcall we can handle in real mode */
1139 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1140 beq hcall_try_real_mode
1142 /* Hypervisor doorbell - exit only if host IPI flag set */
1143 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1145 lbz r0, HSTATE_HOST_IPI(r13)
1150 /* External interrupt ? */
1151 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1152 bne+ guest_exit_cont
1154 /* External interrupt, first check for host_ipi. If this is
1155 * set, we know the host wants us out so let's do it now
1161 /* Check if any CPU is heading out to the host, if so head out too */
1162 4: ld r5, HSTATE_KVM_VCORE(r13)
1163 lwz r0, VCORE_ENTRY_EXIT(r5)
1166 blt deliver_guest_interrupt
1168 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1169 /* Save more register state */
1172 std r6, VCPU_DAR(r9)
1173 stw r7, VCPU_DSISR(r9)
1174 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1175 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1177 std r6, VCPU_FAULT_DAR(r9)
1178 stw r7, VCPU_FAULT_DSISR(r9)
1180 /* See if it is a machine check */
1181 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1182 beq machine_check_realmode
1184 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1185 addi r3, r9, VCPU_TB_RMEXIT
1187 bl kvmhv_accumulate_time
1191 /* Increment exit count, poke other threads to exit */
1192 bl kvmhv_commence_exit
1194 ld r9, HSTATE_KVM_VCPU(r13)
1195 lwz r12, VCPU_TRAP(r9)
1197 /* Stop others sending VCPU interrupts to this physical CPU */
1199 stw r0, VCPU_CPU(r9)
1200 stw r0, VCPU_THREAD_CPU(r9)
1202 /* Save guest CTRL register, set runlatch to 1 */
1204 stw r6,VCPU_CTRL(r9)
1210 /* Read the guest SLB and save it away */
1211 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1217 andis. r0,r8,SLB_ESID_V@h
1219 add r8,r8,r6 /* put index in */
1221 std r8,VCPU_SLB_E(r7)
1222 std r3,VCPU_SLB_V(r7)
1223 addi r7,r7,VCPU_SLB_SIZE
1227 stw r5,VCPU_SLB_MAX(r9)
1230 * Save the guest PURR/SPURR
1235 ld r8,VCPU_SPURR(r9)
1236 std r5,VCPU_PURR(r9)
1237 std r6,VCPU_SPURR(r9)
1242 * Restore host PURR/SPURR and add guest times
1243 * so that the time in the guest gets accounted.
1245 ld r3,HSTATE_PURR(r13)
1246 ld r4,HSTATE_SPURR(r13)
1257 /* r5 is a guest timebase value here, convert to host TB */
1258 ld r3,HSTATE_KVM_VCORE(r13)
1259 ld r4,VCORE_TB_OFFSET(r3)
1261 std r5,VCPU_DEC_EXPIRES(r9)
1265 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1266 /* Save POWER8-specific registers */
1270 std r5, VCPU_IAMR(r9)
1271 stw r6, VCPU_PSPB(r9)
1272 std r7, VCPU_FSCR(r9)
1277 std r6, VCPU_VTB(r9)
1278 std r7, VCPU_TAR(r9)
1279 mfspr r8, SPRN_EBBHR
1280 std r8, VCPU_EBBHR(r9)
1281 mfspr r5, SPRN_EBBRR
1282 mfspr r6, SPRN_BESCR
1283 mfspr r7, SPRN_CSIGR
1285 std r5, VCPU_EBBRR(r9)
1286 std r6, VCPU_BESCR(r9)
1287 std r7, VCPU_CSIGR(r9)
1288 std r8, VCPU_TACR(r9)
1289 mfspr r5, SPRN_TCSCR
1293 std r5, VCPU_TCSCR(r9)
1294 std r6, VCPU_ACOP(r9)
1295 stw r7, VCPU_GUEST_PID(r9)
1296 std r8, VCPU_WORT(r9)
1298 * Restore various registers to 0, where non-zero values
1299 * set by the guest could disrupt the host.
1303 mtspr SPRN_CIABR, r0
1304 mtspr SPRN_DAWRX, r0
1305 mtspr SPRN_TCSCR, r0
1307 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1310 mtspr SPRN_MMCRS, r0
1313 /* Save and reset AMR and UAMOR before turning on the MMU */
1317 std r6,VCPU_UAMOR(r9)
1321 /* Switch DSCR back to host value */
1323 ld r7, HSTATE_DSCR(r13)
1324 std r8, VCPU_DSCR(r9)
1327 /* Save non-volatile GPRs */
1328 std r14, VCPU_GPR(R14)(r9)
1329 std r15, VCPU_GPR(R15)(r9)
1330 std r16, VCPU_GPR(R16)(r9)
1331 std r17, VCPU_GPR(R17)(r9)
1332 std r18, VCPU_GPR(R18)(r9)
1333 std r19, VCPU_GPR(R19)(r9)
1334 std r20, VCPU_GPR(R20)(r9)
1335 std r21, VCPU_GPR(R21)(r9)
1336 std r22, VCPU_GPR(R22)(r9)
1337 std r23, VCPU_GPR(R23)(r9)
1338 std r24, VCPU_GPR(R24)(r9)
1339 std r25, VCPU_GPR(R25)(r9)
1340 std r26, VCPU_GPR(R26)(r9)
1341 std r27, VCPU_GPR(R27)(r9)
1342 std r28, VCPU_GPR(R28)(r9)
1343 std r29, VCPU_GPR(R29)(r9)
1344 std r30, VCPU_GPR(R30)(r9)
1345 std r31, VCPU_GPR(R31)(r9)
1348 mfspr r3, SPRN_SPRG0
1349 mfspr r4, SPRN_SPRG1
1350 mfspr r5, SPRN_SPRG2
1351 mfspr r6, SPRN_SPRG3
1352 std r3, VCPU_SPRG0(r9)
1353 std r4, VCPU_SPRG1(r9)
1354 std r5, VCPU_SPRG2(r9)
1355 std r6, VCPU_SPRG3(r9)
1361 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1364 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1367 /* Increment yield count if they have a VPA */
1368 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1371 li r4, LPPACA_YIELDCOUNT
1376 stb r3, VCPU_VPA_DIRTY(r9)
1378 /* Save PMU registers if requested */
1379 /* r8 and cr0.eq are live here */
1382 * POWER8 seems to have a hardware bug where setting
1383 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1384 * when some counters are already negative doesn't seem
1385 * to cause a performance monitor alert (and hence interrupt).
1386 * The effect of this is that when saving the PMU state,
1387 * if there is no PMU alert pending when we read MMCR0
1388 * before freezing the counters, but one becomes pending
1389 * before we read the counters, we lose it.
1390 * To work around this, we need a way to freeze the counters
1391 * before reading MMCR0. Normally, freezing the counters
1392 * is done by writing MMCR0 (to set MMCR0[FC]) which
1393 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1394 * we can also freeze the counters using MMCR2, by writing
1395 * 1s to all the counter freeze condition bits (there are
1396 * 9 bits each for 6 counters).
1398 li r3, -1 /* set all freeze bits */
1400 mfspr r10, SPRN_MMCR2
1401 mtspr SPRN_MMCR2, r3
1403 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1405 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1406 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1407 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1408 mfspr r6, SPRN_MMCRA
1409 /* Clear MMCRA in order to disable SDAR updates */
1411 mtspr SPRN_MMCRA, r7
1413 beq 21f /* if no VPA, save PMU stuff anyway */
1414 lbz r7, LPPACA_PMCINUSE(r8)
1415 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1417 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1419 21: mfspr r5, SPRN_MMCR1
1422 std r4, VCPU_MMCR(r9)
1423 std r5, VCPU_MMCR + 8(r9)
1424 std r6, VCPU_MMCR + 16(r9)
1426 std r10, VCPU_MMCR + 24(r9)
1427 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1428 std r7, VCPU_SIAR(r9)
1429 std r8, VCPU_SDAR(r9)
1436 stw r3, VCPU_PMC(r9)
1437 stw r4, VCPU_PMC + 4(r9)
1438 stw r5, VCPU_PMC + 8(r9)
1439 stw r6, VCPU_PMC + 12(r9)
1440 stw r7, VCPU_PMC + 16(r9)
1441 stw r8, VCPU_PMC + 20(r9)
1444 mfspr r6, SPRN_SPMC1
1445 mfspr r7, SPRN_SPMC2
1446 mfspr r8, SPRN_MMCRS
1447 std r5, VCPU_SIER(r9)
1448 stw r6, VCPU_PMC + 24(r9)
1449 stw r7, VCPU_PMC + 28(r9)
1450 std r8, VCPU_MMCR + 32(r9)
1452 mtspr SPRN_MMCRS, r4
1453 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1462 * POWER7/POWER8 guest -> host partition switch code.
1463 * We don't have to lock against tlbies but we do
1464 * have to coordinate the hardware threads.
1466 kvmhv_switch_to_host:
1467 /* Secondary threads wait for primary to do partition switch */
1468 ld r5,HSTATE_KVM_VCORE(r13)
1469 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1470 lbz r3,HSTATE_PTID(r13)
1474 13: lbz r3,VCORE_IN_GUEST(r5)
1480 /* Primary thread waits for all the secondaries to exit guest */
1481 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1482 rlwinm r0,r3,32-8,0xff
1488 /* Did we actually switch to the guest at all? */
1489 lbz r6, VCORE_IN_GUEST(r5)
1493 /* Primary thread switches back to host partition */
1494 ld r6,KVM_HOST_SDR1(r4)
1495 lwz r7,KVM_HOST_LPID(r4)
1496 li r8,LPID_RSVD /* switch to reserved LPID */
1499 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1504 /* DPDES is shared between threads */
1505 mfspr r7, SPRN_DPDES
1506 std r7, VCORE_DPDES(r5)
1507 /* clear DPDES so we don't get guest doorbells in the host */
1509 mtspr SPRN_DPDES, r8
1510 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1512 /* If HMI, call kvmppc_realmode_hmi_handler() */
1513 cmpwi r12, BOOK3S_INTERRUPT_HMI
1515 bl kvmppc_realmode_hmi_handler
1517 li r12, BOOK3S_INTERRUPT_HMI
1519 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1520 * the TB. Hence it is not required to subtract guest timebase
1521 * offset from timebase. So, skip it.
1523 * Also, do not call kvmppc_subcore_exit_guest() because it has
1524 * been invoked as part of kvmppc_realmode_hmi_handler().
1529 /* Subtract timebase offset from timebase */
1530 ld r8,VCORE_TB_OFFSET(r5)
1533 mftb r6 /* current guest timebase */
1535 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1536 mftb r7 /* check if lower 24 bits overflowed */
1541 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1544 17: bl kvmppc_subcore_exit_guest
1546 30: ld r5,HSTATE_KVM_VCORE(r13)
1547 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1550 ld r0, VCORE_PCR(r5)
1556 /* Signal secondary CPUs to continue */
1557 stb r0,VCORE_IN_GUEST(r5)
1558 19: lis r8,0x7fff /* MAX_INT@h */
1561 16: ld r8,KVM_HOST_LPCR(r4)
1565 /* load host SLB entries */
1566 ld r8,PACA_SLBSHADOWPTR(r13)
1568 .rept SLB_NUM_BOLTED
1569 li r3, SLBSHADOW_SAVEAREA
1573 andis. r7,r5,SLB_ESID_V@h
1579 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1580 /* Finish timing, if we have a vcpu */
1581 ld r4, HSTATE_KVM_VCPU(r13)
1585 bl kvmhv_accumulate_time
1588 /* Unset guest mode */
1589 li r0, KVM_GUEST_MODE_NONE
1590 stb r0, HSTATE_IN_GUEST(r13)
1592 ld r0, 112+PPC_LR_STKOFF(r1)
1598 * Check whether an HDSI is an HPTE not found fault or something else.
1599 * If it is an HPTE not found fault that is due to the guest accessing
1600 * a page that they have mapped but which we have paged out, then
1601 * we continue on with the guest exit path. In all other cases,
1602 * reflect the HDSI to the guest as a DSI.
1606 mfspr r6, SPRN_HDSISR
1607 /* HPTE not found fault or protection fault? */
1608 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1609 beq 1f /* if not, send it to the guest */
1610 andi. r0, r11, MSR_DR /* data relocation enabled? */
1613 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1614 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1615 bne 7f /* if no SLB entry found */
1616 4: std r4, VCPU_FAULT_DAR(r9)
1617 stw r6, VCPU_FAULT_DSISR(r9)
1619 /* Search the hash table. */
1620 mr r3, r9 /* vcpu pointer */
1621 li r7, 1 /* data fault */
1622 bl kvmppc_hpte_hv_fault
1623 ld r9, HSTATE_KVM_VCPU(r13)
1625 ld r11, VCPU_MSR(r9)
1626 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1627 cmpdi r3, 0 /* retry the instruction */
1629 cmpdi r3, -1 /* handle in kernel mode */
1631 cmpdi r3, -2 /* MMIO emulation; need instr word */
1634 /* Synthesize a DSI (or DSegI) for the guest */
1635 ld r4, VCPU_FAULT_DAR(r9)
1637 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1638 mtspr SPRN_DSISR, r6
1639 7: mtspr SPRN_DAR, r4
1640 mtspr SPRN_SRR0, r10
1641 mtspr SPRN_SRR1, r11
1643 bl kvmppc_msr_interrupt
1644 fast_interrupt_c_return:
1645 6: ld r7, VCPU_CTR(r9)
1652 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1653 ld r5, KVM_VRMA_SLB_V(r5)
1656 /* If this is for emulated MMIO, load the instruction word */
1657 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1659 /* Set guest mode to 'jump over instruction' so if lwz faults
1660 * we'll just continue at the next IP. */
1661 li r0, KVM_GUEST_MODE_SKIP
1662 stb r0, HSTATE_IN_GUEST(r13)
1664 /* Do the access with MSR:DR enabled */
1666 ori r4, r3, MSR_DR /* Enable paging for data */
1671 /* Store the result */
1672 stw r8, VCPU_LAST_INST(r9)
1674 /* Unset guest mode. */
1675 li r0, KVM_GUEST_MODE_HOST_HV
1676 stb r0, HSTATE_IN_GUEST(r13)
1680 * Similarly for an HISI, reflect it to the guest as an ISI unless
1681 * it is an HPTE not found fault for a page that we have paged out.
1684 andis. r0, r11, SRR1_ISI_NOPT@h
1686 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1689 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1690 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1691 bne 7f /* if no SLB entry found */
1693 /* Search the hash table. */
1694 mr r3, r9 /* vcpu pointer */
1697 li r7, 0 /* instruction fault */
1698 bl kvmppc_hpte_hv_fault
1699 ld r9, HSTATE_KVM_VCPU(r13)
1701 ld r11, VCPU_MSR(r9)
1702 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1703 cmpdi r3, 0 /* retry the instruction */
1704 beq fast_interrupt_c_return
1705 cmpdi r3, -1 /* handle in kernel mode */
1708 /* Synthesize an ISI (or ISegI) for the guest */
1710 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1711 7: mtspr SPRN_SRR0, r10
1712 mtspr SPRN_SRR1, r11
1714 bl kvmppc_msr_interrupt
1715 b fast_interrupt_c_return
1717 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1718 ld r5, KVM_VRMA_SLB_V(r6)
1722 * Try to handle an hcall in real mode.
1723 * Returns to the guest if we handle it, or continues on up to
1724 * the kernel if we can't (i.e. if we don't have a handler for
1725 * it, or if the handler returns H_TOO_HARD).
1727 * r5 - r8 contain hcall args,
1728 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1730 hcall_try_real_mode:
1731 ld r3,VCPU_GPR(R3)(r9)
1733 /* sc 1 from userspace - reflect to guest syscall */
1734 bne sc_1_fast_return
1736 cmpldi r3,hcall_real_table_end - hcall_real_table
1738 /* See if this hcall is enabled for in-kernel handling */
1740 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1741 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1743 ld r0, KVM_ENABLED_HCALLS(r4)
1744 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1748 /* Get pointer to handler, if any, and call it */
1749 LOAD_REG_ADDR(r4, hcall_real_table)
1755 mr r3,r9 /* get vcpu pointer */
1756 ld r4,VCPU_GPR(R4)(r9)
1759 beq hcall_real_fallback
1760 ld r4,HSTATE_KVM_VCPU(r13)
1761 std r3,VCPU_GPR(R3)(r4)
1769 li r10, BOOK3S_INTERRUPT_SYSCALL
1770 bl kvmppc_msr_interrupt
1774 /* We've attempted a real mode hcall, but it's punted it back
1775 * to userspace. We need to restore some clobbered volatiles
1776 * before resuming the pass-it-to-qemu path */
1777 hcall_real_fallback:
1778 li r12,BOOK3S_INTERRUPT_SYSCALL
1779 ld r9, HSTATE_KVM_VCPU(r13)
1783 .globl hcall_real_table
1785 .long 0 /* 0 - unused */
1786 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1787 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1788 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1789 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1790 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1791 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1792 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1793 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
1794 .long 0 /* 0x24 - H_SET_SPRG0 */
1795 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1810 #ifdef CONFIG_KVM_XICS
1811 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1812 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1813 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1814 .long 0 /* 0x70 - H_IPOLL */
1815 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1817 .long 0 /* 0x64 - H_EOI */
1818 .long 0 /* 0x68 - H_CPPR */
1819 .long 0 /* 0x6c - H_IPI */
1820 .long 0 /* 0x70 - H_IPOLL */
1821 .long 0 /* 0x74 - H_XIRR */
1849 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1850 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1866 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1870 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1871 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
1872 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
1985 .long DOTSYM(kvmppc_h_random) - hcall_real_table
1986 .globl hcall_real_table_end
1987 hcall_real_table_end:
1989 _GLOBAL(kvmppc_h_set_xdabr)
1990 andi. r0, r5, DABRX_USER | DABRX_KERNEL
1992 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
1995 6: li r3, H_PARAMETER
1998 _GLOBAL(kvmppc_h_set_dabr)
1999 li r5, DABRX_USER | DABRX_KERNEL
2003 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2004 std r4,VCPU_DABR(r3)
2005 stw r5, VCPU_DABRX(r3)
2006 mtspr SPRN_DABRX, r5
2007 /* Work around P7 bug where DABR can get corrupted on mtspr */
2008 1: mtspr SPRN_DABR,r4
2016 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2017 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2018 rlwimi r5, r4, 2, DAWRX_WT
2020 std r4, VCPU_DAWR(r3)
2021 std r5, VCPU_DAWRX(r3)
2023 mtspr SPRN_DAWRX, r5
2027 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2029 std r11,VCPU_MSR(r3)
2031 stb r0,VCPU_CEDED(r3)
2032 sync /* order setting ceded vs. testing prodded */
2033 lbz r5,VCPU_PRODDED(r3)
2035 bne kvm_cede_prodded
2036 li r12,0 /* set trap to 0 to say hcall is handled */
2037 stw r12,VCPU_TRAP(r3)
2039 std r0,VCPU_GPR(R3)(r3)
2042 * Set our bit in the bitmask of napping threads unless all the
2043 * other threads are already napping, in which case we send this
2046 ld r5,HSTATE_KVM_VCORE(r13)
2047 lbz r6,HSTATE_PTID(r13)
2048 lwz r8,VCORE_ENTRY_EXIT(r5)
2052 addi r6,r5,VCORE_NAPPING_THREADS
2059 /* order napping_threads update vs testing entry_exit_map */
2062 stb r0,HSTATE_NAPPING(r13)
2063 lwz r7,VCORE_ENTRY_EXIT(r5)
2065 bge 33f /* another thread already exiting */
2068 * Although not specifically required by the architecture, POWER7
2069 * preserves the following registers in nap mode, even if an SMT mode
2070 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2071 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2073 /* Save non-volatile GPRs */
2074 std r14, VCPU_GPR(R14)(r3)
2075 std r15, VCPU_GPR(R15)(r3)
2076 std r16, VCPU_GPR(R16)(r3)
2077 std r17, VCPU_GPR(R17)(r3)
2078 std r18, VCPU_GPR(R18)(r3)
2079 std r19, VCPU_GPR(R19)(r3)
2080 std r20, VCPU_GPR(R20)(r3)
2081 std r21, VCPU_GPR(R21)(r3)
2082 std r22, VCPU_GPR(R22)(r3)
2083 std r23, VCPU_GPR(R23)(r3)
2084 std r24, VCPU_GPR(R24)(r3)
2085 std r25, VCPU_GPR(R25)(r3)
2086 std r26, VCPU_GPR(R26)(r3)
2087 std r27, VCPU_GPR(R27)(r3)
2088 std r28, VCPU_GPR(R28)(r3)
2089 std r29, VCPU_GPR(R29)(r3)
2090 std r30, VCPU_GPR(R30)(r3)
2091 std r31, VCPU_GPR(R31)(r3)
2096 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2098 ld r9, HSTATE_KVM_VCPU(r13)
2100 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2104 * Set DEC to the smaller of DEC and HDEC, so that we wake
2105 * no later than the end of our timeslice (HDEC interrupts
2106 * don't wake us from nap).
2115 /* save expiry time of guest decrementer */
2118 ld r4, HSTATE_KVM_VCPU(r13)
2119 ld r5, HSTATE_KVM_VCORE(r13)
2120 ld r6, VCORE_TB_OFFSET(r5)
2121 subf r3, r6, r3 /* convert to host TB value */
2122 std r3, VCPU_DEC_EXPIRES(r4)
2124 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2125 ld r4, HSTATE_KVM_VCPU(r13)
2126 addi r3, r4, VCPU_TB_CEDE
2127 bl kvmhv_accumulate_time
2130 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2133 * Take a nap until a decrementer or external or doobell interrupt
2134 * occurs, with PECE1 and PECE0 set in LPCR.
2135 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2136 * Also clear the runlatch bit before napping.
2139 mfspr r0, SPRN_CTRLF
2141 mtspr SPRN_CTRLT, r0
2144 stb r0,HSTATE_HWTHREAD_REQ(r13)
2146 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2148 ori r5, r5, LPCR_PECEDH
2149 rlwimi r5, r3, 0, LPCR_PECEDP
2150 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2154 std r0, HSTATE_SCRATCH0(r13)
2156 ld r0, HSTATE_SCRATCH0(r13)
2168 /* get vcpu pointer */
2169 ld r4, HSTATE_KVM_VCPU(r13)
2171 /* Woken by external or decrementer interrupt */
2172 ld r1, HSTATE_HOST_R1(r13)
2174 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2175 addi r3, r4, VCPU_TB_RMINTR
2176 bl kvmhv_accumulate_time
2179 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2181 bl kvmppc_restore_tm
2182 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2185 /* load up FP state */
2188 /* Restore guest decrementer */
2189 ld r3, VCPU_DEC_EXPIRES(r4)
2190 ld r5, HSTATE_KVM_VCORE(r13)
2191 ld r6, VCORE_TB_OFFSET(r5)
2192 add r3, r3, r6 /* convert host TB to guest TB value */
2198 ld r14, VCPU_GPR(R14)(r4)
2199 ld r15, VCPU_GPR(R15)(r4)
2200 ld r16, VCPU_GPR(R16)(r4)
2201 ld r17, VCPU_GPR(R17)(r4)
2202 ld r18, VCPU_GPR(R18)(r4)
2203 ld r19, VCPU_GPR(R19)(r4)
2204 ld r20, VCPU_GPR(R20)(r4)
2205 ld r21, VCPU_GPR(R21)(r4)
2206 ld r22, VCPU_GPR(R22)(r4)
2207 ld r23, VCPU_GPR(R23)(r4)
2208 ld r24, VCPU_GPR(R24)(r4)
2209 ld r25, VCPU_GPR(R25)(r4)
2210 ld r26, VCPU_GPR(R26)(r4)
2211 ld r27, VCPU_GPR(R27)(r4)
2212 ld r28, VCPU_GPR(R28)(r4)
2213 ld r29, VCPU_GPR(R29)(r4)
2214 ld r30, VCPU_GPR(R30)(r4)
2215 ld r31, VCPU_GPR(R31)(r4)
2217 /* Check the wake reason in SRR1 to see why we got here */
2218 bl kvmppc_check_wake_reason
2220 /* clear our bit in vcore->napping_threads */
2221 34: ld r5,HSTATE_KVM_VCORE(r13)
2222 lbz r7,HSTATE_PTID(r13)
2225 addi r6,r5,VCORE_NAPPING_THREADS
2231 stb r0,HSTATE_NAPPING(r13)
2233 /* See if the wake reason means we need to exit */
2234 stw r12, VCPU_TRAP(r4)
2239 /* see if any other thread is already exiting */
2240 lwz r0,VCORE_ENTRY_EXIT(r5)
2244 b kvmppc_cede_reentry /* if not go back to guest */
2246 /* cede when already previously prodded case */
2249 stb r0,VCPU_PRODDED(r3)
2250 sync /* order testing prodded vs. clearing ceded */
2251 stb r0,VCPU_CEDED(r3)
2255 /* we've ceded but we want to give control to the host */
2257 ld r9, HSTATE_KVM_VCPU(r13)
2260 /* Try to handle a machine check in real mode */
2261 machine_check_realmode:
2262 mr r3, r9 /* get vcpu pointer */
2263 bl kvmppc_realmode_machine_check
2265 ld r9, HSTATE_KVM_VCPU(r13)
2266 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2268 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2269 * machine check interrupt (set HSRR0 to 0x200). And for handled
2270 * errors (no-fatal), just go back to guest execution with current
2271 * HSRR0 instead of exiting guest. This new approach will inject
2272 * machine check to guest for fatal error causing guest to crash.
2274 * The old code used to return to host for unhandled errors which
2275 * was causing guest to hang with soft lockups inside guest and
2276 * makes it difficult to recover guest instance.
2278 * if we receive machine check with MSR(RI=0) then deliver it to
2279 * guest as machine check causing guest to crash.
2281 ld r11, VCPU_MSR(r9)
2282 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2283 bne mc_cont /* if so, exit to host */
2284 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2285 beq 1f /* Deliver a machine check to guest */
2287 cmpdi r3, 0 /* Did we handle MCE ? */
2288 bne 2f /* Continue guest execution. */
2289 /* If not, deliver a machine check. SRR0/1 are already set */
2290 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2291 bl kvmppc_msr_interrupt
2292 2: b fast_interrupt_c_return
2295 * Check the reason we woke from nap, and take appropriate action.
2297 * 0 if nothing needs to be done
2298 * 1 if something happened that needs to be handled by the host
2299 * -1 if there was a guest wakeup (IPI or msgsnd)
2301 * Also sets r12 to the interrupt vector for any interrupt that needs
2302 * to be handled now by the host (0x500 for external interrupt), or zero.
2303 * Modifies r0, r6, r7, r8.
2305 kvmppc_check_wake_reason:
2308 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2310 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2311 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2312 cmpwi r6, 8 /* was it an external interrupt? */
2313 li r12, BOOK3S_INTERRUPT_EXTERNAL
2314 beq kvmppc_read_intr /* if so, see what it was */
2317 cmpwi r6, 6 /* was it the decrementer? */
2320 cmpwi r6, 5 /* privileged doorbell? */
2322 cmpwi r6, 3 /* hypervisor doorbell? */
2324 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2325 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2327 li r3, 1 /* anything else, return 1 */
2330 /* hypervisor doorbell */
2331 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2334 * Clear the doorbell as we will invoke the handler
2335 * explicitly in the guest exit path.
2337 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2339 /* see if it's a host IPI */
2341 lbz r0, HSTATE_HOST_IPI(r13)
2344 /* if not, return -1 */
2348 /* Woken up due to Hypervisor maintenance interrupt */
2349 4: li r12, BOOK3S_INTERRUPT_HMI
2354 * Determine what sort of external interrupt is pending (if any).
2356 * 0 if no interrupt is pending
2357 * 1 if an interrupt is pending that needs to be handled by the host
2358 * -1 if there was a guest wakeup IPI (which has now been cleared)
2359 * Modifies r0, r6, r7, r8, returns value in r3.
2362 /* see if a host IPI is pending */
2364 lbz r0, HSTATE_HOST_IPI(r13)
2368 /* Now read the interrupt from the ICP */
2369 ld r6, HSTATE_XICS_PHYS(r13)
2375 * Save XIRR for later. Since we get in in reverse endian on LE
2376 * systems, save it byte reversed and fetch it back in host endian.
2378 li r3, HSTATE_SAVED_XIRR
2380 #ifdef __LITTLE_ENDIAN__
2381 lwz r3, HSTATE_SAVED_XIRR(r13)
2385 rlwinm. r3, r3, 0, 0xffffff
2387 beq 1f /* if nothing pending in the ICP */
2389 /* We found something in the ICP...
2391 * If it's not an IPI, stash it in the PACA and return to
2392 * the host, we don't (yet) handle directing real external
2393 * interrupts directly to the guest
2395 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2398 /* It's an IPI, clear the MFRR and EOI it */
2401 stbcix r3, r6, r8 /* clear the IPI */
2402 stwcix r0, r6, r7 /* EOI it */
2405 /* We need to re-check host IPI now in case it got set in the
2406 * meantime. If it's clear, we bounce the interrupt to the
2409 lbz r0, HSTATE_HOST_IPI(r13)
2413 /* OK, it's an IPI for us */
2418 42: /* It's not an IPI and it's for the host. We saved a copy of XIRR in
2419 * the PACA earlier, it will be picked up by the host ICP driver
2424 43: /* We raced with the host, we need to resend that IPI, bummer */
2426 stbcix r0, r6, r8 /* set the IPI */
2432 * Save away FP, VMX and VSX registers.
2434 * N.B. r30 and r31 are volatile across this function,
2435 * thus it is not callable from C.
2442 #ifdef CONFIG_ALTIVEC
2444 oris r8,r8,MSR_VEC@h
2445 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2449 oris r8,r8,MSR_VSX@h
2450 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2453 addi r3,r3,VCPU_FPRS
2455 #ifdef CONFIG_ALTIVEC
2457 addi r3,r31,VCPU_VRS
2459 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2461 mfspr r6,SPRN_VRSAVE
2462 stw r6,VCPU_VRSAVE(r31)
2467 * Load up FP, VMX and VSX registers
2469 * N.B. r30 and r31 are volatile across this function,
2470 * thus it is not callable from C.
2477 #ifdef CONFIG_ALTIVEC
2479 oris r8,r8,MSR_VEC@h
2480 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2484 oris r8,r8,MSR_VSX@h
2485 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2488 addi r3,r4,VCPU_FPRS
2490 #ifdef CONFIG_ALTIVEC
2492 addi r3,r31,VCPU_VRS
2494 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2496 lwz r7,VCPU_VRSAVE(r31)
2497 mtspr SPRN_VRSAVE,r7
2502 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2504 * Save transactional state and TM-related registers.
2505 * Called with r9 pointing to the vcpu struct.
2506 * This can modify all checkpointed registers, but
2507 * restores r1, r2 and r9 (vcpu pointer) before exit.
2511 std r0, PPC_LR_STKOFF(r1)
2516 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2520 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2521 beq 1f /* TM not active in guest. */
2523 std r1, HSTATE_HOST_R1(r13)
2524 li r3, TM_CAUSE_KVM_RESCHED
2526 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2530 /* All GPRs are volatile at this point. */
2533 /* Temporarily store r13 and r9 so we have some regs to play with */
2536 std r9, PACATMSCRATCH(r13)
2537 ld r9, HSTATE_KVM_VCPU(r13)
2539 /* Get a few more GPRs free. */
2540 std r29, VCPU_GPRS_TM(29)(r9)
2541 std r30, VCPU_GPRS_TM(30)(r9)
2542 std r31, VCPU_GPRS_TM(31)(r9)
2544 /* Save away PPR and DSCR soon so don't run with user values. */
2547 mfspr r30, SPRN_DSCR
2548 ld r29, HSTATE_DSCR(r13)
2549 mtspr SPRN_DSCR, r29
2551 /* Save all but r9, r13 & r29-r31 */
2554 .if (reg != 9) && (reg != 13)
2555 std reg, VCPU_GPRS_TM(reg)(r9)
2559 /* ... now save r13 */
2561 std r4, VCPU_GPRS_TM(13)(r9)
2562 /* ... and save r9 */
2563 ld r4, PACATMSCRATCH(r13)
2564 std r4, VCPU_GPRS_TM(9)(r9)
2566 /* Reload stack pointer and TOC. */
2567 ld r1, HSTATE_HOST_R1(r13)
2570 /* Set MSR RI now we have r1 and r13 back. */
2574 /* Save away checkpinted SPRs. */
2575 std r31, VCPU_PPR_TM(r9)
2576 std r30, VCPU_DSCR_TM(r9)
2582 std r5, VCPU_LR_TM(r9)
2583 stw r6, VCPU_CR_TM(r9)
2584 std r7, VCPU_CTR_TM(r9)
2585 std r8, VCPU_AMR_TM(r9)
2586 std r10, VCPU_TAR_TM(r9)
2588 /* Restore r12 as trap number. */
2589 lwz r12, VCPU_TRAP(r9)
2592 addi r3, r9, VCPU_FPRS_TM
2594 addi r3, r9, VCPU_VRS_TM
2596 mfspr r6, SPRN_VRSAVE
2597 stw r6, VCPU_VRSAVE_TM(r9)
2600 * We need to save these SPRs after the treclaim so that the software
2601 * error code is recorded correctly in the TEXASR. Also the user may
2602 * change these outside of a transaction, so they must always be
2605 mfspr r5, SPRN_TFHAR
2606 mfspr r6, SPRN_TFIAR
2607 mfspr r7, SPRN_TEXASR
2608 std r5, VCPU_TFHAR(r9)
2609 std r6, VCPU_TFIAR(r9)
2610 std r7, VCPU_TEXASR(r9)
2612 ld r0, PPC_LR_STKOFF(r1)
2617 * Restore transactional state and TM-related registers.
2618 * Called with r4 pointing to the vcpu struct.
2619 * This potentially modifies all checkpointed registers.
2620 * It restores r1, r2, r4 from the PACA.
2624 std r0, PPC_LR_STKOFF(r1)
2626 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2632 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2636 * The user may change these outside of a transaction, so they must
2637 * always be context switched.
2639 ld r5, VCPU_TFHAR(r4)
2640 ld r6, VCPU_TFIAR(r4)
2641 ld r7, VCPU_TEXASR(r4)
2642 mtspr SPRN_TFHAR, r5
2643 mtspr SPRN_TFIAR, r6
2644 mtspr SPRN_TEXASR, r7
2647 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2648 beqlr /* TM not active in guest */
2649 std r1, HSTATE_HOST_R1(r13)
2651 /* Make sure the failure summary is set, otherwise we'll program check
2652 * when we trechkpt. It's possible that this might have been not set
2653 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2656 oris r7, r7, (TEXASR_FS)@h
2657 mtspr SPRN_TEXASR, r7
2660 * We need to load up the checkpointed state for the guest.
2661 * We need to do this early as it will blow away any GPRs, VSRs and
2666 addi r3, r31, VCPU_FPRS_TM
2668 addi r3, r31, VCPU_VRS_TM
2671 lwz r7, VCPU_VRSAVE_TM(r4)
2672 mtspr SPRN_VRSAVE, r7
2674 ld r5, VCPU_LR_TM(r4)
2675 lwz r6, VCPU_CR_TM(r4)
2676 ld r7, VCPU_CTR_TM(r4)
2677 ld r8, VCPU_AMR_TM(r4)
2678 ld r9, VCPU_TAR_TM(r4)
2686 * Load up PPR and DSCR values but don't put them in the actual SPRs
2687 * till the last moment to avoid running with userspace PPR and DSCR for
2690 ld r29, VCPU_DSCR_TM(r4)
2691 ld r30, VCPU_PPR_TM(r4)
2693 std r2, PACATMSCRATCH(r13) /* Save TOC */
2695 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2699 /* Load GPRs r0-r28 */
2702 ld reg, VCPU_GPRS_TM(reg)(r31)
2706 mtspr SPRN_DSCR, r29
2709 /* Load final GPRs */
2710 ld 29, VCPU_GPRS_TM(29)(r31)
2711 ld 30, VCPU_GPRS_TM(30)(r31)
2712 ld 31, VCPU_GPRS_TM(31)(r31)
2714 /* TM checkpointed state is now setup. All GPRs are now volatile. */
2717 /* Now let's get back the state we need. */
2720 ld r29, HSTATE_DSCR(r13)
2721 mtspr SPRN_DSCR, r29
2722 ld r4, HSTATE_KVM_VCPU(r13)
2723 ld r1, HSTATE_HOST_R1(r13)
2724 ld r2, PACATMSCRATCH(r13)
2726 /* Set the MSR RI since we have our registers back. */
2730 ld r0, PPC_LR_STKOFF(r1)
2736 * We come here if we get any exception or interrupt while we are
2737 * executing host real mode code while in guest MMU context.
2738 * For now just spin, but we should do something better.
2740 kvmppc_bad_host_intr:
2744 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2745 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2746 * r11 has the guest MSR value (in/out)
2747 * r9 has a vcpu pointer (in)
2748 * r0 is used as a scratch register
2750 kvmppc_msr_interrupt:
2751 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2752 cmpwi r0, 2 /* Check if we are in transactional state.. */
2753 ld r11, VCPU_INTR_MSR(r9)
2755 /* ... if transactional, change to suspended */
2757 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2761 * This works around a hardware bug on POWER8E processors, where
2762 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2763 * performance monitor interrupt. Instead, when we need to have
2764 * an interrupt pending, we have to arrange for a counter to overflow.
2768 mtspr SPRN_MMCR2, r3
2769 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2770 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2771 mtspr SPRN_MMCR0, r3
2778 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2780 * Start timing an activity
2781 * r3 = pointer to time accumulation struct, r4 = vcpu
2784 ld r5, HSTATE_KVM_VCORE(r13)
2785 lbz r6, VCORE_IN_GUEST(r5)
2787 beq 5f /* if in guest, need to */
2788 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2791 std r3, VCPU_CUR_ACTIVITY(r4)
2792 std r5, VCPU_ACTIVITY_START(r4)
2796 * Accumulate time to one activity and start another.
2797 * r3 = pointer to new time accumulation struct, r4 = vcpu
2799 kvmhv_accumulate_time:
2800 ld r5, HSTATE_KVM_VCORE(r13)
2801 lbz r8, VCORE_IN_GUEST(r5)
2803 beq 4f /* if in guest, need to */
2804 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2805 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2806 ld r6, VCPU_ACTIVITY_START(r4)
2807 std r3, VCPU_CUR_ACTIVITY(r4)
2810 std r7, VCPU_ACTIVITY_START(r4)
2814 ld r8, TAS_SEQCOUNT(r5)
2817 std r8, TAS_SEQCOUNT(r5)
2819 ld r7, TAS_TOTAL(r5)
2821 std r7, TAS_TOTAL(r5)
2827 3: std r3, TAS_MIN(r5)
2833 std r8, TAS_SEQCOUNT(r5)