2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <asm/uaccess.h>
46 #include <asm/machdep.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
65 #define DBG(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...) udbg_printf(fmt)
73 #define DBG_LOW(fmt...)
81 * Note: pte --> Linux PTE
82 * HPTE --> PowerPC Hashed Page Table Entry
85 * htab_initialize is called with the MMU off (of course), but
86 * the kernel has been copied down to zero so it can directly
87 * reference global data. At this point it is very difficult
88 * to print debug info.
92 static unsigned long _SDR1;
93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94 EXPORT_SYMBOL_GPL(mmu_psize_defs);
96 struct hash_pte *htab_address;
97 unsigned long htab_size_bytes;
98 unsigned long htab_hash_mask;
99 EXPORT_SYMBOL_GPL(htab_hash_mask);
100 int mmu_linear_psize = MMU_PAGE_4K;
101 EXPORT_SYMBOL_GPL(mmu_linear_psize);
102 int mmu_virtual_psize = MMU_PAGE_4K;
103 int mmu_vmalloc_psize = MMU_PAGE_4K;
104 #ifdef CONFIG_SPARSEMEM_VMEMMAP
105 int mmu_vmemmap_psize = MMU_PAGE_4K;
107 int mmu_io_psize = MMU_PAGE_4K;
108 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
109 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
110 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
111 u16 mmu_slb_size = 64;
112 EXPORT_SYMBOL_GPL(mmu_slb_size);
113 #ifdef CONFIG_PPC_64K_PAGES
114 int mmu_ci_restrictions;
116 #ifdef CONFIG_DEBUG_PAGEALLOC
117 static u8 *linear_map_hash_slots;
118 static unsigned long linear_map_hash_count;
119 static DEFINE_SPINLOCK(linear_map_hash_lock);
120 #endif /* CONFIG_DEBUG_PAGEALLOC */
121 struct mmu_hash_ops mmu_hash_ops;
122 EXPORT_SYMBOL(mmu_hash_ops);
124 /* There are definitions of page sizes arrays to be used when none
125 * is provided by the firmware.
128 /* Pre-POWER4 CPUs (4k pages only)
130 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
140 /* POWER4, GPUL, POWER5
142 * Support for 16Mb large pages
144 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
148 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
156 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
163 * 'R' and 'C' update notes:
164 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
165 * create writeable HPTEs without C set, because the hcall H_PROTECT
166 * that we use in that case will not update C
167 * - The above is however not a problem, because we also don't do that
168 * fancy "no flush" variant of eviction and we use H_REMOVE which will
169 * do the right thing and thus we don't have the race I described earlier
171 * - Under bare metal, we do have the race, so we need R and C set
172 * - We make sure R is always set and never lost
173 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
175 unsigned long htab_convert_pte_flags(unsigned long pteflags)
177 unsigned long rflags = 0;
179 /* _PAGE_EXEC -> NOEXEC */
180 if ((pteflags & _PAGE_EXEC) == 0)
184 * Linux uses slb key 0 for kernel and 1 for user.
185 * kernel RW areas are mapped with PPP=0b000
186 * User area is mapped with PPP=0b010 for read/write
187 * or PPP=0b011 for read-only (including writeable but clean pages).
189 if (pteflags & _PAGE_PRIVILEGED) {
191 * Kernel read only mapped with ppp bits 0b110
193 if (!(pteflags & _PAGE_WRITE))
194 rflags |= (HPTE_R_PP0 | 0x2);
196 if (pteflags & _PAGE_RWX)
198 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
202 * We can't allow hardware to update hpte bits. Hence always
203 * set 'R' bit and set 'C' if it is a write fault
207 if (pteflags & _PAGE_DIRTY)
213 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
215 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
216 rflags |= (HPTE_R_I | HPTE_R_G);
217 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
218 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
221 * Add memory coherence if cache inhibited is not set
228 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
229 unsigned long pstart, unsigned long prot,
230 int psize, int ssize)
232 unsigned long vaddr, paddr;
233 unsigned int step, shift;
236 shift = mmu_psize_defs[psize].shift;
239 prot = htab_convert_pte_flags(prot);
241 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
242 vstart, vend, pstart, prot, psize, ssize);
244 for (vaddr = vstart, paddr = pstart; vaddr < vend;
245 vaddr += step, paddr += step) {
246 unsigned long hash, hpteg;
247 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
248 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
249 unsigned long tprot = prot;
252 * If we hit a bad address return error.
256 /* Make kernel text executable */
257 if (overlaps_kernel_text(vaddr, vaddr + step))
260 /* Make kvm guest trampolines executable */
261 if (overlaps_kvm_tmp(vaddr, vaddr + step))
265 * If relocatable, check if it overlaps interrupt vectors that
266 * are copied down to real 0. For relocatable kernel
267 * (e.g. kdump case) we copy interrupt vectors down to real
268 * address 0. Mark that region as executable. This is
269 * because on p8 system with relocation on exception feature
270 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
271 * in order to execute the interrupt handlers in virtual
272 * mode the vector region need to be marked as executable.
274 if ((PHYSICAL_START > MEMORY_START) &&
275 overlaps_interrupt_vector_text(vaddr, vaddr + step))
278 hash = hpt_hash(vpn, shift, ssize);
279 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
281 BUG_ON(!mmu_hash_ops.hpte_insert);
282 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
283 HPTE_V_BOLTED, psize, psize,
289 #ifdef CONFIG_DEBUG_PAGEALLOC
290 if (debug_pagealloc_enabled() &&
291 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
292 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
293 #endif /* CONFIG_DEBUG_PAGEALLOC */
295 return ret < 0 ? ret : 0;
298 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
299 int psize, int ssize)
302 unsigned int step, shift;
306 shift = mmu_psize_defs[psize].shift;
309 if (!mmu_hash_ops.hpte_removebolted)
312 for (vaddr = vstart; vaddr < vend; vaddr += step) {
313 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
325 static bool disable_1tb_segments = false;
327 static int __init parse_disable_1tb_segments(char *p)
329 disable_1tb_segments = true;
332 early_param("disable_1tb_segments", parse_disable_1tb_segments);
334 static int __init htab_dt_scan_seg_sizes(unsigned long node,
335 const char *uname, int depth,
338 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
342 /* We are scanning "cpu" nodes only */
343 if (type == NULL || strcmp(type, "cpu") != 0)
346 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
349 for (; size >= 4; size -= 4, ++prop) {
350 if (be32_to_cpu(prop[0]) == 40) {
351 DBG("1T segment support detected\n");
353 if (disable_1tb_segments) {
354 DBG("1T segments disabled by command line\n");
358 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
362 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
366 static int __init get_idx_from_shift(unsigned int shift)
390 static int __init htab_dt_scan_page_sizes(unsigned long node,
391 const char *uname, int depth,
394 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
398 /* We are scanning "cpu" nodes only */
399 if (type == NULL || strcmp(type, "cpu") != 0)
402 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
406 pr_info("Page sizes from device-tree:\n");
408 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
410 unsigned int base_shift = be32_to_cpu(prop[0]);
411 unsigned int slbenc = be32_to_cpu(prop[1]);
412 unsigned int lpnum = be32_to_cpu(prop[2]);
413 struct mmu_psize_def *def;
416 size -= 3; prop += 3;
417 base_idx = get_idx_from_shift(base_shift);
419 /* skip the pte encoding also */
420 prop += lpnum * 2; size -= lpnum * 2;
423 def = &mmu_psize_defs[base_idx];
424 if (base_idx == MMU_PAGE_16M)
425 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
427 def->shift = base_shift;
428 if (base_shift <= 23)
431 def->avpnm = (1 << (base_shift - 23)) - 1;
434 * We don't know for sure what's up with tlbiel, so
435 * for now we only set it for 4K and 64K pages
437 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
442 while (size > 0 && lpnum) {
443 unsigned int shift = be32_to_cpu(prop[0]);
444 int penc = be32_to_cpu(prop[1]);
446 prop += 2; size -= 2;
449 idx = get_idx_from_shift(shift);
454 pr_err("Invalid penc for base_shift=%d "
455 "shift=%d\n", base_shift, shift);
457 def->penc[idx] = penc;
458 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
459 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
460 base_shift, shift, def->sllp,
461 def->avpnm, def->tlbiel, def->penc[idx]);
468 #ifdef CONFIG_HUGETLB_PAGE
469 /* Scan for 16G memory blocks that have been set aside for huge pages
470 * and reserve those blocks for 16G huge pages.
472 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
473 const char *uname, int depth,
475 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
476 const __be64 *addr_prop;
477 const __be32 *page_count_prop;
478 unsigned int expected_pages;
479 long unsigned int phys_addr;
480 long unsigned int block_size;
482 /* We are scanning "memory" nodes only */
483 if (type == NULL || strcmp(type, "memory") != 0)
486 /* This property is the log base 2 of the number of virtual pages that
487 * will represent this memory block. */
488 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
489 if (page_count_prop == NULL)
491 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
492 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
493 if (addr_prop == NULL)
495 phys_addr = be64_to_cpu(addr_prop[0]);
496 block_size = be64_to_cpu(addr_prop[1]);
497 if (block_size != (16 * GB))
499 printk(KERN_INFO "Huge page(16GB) memory: "
500 "addr = 0x%lX size = 0x%lX pages = %d\n",
501 phys_addr, block_size, expected_pages);
502 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
503 memblock_reserve(phys_addr, block_size * expected_pages);
504 add_gpage(phys_addr, block_size, expected_pages);
508 #endif /* CONFIG_HUGETLB_PAGE */
510 static void mmu_psize_set_default_penc(void)
513 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
514 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
515 mmu_psize_defs[bpsize].penc[apsize] = -1;
518 #ifdef CONFIG_PPC_64K_PAGES
520 static bool might_have_hea(void)
523 * The HEA ethernet adapter requires awareness of the
524 * GX bus. Without that awareness we can easily assume
525 * we will never see an HEA ethernet device.
527 #ifdef CONFIG_IBMEBUS
528 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
529 !firmware_has_feature(FW_FEATURE_SPLPAR);
535 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
537 static void __init htab_scan_page_sizes(void)
541 /* se the invalid penc to -1 */
542 mmu_psize_set_default_penc();
544 /* Default to 4K pages only */
545 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
546 sizeof(mmu_psize_defaults_old));
549 * Try to find the available page sizes in the device-tree
551 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
552 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
554 * Nothing in the device-tree, but the CPU supports 16M pages,
555 * so let's fallback on a known size list for 16M capable CPUs.
557 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
558 sizeof(mmu_psize_defaults_gp));
561 #ifdef CONFIG_HUGETLB_PAGE
562 /* Reserve 16G huge page memory sections for huge pages */
563 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
564 #endif /* CONFIG_HUGETLB_PAGE */
567 static void __init htab_init_page_sizes(void)
569 if (!debug_pagealloc_enabled()) {
571 * Pick a size for the linear mapping. Currently, we only
572 * support 16M, 1M and 4K which is the default
574 if (mmu_psize_defs[MMU_PAGE_16M].shift)
575 mmu_linear_psize = MMU_PAGE_16M;
576 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
577 mmu_linear_psize = MMU_PAGE_1M;
580 #ifdef CONFIG_PPC_64K_PAGES
582 * Pick a size for the ordinary pages. Default is 4K, we support
583 * 64K for user mappings and vmalloc if supported by the processor.
584 * We only use 64k for ioremap if the processor
585 * (and firmware) support cache-inhibited large pages.
586 * If not, we use 4k and set mmu_ci_restrictions so that
587 * hash_page knows to switch processes that use cache-inhibited
588 * mappings to 4k pages.
590 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
591 mmu_virtual_psize = MMU_PAGE_64K;
592 mmu_vmalloc_psize = MMU_PAGE_64K;
593 if (mmu_linear_psize == MMU_PAGE_4K)
594 mmu_linear_psize = MMU_PAGE_64K;
595 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
597 * When running on pSeries using 64k pages for ioremap
598 * would stop us accessing the HEA ethernet. So if we
599 * have the chance of ever seeing one, stay at 4k.
601 if (!might_have_hea())
602 mmu_io_psize = MMU_PAGE_64K;
604 mmu_ci_restrictions = 1;
606 #endif /* CONFIG_PPC_64K_PAGES */
608 #ifdef CONFIG_SPARSEMEM_VMEMMAP
609 /* We try to use 16M pages for vmemmap if that is supported
610 * and we have at least 1G of RAM at boot
612 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
613 memblock_phys_mem_size() >= 0x40000000)
614 mmu_vmemmap_psize = MMU_PAGE_16M;
615 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
616 mmu_vmemmap_psize = MMU_PAGE_64K;
618 mmu_vmemmap_psize = MMU_PAGE_4K;
619 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
621 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
622 "virtual = %d, io = %d"
623 #ifdef CONFIG_SPARSEMEM_VMEMMAP
627 mmu_psize_defs[mmu_linear_psize].shift,
628 mmu_psize_defs[mmu_virtual_psize].shift,
629 mmu_psize_defs[mmu_io_psize].shift
630 #ifdef CONFIG_SPARSEMEM_VMEMMAP
631 ,mmu_psize_defs[mmu_vmemmap_psize].shift
636 static int __init htab_dt_scan_pftsize(unsigned long node,
637 const char *uname, int depth,
640 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
643 /* We are scanning "cpu" nodes only */
644 if (type == NULL || strcmp(type, "cpu") != 0)
647 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
649 /* pft_size[0] is the NUMA CEC cookie */
650 ppc64_pft_size = be32_to_cpu(prop[1]);
656 unsigned htab_shift_for_mem_size(unsigned long mem_size)
658 unsigned memshift = __ilog2(mem_size);
659 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
662 /* round mem_size up to next power of 2 */
663 if ((1UL << memshift) < mem_size)
666 /* aim for 2 pages / pteg */
667 pteg_shift = memshift - (pshift + 1);
670 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
671 * size permitted by the architecture.
673 return max(pteg_shift + 7, 18U);
676 static unsigned long __init htab_get_table_size(void)
678 /* If hash size isn't already provided by the platform, we try to
679 * retrieve it from the device-tree. If it's not there neither, we
680 * calculate it now based on the total RAM size
682 if (ppc64_pft_size == 0)
683 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
685 return 1UL << ppc64_pft_size;
687 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
690 #ifdef CONFIG_MEMORY_HOTPLUG
691 int create_section_mapping(unsigned long start, unsigned long end)
693 int rc = htab_bolt_mapping(start, end, __pa(start),
694 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
698 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
700 BUG_ON(rc2 && (rc2 != -ENOENT));
705 int remove_section_mapping(unsigned long start, unsigned long end)
707 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
712 #endif /* CONFIG_MEMORY_HOTPLUG */
714 static void update_hid_for_hash(void)
717 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
719 asm volatile("ptesync": : :"memory");
720 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
721 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
722 : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");
723 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
727 hid0 = mfspr(SPRN_HID0);
728 hid0 &= ~HID0_POWER9_RADIX;
729 mtspr(SPRN_HID0, hid0);
730 asm volatile("isync": : :"memory");
732 /* Wait for it to happen */
733 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
737 static void __init hash_init_partition_table(phys_addr_t hash_table,
738 unsigned long htab_size)
740 unsigned long ps_field;
741 unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
744 * slb llp encoding for the page size used in VPM real mode.
745 * We can ignore that for lpid 0
748 htab_size = __ilog2(htab_size) - 18;
750 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
751 partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
752 MEMBLOCK_ALLOC_ANYWHERE));
754 /* Initialize the Partition Table with no entries */
755 memset((void *)partition_tb, 0, patb_size);
756 partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size);
758 * FIXME!! This should be done via update_partition table
759 * For now UPRT is 0 for us.
761 partition_tb->patb1 = 0;
762 pr_info("Partition table %p\n", partition_tb);
763 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
764 update_hid_for_hash();
766 * update partition table control register,
769 mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
773 static void __init htab_initialize(void)
776 unsigned long pteg_count;
778 unsigned long base = 0, size = 0;
779 struct memblock_region *reg;
781 DBG(" -> htab_initialize()\n");
783 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
784 mmu_kernel_ssize = MMU_SEGSIZE_1T;
785 mmu_highuser_ssize = MMU_SEGSIZE_1T;
786 printk(KERN_INFO "Using 1TB segments\n");
790 * Calculate the required size of the htab. We want the number of
791 * PTEGs to equal one half the number of real pages.
793 htab_size_bytes = htab_get_table_size();
794 pteg_count = htab_size_bytes >> 7;
796 htab_hash_mask = pteg_count - 1;
798 if (firmware_has_feature(FW_FEATURE_LPAR) ||
799 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
800 /* Using a hypervisor which owns the htab */
803 #ifdef CONFIG_FA_DUMP
805 * If firmware assisted dump is active firmware preserves
806 * the contents of htab along with entire partition memory.
807 * Clear the htab if firmware assisted dump is active so
808 * that we dont end up using old mappings.
810 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
811 mmu_hash_ops.hpte_clear_all();
814 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
816 #ifdef CONFIG_PPC_CELL
818 * Cell may require the hash table down low when using the
819 * Axon IOMMU in order to fit the dynamic region over it, see
820 * comments in cell/iommu.c
822 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
824 pr_info("Hash table forced below 2G for Axon IOMMU\n");
826 #endif /* CONFIG_PPC_CELL */
828 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
831 DBG("Hash table allocated at %lx, size: %lx\n", table,
834 htab_address = __va(table);
836 /* htab absolute addr + encoded htabsize */
837 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
839 /* Initialize the HPT with no entries */
840 memset((void *)table, 0, htab_size_bytes);
842 if (!cpu_has_feature(CPU_FTR_ARCH_300))
844 mtspr(SPRN_SDR1, _SDR1);
846 hash_init_partition_table(table, htab_size_bytes);
849 prot = pgprot_val(PAGE_KERNEL);
851 #ifdef CONFIG_DEBUG_PAGEALLOC
852 if (debug_pagealloc_enabled()) {
853 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
854 linear_map_hash_slots = __va(memblock_alloc_base(
855 linear_map_hash_count, 1, ppc64_rma_size));
856 memset(linear_map_hash_slots, 0, linear_map_hash_count);
858 #endif /* CONFIG_DEBUG_PAGEALLOC */
860 /* On U3 based machines, we need to reserve the DART area and
861 * _NOT_ map it to avoid cache paradoxes as it's remapped non
865 /* create bolted the linear mapping in the hash table */
866 for_each_memblock(memory, reg) {
867 base = (unsigned long)__va(reg->base);
870 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
873 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
874 prot, mmu_linear_psize, mmu_kernel_ssize));
876 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
879 * If we have a memory_limit and we've allocated TCEs then we need to
880 * explicitly map the TCE area at the top of RAM. We also cope with the
881 * case that the TCEs start below memory_limit.
882 * tce_alloc_start/end are 16MB aligned so the mapping should work
883 * for either 4K or 16MB pages.
885 if (tce_alloc_start) {
886 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
887 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
889 if (base + size >= tce_alloc_start)
890 tce_alloc_start = base + size + 1;
892 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
893 __pa(tce_alloc_start), prot,
894 mmu_linear_psize, mmu_kernel_ssize));
898 DBG(" <- htab_initialize()\n");
903 void __init hash__early_init_devtree(void)
905 /* Initialize segment sizes */
906 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
908 /* Initialize page sizes */
909 htab_scan_page_sizes();
912 void __init hash__early_init_mmu(void)
914 htab_init_page_sizes();
917 * initialize page table size
919 __pte_frag_nr = H_PTE_FRAG_NR;
920 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
922 __pte_index_size = H_PTE_INDEX_SIZE;
923 __pmd_index_size = H_PMD_INDEX_SIZE;
924 __pud_index_size = H_PUD_INDEX_SIZE;
925 __pgd_index_size = H_PGD_INDEX_SIZE;
926 __pmd_cache_index = H_PMD_CACHE_INDEX;
927 __pte_table_size = H_PTE_TABLE_SIZE;
928 __pmd_table_size = H_PMD_TABLE_SIZE;
929 __pud_table_size = H_PUD_TABLE_SIZE;
930 __pgd_table_size = H_PGD_TABLE_SIZE;
932 * 4k use hugepd format, so for hash set then to
939 __kernel_virt_start = H_KERN_VIRT_START;
940 __kernel_virt_size = H_KERN_VIRT_SIZE;
941 __vmalloc_start = H_VMALLOC_START;
942 __vmalloc_end = H_VMALLOC_END;
943 vmemmap = (struct page *)H_VMEMMAP_BASE;
944 ioremap_bot = IOREMAP_BASE;
947 pci_io_base = ISA_IO_BASE;
950 /* Select appropriate backend */
951 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
953 else if (firmware_has_feature(FW_FEATURE_LPAR))
955 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
958 if (!mmu_hash_ops.hpte_insert)
959 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
961 /* Initialize the MMU Hash table and create the linear mapping
962 * of memory. Has to be done before SLB initialization as this is
963 * currently where the page size encoding is obtained.
967 pr_info("Initializing hash mmu with SLB\n");
968 /* Initialize SLB management */
973 void hash__early_init_mmu_secondary(void)
975 /* Initialize hash table for that CPU */
976 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
977 if (!cpu_has_feature(CPU_FTR_ARCH_300))
978 mtspr(SPRN_SDR1, _SDR1);
981 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
986 #endif /* CONFIG_SMP */
989 * Called by asm hashtable.S for doing lazy icache flush
991 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
995 if (!pfn_valid(pte_pfn(pte)))
998 page = pte_page(pte);
1001 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1002 if (trap == 0x400) {
1003 flush_dcache_icache_page(page);
1004 set_bit(PG_arch_1, &page->flags);
1011 #ifdef CONFIG_PPC_MM_SLICES
1012 static unsigned int get_paca_psize(unsigned long addr)
1015 unsigned char *hpsizes;
1016 unsigned long index, mask_index;
1018 if (addr < SLICE_LOW_TOP) {
1019 lpsizes = get_paca()->mm_ctx_low_slices_psize;
1020 index = GET_LOW_SLICE_INDEX(addr);
1021 return (lpsizes >> (index * 4)) & 0xF;
1023 hpsizes = get_paca()->mm_ctx_high_slices_psize;
1024 index = GET_HIGH_SLICE_INDEX(addr);
1025 mask_index = index & 0x1;
1026 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
1030 unsigned int get_paca_psize(unsigned long addr)
1032 return get_paca()->mm_ctx_user_psize;
1037 * Demote a segment to using 4k pages.
1038 * For now this makes the whole process use 4k pages.
1040 #ifdef CONFIG_PPC_64K_PAGES
1041 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1043 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1045 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1046 copro_flush_all_slbs(mm);
1047 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1049 copy_mm_to_paca(&mm->context);
1050 slb_flush_and_rebolt();
1053 #endif /* CONFIG_PPC_64K_PAGES */
1055 #ifdef CONFIG_PPC_SUBPAGE_PROT
1057 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1058 * Userspace sets the subpage permissions using the subpage_prot system call.
1060 * Result is 0: full permissions, _PAGE_RW: read-only,
1061 * _PAGE_RWX: no access.
1063 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1065 struct subpage_prot_table *spt = &mm->context.spt;
1069 if (ea >= spt->maxaddr)
1071 if (ea < 0x100000000UL) {
1072 /* addresses below 4GB use spt->low_prot */
1073 sbpm = spt->low_prot;
1075 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1079 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1082 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1084 /* extract 2-bit bitfield for this 4k subpage */
1085 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1088 * 0 -> full premission
1091 * We return the flag that need to be cleared.
1093 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1097 #else /* CONFIG_PPC_SUBPAGE_PROT */
1098 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1104 void hash_failure_debug(unsigned long ea, unsigned long access,
1105 unsigned long vsid, unsigned long trap,
1106 int ssize, int psize, int lpsize, unsigned long pte)
1108 if (!printk_ratelimit())
1110 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1111 ea, access, current->comm);
1112 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1113 trap, vsid, ssize, psize, lpsize, pte);
1116 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1117 int psize, bool user_region)
1120 if (psize != get_paca_psize(ea)) {
1121 copy_mm_to_paca(&mm->context);
1122 slb_flush_and_rebolt();
1124 } else if (get_paca()->vmalloc_sllp !=
1125 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1126 get_paca()->vmalloc_sllp =
1127 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1128 slb_vmalloc_update();
1134 * 1 - normal page fault
1135 * -1 - critical hash insertion error
1136 * -2 - access not permitted by subpage protection mechanism
1138 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1139 unsigned long access, unsigned long trap,
1140 unsigned long flags)
1143 enum ctx_state prev_state = exception_enter();
1148 const struct cpumask *tmp;
1149 int rc, user_region = 0;
1152 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1154 trace_hash_fault(ea, access, trap);
1156 /* Get region & vsid */
1157 switch (REGION_ID(ea)) {
1158 case USER_REGION_ID:
1161 DBG_LOW(" user region with no mm !\n");
1165 psize = get_slice_psize(mm, ea);
1166 ssize = user_segment_size(ea);
1167 vsid = get_vsid(mm->context.id, ea, ssize);
1169 case VMALLOC_REGION_ID:
1170 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1171 if (ea < VMALLOC_END)
1172 psize = mmu_vmalloc_psize;
1174 psize = mmu_io_psize;
1175 ssize = mmu_kernel_ssize;
1178 /* Not a valid range
1179 * Send the problem up to do_page_fault
1184 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1188 DBG_LOW("Bad address!\n");
1194 if (pgdir == NULL) {
1199 /* Check CPU locality */
1200 tmp = cpumask_of(smp_processor_id());
1201 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1202 flags |= HPTE_LOCAL_UPDATE;
1204 #ifndef CONFIG_PPC_64K_PAGES
1205 /* If we use 4K pages and our psize is not 4K, then we might
1206 * be hitting a special driver mapping, and need to align the
1207 * address before we fetch the PTE.
1209 * It could also be a hugepage mapping, in which case this is
1210 * not necessary, but it's not harmful, either.
1212 if (psize != MMU_PAGE_4K)
1213 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1214 #endif /* CONFIG_PPC_64K_PAGES */
1216 /* Get PTE and page size from page tables */
1217 ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1218 if (ptep == NULL || !pte_present(*ptep)) {
1219 DBG_LOW(" no PTE !\n");
1224 /* Add _PAGE_PRESENT to the required access perm */
1225 access |= _PAGE_PRESENT;
1227 /* Pre-check access permissions (will be re-checked atomically
1228 * in __hash_page_XX but this pre-check is a fast path
1230 if (!check_pte_access(access, pte_val(*ptep))) {
1231 DBG_LOW(" no access !\n");
1238 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1239 trap, flags, ssize, psize);
1240 #ifdef CONFIG_HUGETLB_PAGE
1242 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1243 flags, ssize, hugeshift, psize);
1247 * if we have hugeshift, and is not transhuge with
1248 * hugetlb disabled, something is really wrong.
1254 if (current->mm == mm)
1255 check_paca_psize(ea, mm, psize, user_region);
1260 #ifndef CONFIG_PPC_64K_PAGES
1261 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1263 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1264 pte_val(*(ptep + PTRS_PER_PTE)));
1266 /* Do actual hashing */
1267 #ifdef CONFIG_PPC_64K_PAGES
1268 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1269 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1270 demote_segment_4k(mm, ea);
1271 psize = MMU_PAGE_4K;
1274 /* If this PTE is non-cacheable and we have restrictions on
1275 * using non cacheable large pages, then we switch to 4k
1277 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1279 demote_segment_4k(mm, ea);
1280 psize = MMU_PAGE_4K;
1281 } else if (ea < VMALLOC_END) {
1283 * some driver did a non-cacheable mapping
1284 * in vmalloc space, so switch vmalloc
1287 printk(KERN_ALERT "Reducing vmalloc segment "
1288 "to 4kB pages because of "
1289 "non-cacheable mapping\n");
1290 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1291 copro_flush_all_slbs(mm);
1295 #endif /* CONFIG_PPC_64K_PAGES */
1297 if (current->mm == mm)
1298 check_paca_psize(ea, mm, psize, user_region);
1300 #ifdef CONFIG_PPC_64K_PAGES
1301 if (psize == MMU_PAGE_64K)
1302 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1305 #endif /* CONFIG_PPC_64K_PAGES */
1307 int spp = subpage_protection(mm, ea);
1311 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1315 /* Dump some info in case of hash insertion failure, they should
1316 * never happen so it is really useful to know if/when they do
1319 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1320 psize, pte_val(*ptep));
1321 #ifndef CONFIG_PPC_64K_PAGES
1322 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1324 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1325 pte_val(*(ptep + PTRS_PER_PTE)));
1327 DBG_LOW(" -> rc=%d\n", rc);
1330 exception_exit(prev_state);
1333 EXPORT_SYMBOL_GPL(hash_page_mm);
1335 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1336 unsigned long dsisr)
1338 unsigned long flags = 0;
1339 struct mm_struct *mm = current->mm;
1341 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1344 if (dsisr & DSISR_NOHPTE)
1345 flags |= HPTE_NOHPTE_UPDATE;
1347 return hash_page_mm(mm, ea, access, trap, flags);
1349 EXPORT_SYMBOL_GPL(hash_page);
1351 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1352 unsigned long dsisr)
1354 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1355 unsigned long flags = 0;
1356 struct mm_struct *mm = current->mm;
1358 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1361 if (dsisr & DSISR_NOHPTE)
1362 flags |= HPTE_NOHPTE_UPDATE;
1364 if (dsisr & DSISR_ISSTORE)
1365 access |= _PAGE_WRITE;
1367 * We set _PAGE_PRIVILEGED only when
1368 * kernel mode access kernel space.
1370 * _PAGE_PRIVILEGED is NOT set
1371 * 1) when kernel mode access user space
1372 * 2) user space access kernel space.
1374 access |= _PAGE_PRIVILEGED;
1375 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1376 access &= ~_PAGE_PRIVILEGED;
1379 access |= _PAGE_EXEC;
1381 return hash_page_mm(mm, ea, access, trap, flags);
1384 #ifdef CONFIG_PPC_MM_SLICES
1385 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1387 int psize = get_slice_psize(mm, ea);
1389 /* We only prefault standard pages for now */
1390 if (unlikely(psize != mm->context.user_psize))
1394 * Don't prefault if subpage protection is enabled for the EA.
1396 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1402 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1408 void hash_preload(struct mm_struct *mm, unsigned long ea,
1409 unsigned long access, unsigned long trap)
1415 unsigned long flags;
1416 int rc, ssize, update_flags = 0;
1418 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1420 if (!should_hash_preload(mm, ea))
1423 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1424 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1426 /* Get Linux PTE if available */
1432 ssize = user_segment_size(ea);
1433 vsid = get_vsid(mm->context.id, ea, ssize);
1437 * Hash doesn't like irqs. Walking linux page table with irq disabled
1438 * saves us from holding multiple locks.
1440 local_irq_save(flags);
1443 * THP pages use update_mmu_cache_pmd. We don't do
1444 * hash preload there. Hence can ignore THP here
1446 ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1450 WARN_ON(hugepage_shift);
1451 #ifdef CONFIG_PPC_64K_PAGES
1452 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1453 * a 64K kernel), then we don't preload, hash_page() will take
1454 * care of it once we actually try to access the page.
1455 * That way we don't have to duplicate all of the logic for segment
1456 * page size demotion here
1458 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1460 #endif /* CONFIG_PPC_64K_PAGES */
1462 /* Is that local to this CPU ? */
1463 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1464 update_flags |= HPTE_LOCAL_UPDATE;
1467 #ifdef CONFIG_PPC_64K_PAGES
1468 if (mm->context.user_psize == MMU_PAGE_64K)
1469 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1470 update_flags, ssize);
1472 #endif /* CONFIG_PPC_64K_PAGES */
1473 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1474 ssize, subpage_protection(mm, ea));
1476 /* Dump some info in case of hash insertion failure, they should
1477 * never happen so it is really useful to know if/when they do
1480 hash_failure_debug(ea, access, vsid, trap, ssize,
1481 mm->context.user_psize,
1482 mm->context.user_psize,
1485 local_irq_restore(flags);
1488 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1489 static inline void tm_flush_hash_page(int local)
1492 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1493 * page back to a block device w/PIO could pick up transactional data
1494 * (bad!) so we force an abort here. Before the sync the page will be
1495 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1496 * kernel uses a page from userspace without unmapping it first, it may
1497 * see the speculated version.
1499 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1500 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1502 tm_abort(TM_CAUSE_TLBI);
1506 static inline void tm_flush_hash_page(int local)
1511 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1512 * do not forget to update the assembly call site !
1514 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1515 unsigned long flags)
1517 unsigned long hash, index, shift, hidx, slot;
1518 int local = flags & HPTE_LOCAL_UPDATE;
1520 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1521 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1522 hash = hpt_hash(vpn, shift, ssize);
1523 hidx = __rpte_to_hidx(pte, index);
1524 if (hidx & _PTEIDX_SECONDARY)
1526 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1527 slot += hidx & _PTEIDX_GROUP_IX;
1528 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1530 * We use same base page size and actual psize, because we don't
1531 * use these functions for hugepage
1533 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,
1535 } pte_iterate_hashed_end();
1537 tm_flush_hash_page(local);
1540 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1541 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1542 pmd_t *pmdp, unsigned int psize, int ssize,
1543 unsigned long flags)
1545 int i, max_hpte_count, valid;
1546 unsigned long s_addr;
1547 unsigned char *hpte_slot_array;
1548 unsigned long hidx, shift, vpn, hash, slot;
1549 int local = flags & HPTE_LOCAL_UPDATE;
1551 s_addr = addr & HPAGE_PMD_MASK;
1552 hpte_slot_array = get_hpte_slot_array(pmdp);
1554 * IF we try to do a HUGE PTE update after a withdraw is done.
1555 * we will find the below NULL. This happens when we do
1556 * split_huge_page_pmd
1558 if (!hpte_slot_array)
1561 if (mmu_hash_ops.hugepage_invalidate) {
1562 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1563 psize, ssize, local);
1567 * No bluk hpte removal support, invalidate each entry
1569 shift = mmu_psize_defs[psize].shift;
1570 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1571 for (i = 0; i < max_hpte_count; i++) {
1573 * 8 bits per each hpte entries
1574 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1576 valid = hpte_valid(hpte_slot_array, i);
1579 hidx = hpte_hash_index(hpte_slot_array, i);
1582 addr = s_addr + (i * (1ul << shift));
1583 vpn = hpt_vpn(addr, vsid, ssize);
1584 hash = hpt_hash(vpn, shift, ssize);
1585 if (hidx & _PTEIDX_SECONDARY)
1588 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1589 slot += hidx & _PTEIDX_GROUP_IX;
1590 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1591 MMU_PAGE_16M, ssize, local);
1594 tm_flush_hash_page(local);
1596 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1598 void flush_hash_range(unsigned long number, int local)
1600 if (mmu_hash_ops.flush_hash_range)
1601 mmu_hash_ops.flush_hash_range(number, local);
1604 struct ppc64_tlb_batch *batch =
1605 this_cpu_ptr(&ppc64_tlb_batch);
1607 for (i = 0; i < number; i++)
1608 flush_hash_page(batch->vpn[i], batch->pte[i],
1609 batch->psize, batch->ssize, local);
1614 * low_hash_fault is called when we the low level hash code failed
1615 * to instert a PTE due to an hypervisor error
1617 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1619 enum ctx_state prev_state = exception_enter();
1621 if (user_mode(regs)) {
1622 #ifdef CONFIG_PPC_SUBPAGE_PROT
1624 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1627 _exception(SIGBUS, regs, BUS_ADRERR, address);
1629 bad_page_fault(regs, address, SIGBUS);
1631 exception_exit(prev_state);
1634 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1635 unsigned long pa, unsigned long rflags,
1636 unsigned long vflags, int psize, int ssize)
1638 unsigned long hpte_group;
1642 hpte_group = ((hash & htab_hash_mask) *
1643 HPTES_PER_GROUP) & ~0x7UL;
1645 /* Insert into the hash table, primary slot */
1646 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1647 psize, psize, ssize);
1649 /* Primary is full, try the secondary */
1650 if (unlikely(slot == -1)) {
1651 hpte_group = ((~hash & htab_hash_mask) *
1652 HPTES_PER_GROUP) & ~0x7UL;
1653 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1654 vflags | HPTE_V_SECONDARY,
1655 psize, psize, ssize);
1658 hpte_group = ((hash & htab_hash_mask) *
1659 HPTES_PER_GROUP)&~0x7UL;
1661 mmu_hash_ops.hpte_remove(hpte_group);
1669 #ifdef CONFIG_DEBUG_PAGEALLOC
1670 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1673 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1674 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1675 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1678 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1680 /* Don't create HPTE entries for bad address */
1684 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1686 mmu_linear_psize, mmu_kernel_ssize);
1689 spin_lock(&linear_map_hash_lock);
1690 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1691 linear_map_hash_slots[lmi] = ret | 0x80;
1692 spin_unlock(&linear_map_hash_lock);
1695 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1697 unsigned long hash, hidx, slot;
1698 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1699 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1701 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1702 spin_lock(&linear_map_hash_lock);
1703 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1704 hidx = linear_map_hash_slots[lmi] & 0x7f;
1705 linear_map_hash_slots[lmi] = 0;
1706 spin_unlock(&linear_map_hash_lock);
1707 if (hidx & _PTEIDX_SECONDARY)
1709 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1710 slot += hidx & _PTEIDX_GROUP_IX;
1711 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1713 mmu_kernel_ssize, 0);
1716 void __kernel_map_pages(struct page *page, int numpages, int enable)
1718 unsigned long flags, vaddr, lmi;
1721 local_irq_save(flags);
1722 for (i = 0; i < numpages; i++, page++) {
1723 vaddr = (unsigned long)page_address(page);
1724 lmi = __pa(vaddr) >> PAGE_SHIFT;
1725 if (lmi >= linear_map_hash_count)
1728 kernel_map_linear_page(vaddr, lmi);
1730 kernel_unmap_linear_page(vaddr, lmi);
1732 local_irq_restore(flags);
1734 #endif /* CONFIG_DEBUG_PAGEALLOC */
1736 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1737 phys_addr_t first_memblock_size)
1739 /* We don't currently support the first MEMBLOCK not mapping 0
1740 * physical on those processors
1742 BUG_ON(first_memblock_base != 0);
1744 /* On LPAR systems, the first entry is our RMA region,
1745 * non-LPAR 64-bit hash MMU systems don't have a limitation
1746 * on real mode access, but using the first entry works well
1747 * enough. We also clamp it to 1G to avoid some funky things
1748 * such as RTAS bugs etc...
1750 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1752 /* Finally limit subsequent allocations */
1753 memblock_set_current_limit(ppc64_rma_size);