arch/powerpc/mm/hash_utils_64.c

   1 /*
   2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   3  *   {mikejc|engebret}@us.ibm.com
   4  *
   5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   6  *
   7  * SMP scalability work:
   8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *    Module name: htab.c
  11  *
  12  *    Description:
  13  *      PowerPC Hashed Page Table functions
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  */
  20
  21 #undef DEBUG
  22 #undef DEBUG_LOW
  23
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/sched.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/stat.h>
  29 #include <linux/sysctl.h>
  30 #include <linux/export.h>
  31 #include <linux/ctype.h>
  32 #include <linux/cache.h>
  33 #include <linux/init.h>
  34 #include <linux/signal.h>
  35 #include <linux/memblock.h>
  36 #include <linux/context_tracking.h>
  37
  38 #include <asm/processor.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/mmu.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/page.h>
  43 #include <asm/types.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/machdep.h>
  46 #include <asm/prom.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/io.h>
  49 #include <asm/eeh.h>
  50 #include <asm/tlb.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/cputable.h>
  53 #include <asm/sections.h>
  54 #include <asm/spu.h>
  55 #include <asm/udbg.h>
  56 #include <asm/code-patching.h>
  57 #include <asm/fadump.h>
  58 #include <asm/firmware.h>
  59 #include <asm/tm.h>
  60
  61 #ifdef DEBUG
  62 #define DBG(fmt...) udbg_printf(fmt)
  63 #else
  64 #define DBG(fmt...)
  65 #endif
  66
  67 #ifdef DEBUG_LOW
  68 #define DBG_LOW(fmt...) udbg_printf(fmt)
  69 #else
  70 #define DBG_LOW(fmt...)
  71 #endif
  72
  73 #define KB (1024)
  74 #define MB (1024*KB)
  75 #define GB (1024L*MB)
  76
  77 /*
  78  * Note:  pte   --> Linux PTE
  79  *        HPTE  --> PowerPC Hashed Page Table Entry
  80  *
  81  * Execution context:
  82  *   htab_initialize is called with the MMU off (of course), but
  83  *   the kernel has been copied down to zero so it can directly
  84  *   reference global data.  At this point it is very difficult
  85  *   to print debug info.
  86  *
  87  */
  88
  89 #ifdef CONFIG_U3_DART
  90 extern unsigned long dart_tablebase;
  91 #endif /* CONFIG_U3_DART */
  92
  93 static unsigned long _SDR1;
  94 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  95
  96 struct hash_pte *htab_address;
  97 unsigned long htab_size_bytes;
  98 unsigned long htab_hash_mask;
  99 EXPORT_SYMBOL_GPL(htab_hash_mask);
 100 int mmu_linear_psize = MMU_PAGE_4K;
 101 int mmu_virtual_psize = MMU_PAGE_4K;
 102 int mmu_vmalloc_psize = MMU_PAGE_4K;
 103 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 104 int mmu_vmemmap_psize = MMU_PAGE_4K;
 105 #endif
 106 int mmu_io_psize = MMU_PAGE_4K;
 107 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 108 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
 109 u16 mmu_slb_size = 64;
 110 EXPORT_SYMBOL_GPL(mmu_slb_size);
 111 #ifdef CONFIG_PPC_64K_PAGES
 112 int mmu_ci_restrictions;
 113 #endif
 114 #ifdef CONFIG_DEBUG_PAGEALLOC
 115 static u8 *linear_map_hash_slots;
 116 static unsigned long linear_map_hash_count;
 117 static DEFINE_SPINLOCK(linear_map_hash_lock);
 118 #endif /* CONFIG_DEBUG_PAGEALLOC */
 119
 120 /* There are definitions of page sizes arrays to be used when none
 121  * is provided by the firmware.
 122  */
 123
 124 /* Pre-POWER4 CPUs (4k pages only)
 125  */
 126 static struct mmu_psize_def mmu_psize_defaults_old[] = {
 127         [MMU_PAGE_4K] = {
 128                 .shift  = 12,
 129                 .sllp   = 0,
 130                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
 131                 .avpnm  = 0,
 132                 .tlbiel = 0,
 133         },
 134 };
 135
 136 /* POWER4, GPUL, POWER5
 137  *
 138  * Support for 16Mb large pages
 139  */
 140 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
 141         [MMU_PAGE_4K] = {
 142                 .shift  = 12,
 143                 .sllp   = 0,
 144                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
 145                 .avpnm  = 0,
 146                 .tlbiel = 1,
 147         },
 148         [MMU_PAGE_16M] = {
 149                 .shift  = 24,
 150                 .sllp   = SLB_VSID_L,
 151                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
 152                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
 153                 .avpnm  = 0x1UL,
 154                 .tlbiel = 0,
 155         },
 156 };
 157
 158 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
 159 {
 160         unsigned long rflags = pteflags & 0x1fa;
 161
 162         /* _PAGE_EXEC -> NOEXEC */
 163         if ((pteflags & _PAGE_EXEC) == 0)
 164                 rflags |= HPTE_R_N;
 165
 166         /* PP bits. PAGE_USER is already PP bit 0x2, so we only
 167          * need to add in 0x1 if it's a read-only user page
 168          */
 169         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
 170                                          (pteflags & _PAGE_DIRTY)))
 171                 rflags |= 1;
 172         /*
 173          * Always add "C" bit for perf. Memory coherence is always enabled
 174          */
 175         return rflags | HPTE_R_C | HPTE_R_M;
 176 }
 177
 178 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 179                       unsigned long pstart, unsigned long prot,
 180                       int psize, int ssize)
 181 {
 182         unsigned long vaddr, paddr;
 183         unsigned int step, shift;
 184         int ret = 0;
 185
 186         shift = mmu_psize_defs[psize].shift;
 187         step = 1 << shift;
 188
 189         prot = htab_convert_pte_flags(prot);
 190
 191         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
 192             vstart, vend, pstart, prot, psize, ssize);
 193
 194         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 195              vaddr += step, paddr += step) {
 196                 unsigned long hash, hpteg;
 197                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
 198                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
 199                 unsigned long tprot = prot;
 200
 201                 /*
 202                  * If we hit a bad address return error.
 203                  */
 204                 if (!vsid)
 205                         return -1;
 206                 /* Make kernel text executable */
 207                 if (overlaps_kernel_text(vaddr, vaddr + step))
 208                         tprot &= ~HPTE_R_N;
 209
 210                 /*
 211                  * If relocatable, check if it overlaps interrupt vectors that
 212                  * are copied down to real 0. For relocatable kernel
 213                  * (e.g. kdump case) we copy interrupt vectors down to real
 214                  * address 0. Mark that region as executable. This is
 215                  * because on p8 system with relocation on exception feature
 216                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
 217                  * in order to execute the interrupt handlers in virtual
 218                  * mode the vector region need to be marked as executable.
 219                  */
 220                 if ((PHYSICAL_START > MEMORY_START) &&
 221                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
 222                                 tprot &= ~HPTE_R_N;
 223
 224                 hash = hpt_hash(vpn, shift, ssize);
 225                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 226
 227                 BUG_ON(!ppc_md.hpte_insert);
 228                 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
 229                                          HPTE_V_BOLTED, psize, psize, ssize);
 230
 231                 if (ret < 0)
 232                         break;
 233 #ifdef CONFIG_DEBUG_PAGEALLOC
 234                 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
 235                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
 236 #endif /* CONFIG_DEBUG_PAGEALLOC */
 237         }
 238         return ret < 0 ? ret : 0;
 239 }
 240
 241 #ifdef CONFIG_MEMORY_HOTPLUG
 242 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 243                       int psize, int ssize)
 244 {
 245         unsigned long vaddr;
 246         unsigned int step, shift;
 247
 248         shift = mmu_psize_defs[psize].shift;
 249         step = 1 << shift;
 250
 251         if (!ppc_md.hpte_removebolted) {
 252                 printk(KERN_WARNING "Platform doesn't implement "
 253                                 "hpte_removebolted\n");
 254                 return -EINVAL;
 255         }
 256
 257         for (vaddr = vstart; vaddr < vend; vaddr += step)
 258                 ppc_md.hpte_removebolted(vaddr, psize, ssize);
 259
 260         return 0;
 261 }
 262 #endif /* CONFIG_MEMORY_HOTPLUG */
 263
 264 static int __init htab_dt_scan_seg_sizes(unsigned long node,
 265                                          const char *uname, int depth,
 266                                          void *data)
 267 {
 268         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 269         __be32 *prop;
 270         unsigned long size = 0;
 271
 272         /* We are scanning "cpu" nodes only */
 273         if (type == NULL || strcmp(type, "cpu") != 0)
 274                 return 0;
 275
 276         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
 277         if (prop == NULL)
 278                 return 0;
 279         for (; size >= 4; size -= 4, ++prop) {
 280                 if (be32_to_cpu(prop[0]) == 40) {
 281                         DBG("1T segment support detected\n");
 282                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
 283                         return 1;
 284                 }
 285         }
 286         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 287         return 0;
 288 }
 289
 290 static void __init htab_init_seg_sizes(void)
 291 {
 292         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 293 }
 294
 295 static int __init get_idx_from_shift(unsigned int shift)
 296 {
 297         int idx = -1;
 298
 299         switch (shift) {
 300         case 0xc:
 301                 idx = MMU_PAGE_4K;
 302                 break;
 303         case 0x10:
 304                 idx = MMU_PAGE_64K;
 305                 break;
 306         case 0x14:
 307                 idx = MMU_PAGE_1M;
 308                 break;
 309         case 0x18:
 310                 idx = MMU_PAGE_16M;
 311                 break;
 312         case 0x22:
 313                 idx = MMU_PAGE_16G;
 314                 break;
 315         }
 316         return idx;
 317 }
 318
 319 static int __init htab_dt_scan_page_sizes(unsigned long node,
 320                                           const char *uname, int depth,
 321                                           void *data)
 322 {
 323         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 324         __be32 *prop;
 325         unsigned long size = 0;
 326
 327         /* We are scanning "cpu" nodes only */
 328         if (type == NULL || strcmp(type, "cpu") != 0)
 329                 return 0;
 330
 331         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
 332         if (prop != NULL) {
 333                 pr_info("Page sizes from device-tree:\n");
 334                 size /= 4;
 335                 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
 336                 while(size > 0) {
 337                         unsigned int base_shift = be32_to_cpu(prop[0]);
 338                         unsigned int slbenc = be32_to_cpu(prop[1]);
 339                         unsigned int lpnum = be32_to_cpu(prop[2]);
 340                         struct mmu_psize_def *def;
 341                         int idx, base_idx;
 342
 343                         size -= 3; prop += 3;
 344                         base_idx = get_idx_from_shift(base_shift);
 345                         if (base_idx < 0) {
 346                                 /*
 347                                  * skip the pte encoding also
 348                                  */
 349                                 prop += lpnum * 2; size -= lpnum * 2;
 350                                 continue;
 351                         }
 352                         def = &mmu_psize_defs[base_idx];
 353                         if (base_idx == MMU_PAGE_16M)
 354                                 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
 355
 356                         def->shift = base_shift;
 357                         if (base_shift <= 23)
 358                                 def->avpnm = 0;
 359                         else
 360                                 def->avpnm = (1 << (base_shift - 23)) - 1;
 361                         def->sllp = slbenc;
 362                         /*
 363                          * We don't know for sure what's up with tlbiel, so
 364                          * for now we only set it for 4K and 64K pages
 365                          */
 366                         if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
 367                                 def->tlbiel = 1;
 368                         else
 369                                 def->tlbiel = 0;
 370
 371                         while (size > 0 && lpnum) {
 372                                 unsigned int shift = be32_to_cpu(prop[0]);
 373                                 int penc  = be32_to_cpu(prop[1]);
 374
 375                                 prop += 2; size -= 2;
 376                                 lpnum--;
 377
 378                                 idx = get_idx_from_shift(shift);
 379                                 if (idx < 0)
 380                                         continue;
 381
 382                                 if (penc == -1)
 383                                         pr_err("Invalid penc for base_shift=%d "
 384                                                "shift=%d\n", base_shift, shift);
 385
 386                                 def->penc[idx] = penc;
 387                                 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
 388                                         " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
 389                                         base_shift, shift, def->sllp,
 390                                         def->avpnm, def->tlbiel, def->penc[idx]);
 391                         }
 392                 }
 393                 return 1;
 394         }
 395         return 0;
 396 }
 397
 398 #ifdef CONFIG_HUGETLB_PAGE
 399 /* Scan for 16G memory blocks that have been set aside for huge pages
 400  * and reserve those blocks for 16G huge pages.
 401  */
 402 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
 403                                         const char *uname, int depth,
 404                                         void *data) {
 405         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 406         __be64 *addr_prop;
 407         __be32 *page_count_prop;
 408         unsigned int expected_pages;
 409         long unsigned int phys_addr;
 410         long unsigned int block_size;
 411
 412         /* We are scanning "memory" nodes only */
 413         if (type == NULL || strcmp(type, "memory") != 0)
 414                 return 0;
 415
 416         /* This property is the log base 2 of the number of virtual pages that
 417          * will represent this memory block. */
 418         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
 419         if (page_count_prop == NULL)
 420                 return 0;
 421         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
 422         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
 423         if (addr_prop == NULL)
 424                 return 0;
 425         phys_addr = be64_to_cpu(addr_prop[0]);
 426         block_size = be64_to_cpu(addr_prop[1]);
 427         if (block_size != (16 * GB))
 428                 return 0;
 429         printk(KERN_INFO "Huge page(16GB) memory: "
 430                         "addr = 0x%lX size = 0x%lX pages = %d\n",
 431                         phys_addr, block_size, expected_pages);
 432         if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
 433                 memblock_reserve(phys_addr, block_size * expected_pages);
 434                 add_gpage(phys_addr, block_size, expected_pages);
 435         }
 436         return 0;
 437 }
 438 #endif /* CONFIG_HUGETLB_PAGE */
 439
 440 static void mmu_psize_set_default_penc(void)
 441 {
 442         int bpsize, apsize;
 443         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
 444                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
 445                         mmu_psize_defs[bpsize].penc[apsize] = -1;
 446 }
 447
 448 static void __init htab_init_page_sizes(void)
 449 {
 450         int rc;
 451
 452         /* se the invalid penc to -1 */
 453         mmu_psize_set_default_penc();
 454
 455         /* Default to 4K pages only */
 456         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 457                sizeof(mmu_psize_defaults_old));
 458
 459         /*
 460          * Try to find the available page sizes in the device-tree
 461          */
 462         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 463         if (rc != 0)  /* Found */
 464                 goto found;
 465
 466         /*
 467          * Not in the device-tree, let's fallback on known size
 468          * list for 16M capable GP & GR
 469          */
 470         if (mmu_has_feature(MMU_FTR_16M_PAGE))
 471                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 472                        sizeof(mmu_psize_defaults_gp));
 473  found:
 474 #ifndef CONFIG_DEBUG_PAGEALLOC
 475         /*
 476          * Pick a size for the linear mapping. Currently, we only support
 477          * 16M, 1M and 4K which is the default
 478          */
 479         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 480                 mmu_linear_psize = MMU_PAGE_16M;
 481         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 482                 mmu_linear_psize = MMU_PAGE_1M;
 483 #endif /* CONFIG_DEBUG_PAGEALLOC */
 484
 485 #ifdef CONFIG_PPC_64K_PAGES
 486         /*
 487          * Pick a size for the ordinary pages. Default is 4K, we support
 488          * 64K for user mappings and vmalloc if supported by the processor.
 489          * We only use 64k for ioremap if the processor
 490          * (and firmware) support cache-inhibited large pages.
 491          * If not, we use 4k and set mmu_ci_restrictions so that
 492          * hash_page knows to switch processes that use cache-inhibited
 493          * mappings to 4k pages.
 494          */
 495         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 496                 mmu_virtual_psize = MMU_PAGE_64K;
 497                 mmu_vmalloc_psize = MMU_PAGE_64K;
 498                 if (mmu_linear_psize == MMU_PAGE_4K)
 499                         mmu_linear_psize = MMU_PAGE_64K;
 500                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
 501                         /*
 502                          * Don't use 64k pages for ioremap on pSeries, since
 503                          * that would stop us accessing the HEA ethernet.
 504                          */
 505                         if (!machine_is(pseries))
 506                                 mmu_io_psize = MMU_PAGE_64K;
 507                 } else
 508                         mmu_ci_restrictions = 1;
 509         }
 510 #endif /* CONFIG_PPC_64K_PAGES */
 511
 512 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 513         /* We try to use 16M pages for vmemmap if that is supported
 514          * and we have at least 1G of RAM at boot
 515          */
 516         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
 517             memblock_phys_mem_size() >= 0x40000000)
 518                 mmu_vmemmap_psize = MMU_PAGE_16M;
 519         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
 520                 mmu_vmemmap_psize = MMU_PAGE_64K;
 521         else
 522                 mmu_vmemmap_psize = MMU_PAGE_4K;
 523 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 524
 525         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 526                "virtual = %d, io = %d"
 527 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 528                ", vmemmap = %d"
 529 #endif
 530                "\n",
 531                mmu_psize_defs[mmu_linear_psize].shift,
 532                mmu_psize_defs[mmu_virtual_psize].shift,
 533                mmu_psize_defs[mmu_io_psize].shift
 534 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 535                ,mmu_psize_defs[mmu_vmemmap_psize].shift
 536 #endif
 537                );
 538
 539 #ifdef CONFIG_HUGETLB_PAGE
 540         /* Reserve 16G huge page memory sections for huge pages */
 541         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
 542 #endif /* CONFIG_HUGETLB_PAGE */
 543 }
 544
 545 static int __init htab_dt_scan_pftsize(unsigned long node,
 546                                        const char *uname, int depth,
 547                                        void *data)
 548 {
 549         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 550         __be32 *prop;
 551
 552         /* We are scanning "cpu" nodes only */
 553         if (type == NULL || strcmp(type, "cpu") != 0)
 554                 return 0;
 555
 556         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 557         if (prop != NULL) {
 558                 /* pft_size[0] is the NUMA CEC cookie */
 559                 ppc64_pft_size = be32_to_cpu(prop[1]);
 560                 return 1;
 561         }
 562         return 0;
 563 }
 564
 565 static unsigned long __init htab_get_table_size(void)
 566 {
 567         unsigned long mem_size, rnd_mem_size, pteg_count, psize;
 568
 569         /* If hash size isn't already provided by the platform, we try to
 570          * retrieve it from the device-tree. If it's not there neither, we
 571          * calculate it now based on the total RAM size
 572          */
 573         if (ppc64_pft_size == 0)
 574                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 575         if (ppc64_pft_size)
 576                 return 1UL << ppc64_pft_size;
 577
 578         /* round mem_size up to next power of 2 */
 579         mem_size = memblock_phys_mem_size();
 580         rnd_mem_size = 1UL << __ilog2(mem_size);
 581         if (rnd_mem_size < mem_size)
 582                 rnd_mem_size <<= 1;
 583
 584         /* # pages / 2 */
 585         psize = mmu_psize_defs[mmu_virtual_psize].shift;
 586         pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
 587
 588         return pteg_count << 7;
 589 }
 590
 591 #ifdef CONFIG_MEMORY_HOTPLUG
 592 int create_section_mapping(unsigned long start, unsigned long end)
 593 {
 594         return htab_bolt_mapping(start, end, __pa(start),
 595                                  pgprot_val(PAGE_KERNEL), mmu_linear_psize,
 596                                  mmu_kernel_ssize);
 597 }
 598
 599 int remove_section_mapping(unsigned long start, unsigned long end)
 600 {
 601         return htab_remove_mapping(start, end, mmu_linear_psize,
 602                         mmu_kernel_ssize);
 603 }
 604 #endif /* CONFIG_MEMORY_HOTPLUG */
 605
 606 #define FUNCTION_TEXT(A)        ((*(unsigned long *)(A)))
 607
 608 static void __init htab_finish_init(void)
 609 {
 610         extern unsigned int *htab_call_hpte_insert1;
 611         extern unsigned int *htab_call_hpte_insert2;
 612         extern unsigned int *htab_call_hpte_remove;
 613         extern unsigned int *htab_call_hpte_updatepp;
 614
 615 #ifdef CONFIG_PPC_HAS_HASH_64K
 616         extern unsigned int *ht64_call_hpte_insert1;
 617         extern unsigned int *ht64_call_hpte_insert2;
 618         extern unsigned int *ht64_call_hpte_remove;
 619         extern unsigned int *ht64_call_hpte_updatepp;
 620
 621         patch_branch(ht64_call_hpte_insert1,
 622                 FUNCTION_TEXT(ppc_md.hpte_insert),
 623                 BRANCH_SET_LINK);
 624         patch_branch(ht64_call_hpte_insert2,
 625                 FUNCTION_TEXT(ppc_md.hpte_insert),
 626                 BRANCH_SET_LINK);
 627         patch_branch(ht64_call_hpte_remove,
 628                 FUNCTION_TEXT(ppc_md.hpte_remove),
 629                 BRANCH_SET_LINK);
 630         patch_branch(ht64_call_hpte_updatepp,
 631                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 632                 BRANCH_SET_LINK);
 633
 634 #endif /* CONFIG_PPC_HAS_HASH_64K */
 635
 636         patch_branch(htab_call_hpte_insert1,
 637                 FUNCTION_TEXT(ppc_md.hpte_insert),
 638                 BRANCH_SET_LINK);
 639         patch_branch(htab_call_hpte_insert2,
 640                 FUNCTION_TEXT(ppc_md.hpte_insert),
 641                 BRANCH_SET_LINK);
 642         patch_branch(htab_call_hpte_remove,
 643                 FUNCTION_TEXT(ppc_md.hpte_remove),
 644                 BRANCH_SET_LINK);
 645         patch_branch(htab_call_hpte_updatepp,
 646                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 647                 BRANCH_SET_LINK);
 648 }
 649
 650 static void __init htab_initialize(void)
 651 {
 652         unsigned long table;
 653         unsigned long pteg_count;
 654         unsigned long prot;
 655         unsigned long base = 0, size = 0, limit;
 656         struct memblock_region *reg;
 657
 658         DBG(" -> htab_initialize()\n");
 659
 660         /* Initialize segment sizes */
 661         htab_init_seg_sizes();
 662
 663         /* Initialize page sizes */
 664         htab_init_page_sizes();
 665
 666         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
 667                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
 668                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
 669                 printk(KERN_INFO "Using 1TB segments\n");
 670         }
 671
 672         /*
 673          * Calculate the required size of the htab.  We want the number of
 674          * PTEGs to equal one half the number of real pages.
 675          */
 676         htab_size_bytes = htab_get_table_size();
 677         pteg_count = htab_size_bytes >> 7;
 678
 679         htab_hash_mask = pteg_count - 1;
 680
 681         if (firmware_has_feature(FW_FEATURE_LPAR)) {
 682                 /* Using a hypervisor which owns the htab */
 683                 htab_address = NULL;
 684                 _SDR1 = 0;
 685 #ifdef CONFIG_FA_DUMP
 686                 /*
 687                  * If firmware assisted dump is active firmware preserves
 688                  * the contents of htab along with entire partition memory.
 689                  * Clear the htab if firmware assisted dump is active so
 690                  * that we dont end up using old mappings.
 691                  */
 692                 if (is_fadump_active() && ppc_md.hpte_clear_all)
 693                         ppc_md.hpte_clear_all();
 694 #endif
 695         } else {
 696                 /* Find storage for the HPT.  Must be contiguous in
 697                  * the absolute address space. On cell we want it to be
 698                  * in the first 2 Gig so we can use it for IOMMU hacks.
 699                  */
 700                 if (machine_is(cell))
 701                         limit = 0x80000000;
 702                 else
 703                         limit = MEMBLOCK_ALLOC_ANYWHERE;
 704
 705                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
 706
 707                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 708                     htab_size_bytes);
 709
 710                 htab_address = __va(table);
 711
 712                 /* htab absolute addr + encoded htabsize */
 713                 _SDR1 = table + __ilog2(pteg_count) - 11;
 714
 715                 /* Initialize the HPT with no entries */
 716                 memset((void *)table, 0, htab_size_bytes);
 717
 718                 /* Set SDR1 */
 719                 mtspr(SPRN_SDR1, _SDR1);
 720         }
 721
 722         prot = pgprot_val(PAGE_KERNEL);
 723
 724 #ifdef CONFIG_DEBUG_PAGEALLOC
 725         linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
 726         linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
 727                                                     1, ppc64_rma_size));
 728         memset(linear_map_hash_slots, 0, linear_map_hash_count);
 729 #endif /* CONFIG_DEBUG_PAGEALLOC */
 730
 731         /* On U3 based machines, we need to reserve the DART area and
 732          * _NOT_ map it to avoid cache paradoxes as it's remapped non
 733          * cacheable later on
 734          */
 735
 736         /* create bolted the linear mapping in the hash table */
 737         for_each_memblock(memory, reg) {
 738                 base = (unsigned long)__va(reg->base);
 739                 size = reg->size;
 740
 741                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
 742                     base, size, prot);
 743
 744 #ifdef CONFIG_U3_DART
 745                 /* Do not map the DART space. Fortunately, it will be aligned
 746                  * in such a way that it will not cross two memblock regions and
 747                  * will fit within a single 16Mb page.
 748                  * The DART space is assumed to be a full 16Mb region even if
 749                  * we only use 2Mb of that space. We will use more of it later
 750                  * for AGP GART. We have to use a full 16Mb large page.
 751                  */
 752                 DBG("DART base: %lx\n", dart_tablebase);
 753
 754                 if (dart_tablebase != 0 && dart_tablebase >= base
 755                     && dart_tablebase < (base + size)) {
 756                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
 757                         if (base != dart_tablebase)
 758                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
 759                                                         __pa(base), prot,
 760                                                         mmu_linear_psize,
 761                                                         mmu_kernel_ssize));
 762                         if ((base + size) > dart_table_end)
 763                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
 764                                                         base + size,
 765                                                         __pa(dart_table_end),
 766                                                          prot,
 767                                                          mmu_linear_psize,
 768                                                          mmu_kernel_ssize));
 769                         continue;
 770                 }
 771 #endif /* CONFIG_U3_DART */
 772                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 773                                 prot, mmu_linear_psize, mmu_kernel_ssize));
 774         }
 775         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 776
 777         /*
 778          * If we have a memory_limit and we've allocated TCEs then we need to
 779          * explicitly map the TCE area at the top of RAM. We also cope with the
 780          * case that the TCEs start below memory_limit.
 781          * tce_alloc_start/end are 16MB aligned so the mapping should work
 782          * for either 4K or 16MB pages.
 783          */
 784         if (tce_alloc_start) {
 785                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 786                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 787
 788                 if (base + size >= tce_alloc_start)
 789                         tce_alloc_start = base + size + 1;
 790
 791                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 792                                          __pa(tce_alloc_start), prot,
 793                                          mmu_linear_psize, mmu_kernel_ssize));
 794         }
 795
 796         htab_finish_init();
 797
 798         DBG(" <- htab_initialize()\n");
 799 }
 800 #undef KB
 801 #undef MB
 802
 803 void __init early_init_mmu(void)
 804 {
 805         /* Setup initial STAB address in the PACA */
 806         get_paca()->stab_real = __pa((u64)&initial_stab);
 807         get_paca()->stab_addr = (u64)&initial_stab;
 808
 809         /* Initialize the MMU Hash table and create the linear mapping
 810          * of memory. Has to be done before stab/slb initialization as
 811          * this is currently where the page size encoding is obtained
 812          */
 813         htab_initialize();
 814
 815         /* Initialize stab / SLB management */
 816         if (mmu_has_feature(MMU_FTR_SLB))
 817                 slb_initialize();
 818         else
 819                 stab_initialize(get_paca()->stab_real);
 820 }
 821
 822 #ifdef CONFIG_SMP
 823 void early_init_mmu_secondary(void)
 824 {
 825         /* Initialize hash table for that CPU */
 826         if (!firmware_has_feature(FW_FEATURE_LPAR))
 827                 mtspr(SPRN_SDR1, _SDR1);
 828
 829         /* Initialize STAB/SLB. We use a virtual address as it works
 830          * in real mode on pSeries.
 831          */
 832         if (mmu_has_feature(MMU_FTR_SLB))
 833                 slb_initialize();
 834         else
 835                 stab_initialize(get_paca()->stab_addr);
 836 }
 837 #endif /* CONFIG_SMP */
 838
 839 /*
 840  * Called by asm hashtable.S for doing lazy icache flush
 841  */
 842 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 843 {
 844         struct page *page;
 845
 846         if (!pfn_valid(pte_pfn(pte)))
 847                 return pp;
 848
 849         page = pte_page(pte);
 850
 851         /* page is dirty */
 852         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
 853                 if (trap == 0x400) {
 854                         flush_dcache_icache_page(page);
 855                         set_bit(PG_arch_1, &page->flags);
 856                 } else
 857                         pp |= HPTE_R_N;
 858         }
 859         return pp;
 860 }
 861
 862 #ifdef CONFIG_PPC_MM_SLICES
 863 unsigned int get_paca_psize(unsigned long addr)
 864 {
 865         u64 lpsizes;
 866         unsigned char *hpsizes;
 867         unsigned long index, mask_index;
 868
 869         if (addr < SLICE_LOW_TOP) {
 870                 lpsizes = get_paca()->context.low_slices_psize;
 871                 index = GET_LOW_SLICE_INDEX(addr);
 872                 return (lpsizes >> (index * 4)) & 0xF;
 873         }
 874         hpsizes = get_paca()->context.high_slices_psize;
 875         index = GET_HIGH_SLICE_INDEX(addr);
 876         mask_index = index & 0x1;
 877         return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
 878 }
 879
 880 #else
 881 unsigned int get_paca_psize(unsigned long addr)
 882 {
 883         return get_paca()->context.user_psize;
 884 }
 885 #endif
 886
 887 /*
 888  * Demote a segment to using 4k pages.
 889  * For now this makes the whole process use 4k pages.
 890  */
 891 #ifdef CONFIG_PPC_64K_PAGES
 892 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
 893 {
 894         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
 895                 return;
 896         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
 897 #ifdef CONFIG_SPU_BASE
 898         spu_flush_all_slbs(mm);
 899 #endif
 900         if (get_paca_psize(addr) != MMU_PAGE_4K) {
 901                 get_paca()->context = mm->context;
 902                 slb_flush_and_rebolt();
 903         }
 904 }
 905 #endif /* CONFIG_PPC_64K_PAGES */
 906
 907 #ifdef CONFIG_PPC_SUBPAGE_PROT
 908 /*
 909  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
 910  * Userspace sets the subpage permissions using the subpage_prot system call.
 911  *
 912  * Result is 0: full permissions, _PAGE_RW: read-only,
 913  * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
 914  */
 915 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
 916 {
 917         struct subpage_prot_table *spt = &mm->context.spt;
 918         u32 spp = 0;
 919         u32 **sbpm, *sbpp;
 920
 921         if (ea >= spt->maxaddr)
 922                 return 0;
 923         if (ea < 0x100000000UL) {
 924                 /* addresses below 4GB use spt->low_prot */
 925                 sbpm = spt->low_prot;
 926         } else {
 927                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
 928                 if (!sbpm)
 929                         return 0;
 930         }
 931         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
 932         if (!sbpp)
 933                 return 0;
 934         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
 935
 936         /* extract 2-bit bitfield for this 4k subpage */
 937         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
 938
 939         /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
 940         spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
 941         return spp;
 942 }
 943
 944 #else /* CONFIG_PPC_SUBPAGE_PROT */
 945 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
 946 {
 947         return 0;
 948 }
 949 #endif
 950
 951 void hash_failure_debug(unsigned long ea, unsigned long access,
 952                         unsigned long vsid, unsigned long trap,
 953                         int ssize, int psize, int lpsize, unsigned long pte)
 954 {
 955         if (!printk_ratelimit())
 956                 return;
 957         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
 958                 ea, access, current->comm);
 959         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
 960                 trap, vsid, ssize, psize, lpsize, pte);
 961 }
 962
 963 /* Result code is:
 964  *  0 - handled
 965  *  1 - normal page fault
 966  * -1 - critical hash insertion error
 967  * -2 - access not permitted by subpage protection mechanism
 968  */
 969 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 970 {
 971         enum ctx_state prev_state = exception_enter();
 972         pgd_t *pgdir;
 973         unsigned long vsid;
 974         struct mm_struct *mm;
 975         pte_t *ptep;
 976         unsigned hugeshift;
 977         const struct cpumask *tmp;
 978         int rc, user_region = 0, local = 0;
 979         int psize, ssize;
 980
 981         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
 982                 ea, access, trap);
 983
 984         /* Get region & vsid */
 985         switch (REGION_ID(ea)) {
 986         case USER_REGION_ID:
 987                 user_region = 1;
 988                 mm = current->mm;
 989                 if (! mm) {
 990                         DBG_LOW(" user region with no mm !\n");
 991                         rc = 1;
 992                         goto bail;
 993                 }
 994                 psize = get_slice_psize(mm, ea);
 995                 ssize = user_segment_size(ea);
 996                 vsid = get_vsid(mm->context.id, ea, ssize);
 997                 break;
 998         case VMALLOC_REGION_ID:
 999                 mm = &init_mm;
1000                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1001                 if (ea < VMALLOC_END)
1002                         psize = mmu_vmalloc_psize;
1003                 else
1004                         psize = mmu_io_psize;
1005                 ssize = mmu_kernel_ssize;
1006                 break;
1007         default:
1008                 /* Not a valid range
1009                  * Send the problem up to do_page_fault
1010                  */
1011                 rc = 1;
1012                 goto bail;
1013         }
1014         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1015
1016         /* Bad address. */
1017         if (!vsid) {
1018                 DBG_LOW("Bad address!\n");
1019                 rc = 1;
1020                 goto bail;
1021         }
1022         /* Get pgdir */
1023         pgdir = mm->pgd;
1024         if (pgdir == NULL) {
1025                 rc = 1;
1026                 goto bail;
1027         }
1028
1029         /* Check CPU locality */
1030         tmp = cpumask_of(smp_processor_id());
1031         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1032                 local = 1;
1033
1034 #ifndef CONFIG_PPC_64K_PAGES
1035         /* If we use 4K pages and our psize is not 4K, then we might
1036          * be hitting a special driver mapping, and need to align the
1037          * address before we fetch the PTE.
1038          *
1039          * It could also be a hugepage mapping, in which case this is
1040          * not necessary, but it's not harmful, either.
1041          */
1042         if (psize != MMU_PAGE_4K)
1043                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1044 #endif /* CONFIG_PPC_64K_PAGES */
1045
1046         /* Get PTE and page size from page tables */
1047         ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
1048         if (ptep == NULL || !pte_present(*ptep)) {
1049                 DBG_LOW(" no PTE !\n");
1050                 rc = 1;
1051                 goto bail;
1052         }
1053
1054         /* Add _PAGE_PRESENT to the required access perm */
1055         access |= _PAGE_PRESENT;
1056
1057         /* Pre-check access permissions (will be re-checked atomically
1058          * in __hash_page_XX but this pre-check is a fast path
1059          */
1060         if (access & ~pte_val(*ptep)) {
1061                 DBG_LOW(" no access !\n");
1062                 rc = 1;
1063                 goto bail;
1064         }
1065
1066         if (hugeshift) {
1067                 if (pmd_trans_huge(*(pmd_t *)ptep))
1068                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1069                                              trap, local, ssize, psize);
1070 #ifdef CONFIG_HUGETLB_PAGE
1071                 else
1072                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1073                                               local, ssize, hugeshift, psize);
1074 #else
1075                 else {
1076                         /*
1077                          * if we have hugeshift, and is not transhuge with
1078                          * hugetlb disabled, something is really wrong.
1079                          */
1080                         rc = 1;
1081                         WARN_ON(1);
1082                 }
1083 #endif
1084                 goto bail;
1085         }
1086
1087 #ifndef CONFIG_PPC_64K_PAGES
1088         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1089 #else
1090         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1091                 pte_val(*(ptep + PTRS_PER_PTE)));
1092 #endif
1093         /* Do actual hashing */
1094 #ifdef CONFIG_PPC_64K_PAGES
1095         /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1096         if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1097                 demote_segment_4k(mm, ea);
1098                 psize = MMU_PAGE_4K;
1099         }
1100
1101         /* If this PTE is non-cacheable and we have restrictions on
1102          * using non cacheable large pages, then we switch to 4k
1103          */
1104         if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1105             (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1106                 if (user_region) {
1107                         demote_segment_4k(mm, ea);
1108                         psize = MMU_PAGE_4K;
1109                 } else if (ea < VMALLOC_END) {
1110                         /*
1111                          * some driver did a non-cacheable mapping
1112                          * in vmalloc space, so switch vmalloc
1113                          * to 4k pages
1114                          */
1115                         printk(KERN_ALERT "Reducing vmalloc segment "
1116                                "to 4kB pages because of "
1117                                "non-cacheable mapping\n");
1118                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1119 #ifdef CONFIG_SPU_BASE
1120                         spu_flush_all_slbs(mm);
1121 #endif
1122                 }
1123         }
1124         if (user_region) {
1125                 if (psize != get_paca_psize(ea)) {
1126                         get_paca()->context = mm->context;
1127                         slb_flush_and_rebolt();
1128                 }
1129         } else if (get_paca()->vmalloc_sllp !=
1130                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1131                 get_paca()->vmalloc_sllp =
1132                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1133                 slb_vmalloc_update();
1134         }
1135 #endif /* CONFIG_PPC_64K_PAGES */
1136
1137 #ifdef CONFIG_PPC_HAS_HASH_64K
1138         if (psize == MMU_PAGE_64K)
1139                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1140         else
1141 #endif /* CONFIG_PPC_HAS_HASH_64K */
1142         {
1143                 int spp = subpage_protection(mm, ea);
1144                 if (access & spp)
1145                         rc = -2;
1146                 else
1147                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1148                                             local, ssize, spp);
1149         }
1150
1151         /* Dump some info in case of hash insertion failure, they should
1152          * never happen so it is really useful to know if/when they do
1153          */
1154         if (rc == -1)
1155                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1156                                    psize, pte_val(*ptep));
1157 #ifndef CONFIG_PPC_64K_PAGES
1158         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1159 #else
1160         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1161                 pte_val(*(ptep + PTRS_PER_PTE)));
1162 #endif
1163         DBG_LOW(" -> rc=%d\n", rc);
1164
1165 bail:
1166         exception_exit(prev_state);
1167         return rc;
1168 }
1169 EXPORT_SYMBOL_GPL(hash_page);
1170
1171 void hash_preload(struct mm_struct *mm, unsigned long ea,
1172                   unsigned long access, unsigned long trap)
1173 {
1174         int hugepage_shift;
1175         unsigned long vsid;
1176         pgd_t *pgdir;
1177         pte_t *ptep;
1178         unsigned long flags;
1179         int rc, ssize, local = 0;
1180
1181         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1182
1183 #ifdef CONFIG_PPC_MM_SLICES
1184         /* We only prefault standard pages for now */
1185         if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1186                 return;
1187 #endif
1188
1189         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1190                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1191
1192         /* Get Linux PTE if available */
1193         pgdir = mm->pgd;
1194         if (pgdir == NULL)
1195                 return;
1196
1197         /* Get VSID */
1198         ssize = user_segment_size(ea);
1199         vsid = get_vsid(mm->context.id, ea, ssize);
1200         if (!vsid)
1201                 return;
1202         /*
1203          * Hash doesn't like irqs. Walking linux page table with irq disabled
1204          * saves us from holding multiple locks.
1205          */
1206         local_irq_save(flags);
1207
1208         /*
1209          * THP pages use update_mmu_cache_pmd. We don't do
1210          * hash preload there. Hence can ignore THP here
1211          */
1212         ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugepage_shift);
1213         if (!ptep)
1214                 goto out_exit;
1215
1216         WARN_ON(hugepage_shift);
1217 #ifdef CONFIG_PPC_64K_PAGES
1218         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1219          * a 64K kernel), then we don't preload, hash_page() will take
1220          * care of it once we actually try to access the page.
1221          * That way we don't have to duplicate all of the logic for segment
1222          * page size demotion here
1223          */
1224         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1225                 goto out_exit;
1226 #endif /* CONFIG_PPC_64K_PAGES */
1227
1228         /* Is that local to this CPU ? */
1229         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1230                 local = 1;
1231
1232         /* Hash it in */
1233 #ifdef CONFIG_PPC_HAS_HASH_64K
1234         if (mm->context.user_psize == MMU_PAGE_64K)
1235                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1236         else
1237 #endif /* CONFIG_PPC_HAS_HASH_64K */
1238                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1239                                     subpage_protection(mm, ea));
1240
1241         /* Dump some info in case of hash insertion failure, they should
1242          * never happen so it is really useful to know if/when they do
1243          */
1244         if (rc == -1)
1245                 hash_failure_debug(ea, access, vsid, trap, ssize,
1246                                    mm->context.user_psize,
1247                                    mm->context.user_psize,
1248                                    pte_val(*ptep));
1249 out_exit:
1250         local_irq_restore(flags);
1251 }
1252
1253 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1254  *          do not forget to update the assembly call site !
1255  */
1256 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1257                      int local)
1258 {
1259         unsigned long hash, index, shift, hidx, slot;
1260
1261         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1262         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1263                 hash = hpt_hash(vpn, shift, ssize);
1264                 hidx = __rpte_to_hidx(pte, index);
1265                 if (hidx & _PTEIDX_SECONDARY)
1266                         hash = ~hash;
1267                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1268                 slot += hidx & _PTEIDX_GROUP_IX;
1269                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1270                 /*
1271                  * We use same base page size and actual psize, because we don't
1272                  * use these functions for hugepage
1273                  */
1274                 ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
1275         } pte_iterate_hashed_end();
1276
1277 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1278         /* Transactions are not aborted by tlbiel, only tlbie.
1279          * Without, syncing a page back to a block device w/ PIO could pick up
1280          * transactional data (bad!) so we force an abort here.  Before the
1281          * sync the page will be made read-only, which will flush_hash_page.
1282          * BIG ISSUE here: if the kernel uses a page from userspace without
1283          * unmapping it first, it may see the speculated version.
1284          */
1285         if (local && cpu_has_feature(CPU_FTR_TM) &&
1286             current->thread.regs &&
1287             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1288                 tm_enable();
1289                 tm_abort(TM_CAUSE_TLBI);
1290         }
1291 #endif
1292 }
1293
1294 void flush_hash_range(unsigned long number, int local)
1295 {
1296         if (ppc_md.flush_hash_range)
1297                 ppc_md.flush_hash_range(number, local);
1298         else {
1299                 int i;
1300                 struct ppc64_tlb_batch *batch =
1301                         &__get_cpu_var(ppc64_tlb_batch);
1302
1303                 for (i = 0; i < number; i++)
1304                         flush_hash_page(batch->vpn[i], batch->pte[i],
1305                                         batch->psize, batch->ssize, local);
1306         }
1307 }
1308
1309 /*
1310  * low_hash_fault is called when we the low level hash code failed
1311  * to instert a PTE due to an hypervisor error
1312  */
1313 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1314 {
1315         enum ctx_state prev_state = exception_enter();
1316
1317         if (user_mode(regs)) {
1318 #ifdef CONFIG_PPC_SUBPAGE_PROT
1319                 if (rc == -2)
1320                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1321                 else
1322 #endif
1323                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1324         } else
1325                 bad_page_fault(regs, address, SIGBUS);
1326
1327         exception_exit(prev_state);
1328 }
1329
1330 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1331                            unsigned long pa, unsigned long rflags,
1332                            unsigned long vflags, int psize, int ssize)
1333 {
1334         unsigned long hpte_group;
1335         long slot;
1336
1337 repeat:
1338         hpte_group = ((hash & htab_hash_mask) *
1339                        HPTES_PER_GROUP) & ~0x7UL;
1340
1341         /* Insert into the hash table, primary slot */
1342         slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1343                                   psize, psize, ssize);
1344
1345         /* Primary is full, try the secondary */
1346         if (unlikely(slot == -1)) {
1347                 hpte_group = ((~hash & htab_hash_mask) *
1348                               HPTES_PER_GROUP) & ~0x7UL;
1349                 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
1350                                           vflags | HPTE_V_SECONDARY,
1351                                           psize, psize, ssize);
1352                 if (slot == -1) {
1353                         if (mftb() & 0x1)
1354                                 hpte_group = ((hash & htab_hash_mask) *
1355                                               HPTES_PER_GROUP)&~0x7UL;
1356
1357                         ppc_md.hpte_remove(hpte_group);
1358                         goto repeat;
1359                 }
1360         }
1361
1362         return slot;
1363 }
1364
1365 #ifdef CONFIG_DEBUG_PAGEALLOC
1366 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1367 {
1368         unsigned long hash;
1369         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1370         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1371         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1372         long ret;
1373
1374         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1375
1376         /* Don't create HPTE entries for bad address */
1377         if (!vsid)
1378                 return;
1379
1380         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1381                                     HPTE_V_BOLTED,
1382                                     mmu_linear_psize, mmu_kernel_ssize);
1383
1384         BUG_ON (ret < 0);
1385         spin_lock(&linear_map_hash_lock);
1386         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1387         linear_map_hash_slots[lmi] = ret | 0x80;
1388         spin_unlock(&linear_map_hash_lock);
1389 }
1390
1391 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1392 {
1393         unsigned long hash, hidx, slot;
1394         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1395         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1396
1397         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1398         spin_lock(&linear_map_hash_lock);
1399         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1400         hidx = linear_map_hash_slots[lmi] & 0x7f;
1401         linear_map_hash_slots[lmi] = 0;
1402         spin_unlock(&linear_map_hash_lock);
1403         if (hidx & _PTEIDX_SECONDARY)
1404                 hash = ~hash;
1405         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1406         slot += hidx & _PTEIDX_GROUP_IX;
1407         ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
1408                                mmu_kernel_ssize, 0);
1409 }
1410
1411 void kernel_map_pages(struct page *page, int numpages, int enable)
1412 {
1413         unsigned long flags, vaddr, lmi;
1414         int i;
1415
1416         local_irq_save(flags);
1417         for (i = 0; i < numpages; i++, page++) {
1418                 vaddr = (unsigned long)page_address(page);
1419                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1420                 if (lmi >= linear_map_hash_count)
1421                         continue;
1422                 if (enable)
1423                         kernel_map_linear_page(vaddr, lmi);
1424                 else
1425                         kernel_unmap_linear_page(vaddr, lmi);
1426         }
1427         local_irq_restore(flags);
1428 }
1429 #endif /* CONFIG_DEBUG_PAGEALLOC */
1430
1431 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1432                                 phys_addr_t first_memblock_size)
1433 {
1434         /* We don't currently support the first MEMBLOCK not mapping 0
1435          * physical on those processors
1436          */
1437         BUG_ON(first_memblock_base != 0);
1438
1439         /* On LPAR systems, the first entry is our RMA region,
1440          * non-LPAR 64-bit hash MMU systems don't have a limitation
1441          * on real mode access, but using the first entry works well
1442          * enough. We also clamp it to 1G to avoid some funky things
1443          * such as RTAS bugs etc...
1444          */
1445         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1446
1447         /* Finally limit subsequent allocations */
1448         memblock_set_current_limit(ppc64_rma_size);
1449 }