arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <linux/rculist.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/rtas.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/firmware.h>
  48 #include <asm/tce.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/udbg.h>
  51 #include <asm/mmzone.h>
  52 #include <asm/plpar_wrappers.h>
  53
  54 #include "pseries.h"
  55
  56 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  57 {
  58         struct iommu_table_group *table_group = NULL;
  59         struct iommu_table *tbl = NULL;
  60         struct iommu_table_group_link *tgl = NULL;
  61
  62         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  63                            node);
  64         if (!table_group)
  65                 goto fail_exit;
  66
  67         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  68         if (!tbl)
  69                 goto fail_exit;
  70
  71         tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
  72                         node);
  73         if (!tgl)
  74                 goto fail_exit;
  75
  76         INIT_LIST_HEAD_RCU(&tbl->it_group_list);
  77         tgl->table_group = table_group;
  78         list_add_rcu(&tgl->next, &tbl->it_group_list);
  79
  80         table_group->tables[0] = tbl;
  81
  82         return table_group;
  83
  84 fail_exit:
  85         kfree(tgl);
  86         kfree(table_group);
  87         kfree(tbl);
  88
  89         return NULL;
  90 }
  91
  92 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  93                 const char *node_name)
  94 {
  95         struct iommu_table *tbl;
  96 #ifdef CONFIG_IOMMU_API
  97         struct iommu_table_group_link *tgl;
  98 #endif
  99
 100         if (!table_group)
 101                 return;
 102
 103         tbl = table_group->tables[0];
 104 #ifdef CONFIG_IOMMU_API
 105         tgl = list_first_entry_or_null(&tbl->it_group_list,
 106                         struct iommu_table_group_link, next);
 107
 108         WARN_ON_ONCE(!tgl);
 109         if (tgl) {
 110                 list_del_rcu(&tgl->next);
 111                 kfree(tgl);
 112         }
 113         if (table_group->group) {
 114                 iommu_group_put(table_group->group);
 115                 BUG_ON(table_group->group);
 116         }
 117 #endif
 118         iommu_free_table(tbl, node_name);
 119
 120         kfree(table_group);
 121 }
 122
 123 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 124                               long npages, unsigned long uaddr,
 125                               enum dma_data_direction direction,
 126                               unsigned long attrs)
 127 {
 128         u64 proto_tce;
 129         __be64 *tcep, *tces;
 130         u64 rpn;
 131
 132         proto_tce = TCE_PCI_READ; // Read allowed
 133
 134         if (direction != DMA_TO_DEVICE)
 135                 proto_tce |= TCE_PCI_WRITE;
 136
 137         tces = tcep = ((__be64 *)tbl->it_base) + index;
 138
 139         while (npages--) {
 140                 /* can't move this out since we might cross MEMBLOCK boundary */
 141                 rpn = __pa(uaddr) >> TCE_SHIFT;
 142                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 143
 144                 uaddr += TCE_PAGE_SIZE;
 145                 tcep++;
 146         }
 147         return 0;
 148 }
 149
 150
 151 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 152 {
 153         __be64 *tcep, *tces;
 154
 155         tces = tcep = ((__be64 *)tbl->it_base) + index;
 156
 157         while (npages--)
 158                 *(tcep++) = 0;
 159 }
 160
 161 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 162 {
 163         __be64 *tcep;
 164
 165         tcep = ((__be64 *)tbl->it_base) + index;
 166
 167         return be64_to_cpu(*tcep);
 168 }
 169
 170 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 171 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 172
 173 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 174                                 long npages, unsigned long uaddr,
 175                                 enum dma_data_direction direction,
 176                                 unsigned long attrs)
 177 {
 178         u64 rc = 0;
 179         u64 proto_tce, tce;
 180         u64 rpn;
 181         int ret = 0;
 182         long tcenum_start = tcenum, npages_start = npages;
 183
 184         rpn = __pa(uaddr) >> TCE_SHIFT;
 185         proto_tce = TCE_PCI_READ;
 186         if (direction != DMA_TO_DEVICE)
 187                 proto_tce |= TCE_PCI_WRITE;
 188
 189         while (npages--) {
 190                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 191                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 192
 193                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 194                         ret = (int)rc;
 195                         tce_free_pSeriesLP(tbl, tcenum_start,
 196                                            (npages_start - (npages + 1)));
 197                         break;
 198                 }
 199
 200                 if (rc && printk_ratelimit()) {
 201                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 202                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 203                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 204                         printk("\ttce val = 0x%llx\n", tce );
 205                         dump_stack();
 206                 }
 207
 208                 tcenum++;
 209                 rpn++;
 210         }
 211         return ret;
 212 }
 213
 214 static DEFINE_PER_CPU(__be64 *, tce_page);
 215
 216 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 217                                      long npages, unsigned long uaddr,
 218                                      enum dma_data_direction direction,
 219                                      unsigned long attrs)
 220 {
 221         u64 rc = 0;
 222         u64 proto_tce;
 223         __be64 *tcep;
 224         u64 rpn;
 225         long l, limit;
 226         long tcenum_start = tcenum, npages_start = npages;
 227         int ret = 0;
 228         unsigned long flags;
 229
 230         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 231                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 232                                            direction, attrs);
 233         }
 234
 235         local_irq_save(flags);  /* to protect tcep and the page behind it */
 236
 237         tcep = __this_cpu_read(tce_page);
 238
 239         /* This is safe to do since interrupts are off when we're called
 240          * from iommu_alloc{,_sg}()
 241          */
 242         if (!tcep) {
 243                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 244                 /* If allocation fails, fall back to the loop implementation */
 245                 if (!tcep) {
 246                         local_irq_restore(flags);
 247                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 248                                             direction, attrs);
 249                 }
 250                 __this_cpu_write(tce_page, tcep);
 251         }
 252
 253         rpn = __pa(uaddr) >> TCE_SHIFT;
 254         proto_tce = TCE_PCI_READ;
 255         if (direction != DMA_TO_DEVICE)
 256                 proto_tce |= TCE_PCI_WRITE;
 257
 258         /* We can map max one pageful of TCEs at a time */
 259         do {
 260                 /*
 261                  * Set up the page with TCE data, looping through and setting
 262                  * the values.
 263                  */
 264                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 265
 266                 for (l = 0; l < limit; l++) {
 267                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 268                         rpn++;
 269                 }
 270
 271                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 272                                             (u64)tcenum << 12,
 273                                             (u64)__pa(tcep),
 274                                             limit);
 275
 276                 npages -= limit;
 277                 tcenum += limit;
 278         } while (npages > 0 && !rc);
 279
 280         local_irq_restore(flags);
 281
 282         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 283                 ret = (int)rc;
 284                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 285                                         (npages_start - (npages + limit)));
 286                 return ret;
 287         }
 288
 289         if (rc && printk_ratelimit()) {
 290                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 291                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 292                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 293                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 294                 dump_stack();
 295         }
 296         return ret;
 297 }
 298
 299 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 300 {
 301         u64 rc;
 302
 303         while (npages--) {
 304                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 305
 306                 if (rc && printk_ratelimit()) {
 307                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 308                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 309                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 310                         dump_stack();
 311                 }
 312
 313                 tcenum++;
 314         }
 315 }
 316
 317
 318 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 319 {
 320         u64 rc;
 321
 322         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 323                 return tce_free_pSeriesLP(tbl, tcenum, npages);
 324
 325         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 326
 327         if (rc && printk_ratelimit()) {
 328                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 329                 printk("\trc      = %lld\n", rc);
 330                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 331                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 332                 dump_stack();
 333         }
 334 }
 335
 336 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 337 {
 338         u64 rc;
 339         unsigned long tce_ret;
 340
 341         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 342
 343         if (rc && printk_ratelimit()) {
 344                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 345                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 346                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 347                 dump_stack();
 348         }
 349
 350         return tce_ret;
 351 }
 352
 353 /* this is compatible with cells for the device tree property */
 354 struct dynamic_dma_window_prop {
 355         __be32  liobn;          /* tce table number */
 356         __be64  dma_base;       /* address hi,lo */
 357         __be32  tce_shift;      /* ilog2(tce_page_size) */
 358         __be32  window_shift;   /* ilog2(tce_window_size) */
 359 };
 360
 361 struct direct_window {
 362         struct device_node *device;
 363         const struct dynamic_dma_window_prop *prop;
 364         struct list_head list;
 365 };
 366
 367 /* Dynamic DMA Window support */
 368 struct ddw_query_response {
 369         u32 windows_available;
 370         u32 largest_available_block;
 371         u32 page_size;
 372         u32 migration_capable;
 373 };
 374
 375 struct ddw_create_response {
 376         u32 liobn;
 377         u32 addr_hi;
 378         u32 addr_lo;
 379 };
 380
 381 static LIST_HEAD(direct_window_list);
 382 /* prevents races between memory on/offline and window creation */
 383 static DEFINE_SPINLOCK(direct_window_list_lock);
 384 /* protects initializing window twice for same device */
 385 static DEFINE_MUTEX(direct_window_init_mutex);
 386 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 387
 388 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 389                                         unsigned long num_pfn, const void *arg)
 390 {
 391         const struct dynamic_dma_window_prop *maprange = arg;
 392         int rc;
 393         u64 tce_size, num_tce, dma_offset, next;
 394         u32 tce_shift;
 395         long limit;
 396
 397         tce_shift = be32_to_cpu(maprange->tce_shift);
 398         tce_size = 1ULL << tce_shift;
 399         next = start_pfn << PAGE_SHIFT;
 400         num_tce = num_pfn << PAGE_SHIFT;
 401
 402         /* round back to the beginning of the tce page size */
 403         num_tce += next & (tce_size - 1);
 404         next &= ~(tce_size - 1);
 405
 406         /* covert to number of tces */
 407         num_tce |= tce_size - 1;
 408         num_tce >>= tce_shift;
 409
 410         do {
 411                 /*
 412                  * Set up the page with TCE data, looping through and setting
 413                  * the values.
 414                  */
 415                 limit = min_t(long, num_tce, 512);
 416                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 417
 418                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 419                                              dma_offset,
 420                                              0, limit);
 421                 next += limit * tce_size;
 422                 num_tce -= limit;
 423         } while (num_tce > 0 && !rc);
 424
 425         return rc;
 426 }
 427
 428 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 429                                         unsigned long num_pfn, const void *arg)
 430 {
 431         const struct dynamic_dma_window_prop *maprange = arg;
 432         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 433         __be64 *tcep;
 434         u32 tce_shift;
 435         u64 rc = 0;
 436         long l, limit;
 437
 438         local_irq_disable();    /* to protect tcep and the page behind it */
 439         tcep = __this_cpu_read(tce_page);
 440
 441         if (!tcep) {
 442                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 443                 if (!tcep) {
 444                         local_irq_enable();
 445                         return -ENOMEM;
 446                 }
 447                 __this_cpu_write(tce_page, tcep);
 448         }
 449
 450         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 451
 452         liobn = (u64)be32_to_cpu(maprange->liobn);
 453         tce_shift = be32_to_cpu(maprange->tce_shift);
 454         tce_size = 1ULL << tce_shift;
 455         next = start_pfn << PAGE_SHIFT;
 456         num_tce = num_pfn << PAGE_SHIFT;
 457
 458         /* round back to the beginning of the tce page size */
 459         num_tce += next & (tce_size - 1);
 460         next &= ~(tce_size - 1);
 461
 462         /* covert to number of tces */
 463         num_tce |= tce_size - 1;
 464         num_tce >>= tce_shift;
 465
 466         /* We can map max one pageful of TCEs at a time */
 467         do {
 468                 /*
 469                  * Set up the page with TCE data, looping through and setting
 470                  * the values.
 471                  */
 472                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 473                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 474
 475                 for (l = 0; l < limit; l++) {
 476                         tcep[l] = cpu_to_be64(proto_tce | next);
 477                         next += tce_size;
 478                 }
 479
 480                 rc = plpar_tce_put_indirect(liobn,
 481                                             dma_offset,
 482                                             (u64)__pa(tcep),
 483                                             limit);
 484
 485                 num_tce -= limit;
 486         } while (num_tce > 0 && !rc);
 487
 488         /* error cleanup: caller will clear whole range */
 489
 490         local_irq_enable();
 491         return rc;
 492 }
 493
 494 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 495                 unsigned long num_pfn, void *arg)
 496 {
 497         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 498 }
 499
 500 static void iommu_table_setparms(struct pci_controller *phb,
 501                                  struct device_node *dn,
 502                                  struct iommu_table *tbl)
 503 {
 504         struct device_node *node;
 505         const unsigned long *basep;
 506         const u32 *sizep;
 507
 508         node = phb->dn;
 509
 510         basep = of_get_property(node, "linux,tce-base", NULL);
 511         sizep = of_get_property(node, "linux,tce-size", NULL);
 512         if (basep == NULL || sizep == NULL) {
 513                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 514                                 "missing tce entries !\n", dn->full_name);
 515                 return;
 516         }
 517
 518         tbl->it_base = (unsigned long)__va(*basep);
 519
 520         if (!is_kdump_kernel())
 521                 memset((void *)tbl->it_base, 0, *sizep);
 522
 523         tbl->it_busno = phb->bus->number;
 524         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 525
 526         /* Units of tce entries */
 527         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 528
 529         /* Test if we are going over 2GB of DMA space */
 530         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 531                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 532                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 533         }
 534
 535         phb->dma_window_base_cur += phb->dma_window_size;
 536
 537         /* Set the tce table size - measured in entries */
 538         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 539
 540         tbl->it_index = 0;
 541         tbl->it_blocksize = 16;
 542         tbl->it_type = TCE_PCI;
 543 }
 544
 545 /*
 546  * iommu_table_setparms_lpar
 547  *
 548  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 549  */
 550 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 551                                       struct device_node *dn,
 552                                       struct iommu_table *tbl,
 553                                       const __be32 *dma_window)
 554 {
 555         unsigned long offset, size;
 556
 557         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 558
 559         tbl->it_busno = phb->bus->number;
 560         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 561         tbl->it_base   = 0;
 562         tbl->it_blocksize  = 16;
 563         tbl->it_type = TCE_PCI;
 564         tbl->it_offset = offset >> tbl->it_page_shift;
 565         tbl->it_size = size >> tbl->it_page_shift;
 566 }
 567
 568 struct iommu_table_ops iommu_table_pseries_ops = {
 569         .set = tce_build_pSeries,
 570         .clear = tce_free_pSeries,
 571         .get = tce_get_pseries
 572 };
 573
 574 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 575 {
 576         struct device_node *dn;
 577         struct iommu_table *tbl;
 578         struct device_node *isa_dn, *isa_dn_orig;
 579         struct device_node *tmp;
 580         struct pci_dn *pci;
 581         int children;
 582
 583         dn = pci_bus_to_OF_node(bus);
 584
 585         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 586
 587         if (bus->self) {
 588                 /* This is not a root bus, any setup will be done for the
 589                  * device-side of the bridge in iommu_dev_setup_pSeries().
 590                  */
 591                 return;
 592         }
 593         pci = PCI_DN(dn);
 594
 595         /* Check if the ISA bus on the system is under
 596          * this PHB.
 597          */
 598         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 599
 600         while (isa_dn && isa_dn != dn)
 601                 isa_dn = isa_dn->parent;
 602
 603         of_node_put(isa_dn_orig);
 604
 605         /* Count number of direct PCI children of the PHB. */
 606         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 607                 children++;
 608
 609         pr_debug("Children: %d\n", children);
 610
 611         /* Calculate amount of DMA window per slot. Each window must be
 612          * a power of two (due to pci_alloc_consistent requirements).
 613          *
 614          * Keep 256MB aside for PHBs with ISA.
 615          */
 616
 617         if (!isa_dn) {
 618                 /* No ISA/IDE - just set window size and return */
 619                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 620
 621                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 622                         pci->phb->dma_window_size >>= 1;
 623                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 624                          pci->phb->dma_window_size);
 625                 pci->phb->dma_window_base_cur = 0;
 626
 627                 return;
 628         }
 629
 630         /* If we have ISA, then we probably have an IDE
 631          * controller too. Allocate a 128MB table but
 632          * skip the first 128MB to avoid stepping on ISA
 633          * space.
 634          */
 635         pci->phb->dma_window_size = 0x8000000ul;
 636         pci->phb->dma_window_base_cur = 0x8000000ul;
 637
 638         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 639         tbl = pci->table_group->tables[0];
 640
 641         iommu_table_setparms(pci->phb, dn, tbl);
 642         tbl->it_ops = &iommu_table_pseries_ops;
 643         iommu_init_table(tbl, pci->phb->node);
 644         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 645
 646         /* Divide the rest (1.75GB) among the children */
 647         pci->phb->dma_window_size = 0x80000000ul;
 648         while (pci->phb->dma_window_size * children > 0x70000000ul)
 649                 pci->phb->dma_window_size >>= 1;
 650
 651         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 652 }
 653
 654 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 655         .set = tce_buildmulti_pSeriesLP,
 656         .clear = tce_freemulti_pSeriesLP,
 657         .get = tce_get_pSeriesLP
 658 };
 659
 660 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 661 {
 662         struct iommu_table *tbl;
 663         struct device_node *dn, *pdn;
 664         struct pci_dn *ppci;
 665         const __be32 *dma_window = NULL;
 666
 667         dn = pci_bus_to_OF_node(bus);
 668
 669         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 670                  dn->full_name);
 671
 672         /* Find nearest ibm,dma-window, walking up the device tree */
 673         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 674                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 675                 if (dma_window != NULL)
 676                         break;
 677         }
 678
 679         if (dma_window == NULL) {
 680                 pr_debug("  no ibm,dma-window property !\n");
 681                 return;
 682         }
 683
 684         ppci = PCI_DN(pdn);
 685
 686         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 687                  pdn->full_name, ppci->table_group);
 688
 689         if (!ppci->table_group) {
 690                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 691                 tbl = ppci->table_group->tables[0];
 692                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 693                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 694                 iommu_init_table(tbl, ppci->phb->node);
 695                 iommu_register_group(ppci->table_group,
 696                                 pci_domain_nr(bus), 0);
 697                 pr_debug("  created table: %p\n", ppci->table_group);
 698         }
 699 }
 700
 701
 702 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 703 {
 704         struct device_node *dn;
 705         struct iommu_table *tbl;
 706
 707         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 708
 709         dn = dev->dev.of_node;
 710
 711         /* If we're the direct child of a root bus, then we need to allocate
 712          * an iommu table ourselves. The bus setup code should have setup
 713          * the window sizes already.
 714          */
 715         if (!dev->bus->self) {
 716                 struct pci_controller *phb = PCI_DN(dn)->phb;
 717
 718                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 719                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 720                 tbl = PCI_DN(dn)->table_group->tables[0];
 721                 iommu_table_setparms(phb, dn, tbl);
 722                 tbl->it_ops = &iommu_table_pseries_ops;
 723                 iommu_init_table(tbl, phb->node);
 724                 iommu_register_group(PCI_DN(dn)->table_group,
 725                                 pci_domain_nr(phb->bus), 0);
 726                 set_iommu_table_base(&dev->dev, tbl);
 727                 iommu_add_device(&dev->dev);
 728                 return;
 729         }
 730
 731         /* If this device is further down the bus tree, search upwards until
 732          * an already allocated iommu table is found and use that.
 733          */
 734
 735         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 736                 dn = dn->parent;
 737
 738         if (dn && PCI_DN(dn)) {
 739                 set_iommu_table_base(&dev->dev,
 740                                 PCI_DN(dn)->table_group->tables[0]);
 741                 iommu_add_device(&dev->dev);
 742         } else
 743                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 744                        pci_name(dev));
 745 }
 746
 747 static int __read_mostly disable_ddw;
 748
 749 static int __init disable_ddw_setup(char *str)
 750 {
 751         disable_ddw = 1;
 752         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 753
 754         return 0;
 755 }
 756
 757 early_param("disable_ddw", disable_ddw_setup);
 758
 759 static void remove_ddw(struct device_node *np, bool remove_prop)
 760 {
 761         struct dynamic_dma_window_prop *dwp;
 762         struct property *win64;
 763         u32 ddw_avail[3];
 764         u64 liobn;
 765         int ret = 0;
 766
 767         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 768                                          &ddw_avail[0], 3);
 769
 770         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 771         if (!win64)
 772                 return;
 773
 774         if (ret || win64->length < sizeof(*dwp))
 775                 goto delprop;
 776
 777         dwp = win64->value;
 778         liobn = (u64)be32_to_cpu(dwp->liobn);
 779
 780         /* clear the whole window, note the arg is in kernel pages */
 781         ret = tce_clearrange_multi_pSeriesLP(0,
 782                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 783         if (ret)
 784                 pr_warning("%s failed to clear tces in window.\n",
 785                          np->full_name);
 786         else
 787                 pr_debug("%s successfully cleared tces in window.\n",
 788                          np->full_name);
 789
 790         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 791         if (ret)
 792                 pr_warning("%s: failed to remove direct window: rtas returned "
 793                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 794                         np->full_name, ret, ddw_avail[2], liobn);
 795         else
 796                 pr_debug("%s: successfully removed direct window: rtas returned "
 797                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 798                         np->full_name, ret, ddw_avail[2], liobn);
 799
 800 delprop:
 801         if (remove_prop)
 802                 ret = of_remove_property(np, win64);
 803         if (ret)
 804                 pr_warning("%s: failed to remove direct window property: %d\n",
 805                         np->full_name, ret);
 806 }
 807
 808 static u64 find_existing_ddw(struct device_node *pdn)
 809 {
 810         struct direct_window *window;
 811         const struct dynamic_dma_window_prop *direct64;
 812         u64 dma_addr = 0;
 813
 814         spin_lock(&direct_window_list_lock);
 815         /* check if we already created a window and dupe that config if so */
 816         list_for_each_entry(window, &direct_window_list, list) {
 817                 if (window->device == pdn) {
 818                         direct64 = window->prop;
 819                         dma_addr = be64_to_cpu(direct64->dma_base);
 820                         break;
 821                 }
 822         }
 823         spin_unlock(&direct_window_list_lock);
 824
 825         return dma_addr;
 826 }
 827
 828 static int find_existing_ddw_windows(void)
 829 {
 830         int len;
 831         struct device_node *pdn;
 832         struct direct_window *window;
 833         const struct dynamic_dma_window_prop *direct64;
 834
 835         if (!firmware_has_feature(FW_FEATURE_LPAR))
 836                 return 0;
 837
 838         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 839                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 840                 if (!direct64)
 841                         continue;
 842
 843                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 844                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 845                         kfree(window);
 846                         remove_ddw(pdn, true);
 847                         continue;
 848                 }
 849
 850                 window->device = pdn;
 851                 window->prop = direct64;
 852                 spin_lock(&direct_window_list_lock);
 853                 list_add(&window->list, &direct_window_list);
 854                 spin_unlock(&direct_window_list_lock);
 855         }
 856
 857         return 0;
 858 }
 859 machine_arch_initcall(pseries, find_existing_ddw_windows);
 860
 861 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 862                         struct ddw_query_response *query)
 863 {
 864         struct device_node *dn;
 865         struct pci_dn *pdn;
 866         u32 cfg_addr;
 867         u64 buid;
 868         int ret;
 869
 870         /*
 871          * Get the config address and phb buid of the PE window.
 872          * Rely on eeh to retrieve this for us.
 873          * Retrieve them from the pci device, not the node with the
 874          * dma-window property
 875          */
 876         dn = pci_device_to_OF_node(dev);
 877         pdn = PCI_DN(dn);
 878         buid = pdn->phb->buid;
 879         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 880
 881         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 882                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 883         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 884                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 885                 BUID_LO(buid), ret);
 886         return ret;
 887 }
 888
 889 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 890                         struct ddw_create_response *create, int page_shift,
 891                         int window_shift)
 892 {
 893         struct device_node *dn;
 894         struct pci_dn *pdn;
 895         u32 cfg_addr;
 896         u64 buid;
 897         int ret;
 898
 899         /*
 900          * Get the config address and phb buid of the PE window.
 901          * Rely on eeh to retrieve this for us.
 902          * Retrieve them from the pci device, not the node with the
 903          * dma-window property
 904          */
 905         dn = pci_device_to_OF_node(dev);
 906         pdn = PCI_DN(dn);
 907         buid = pdn->phb->buid;
 908         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 909
 910         do {
 911                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 912                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 913                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 914                                 page_shift, window_shift);
 915         } while (rtas_busy_delay(ret));
 916         dev_info(&dev->dev,
 917                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 918                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 919                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 920                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 921
 922         return ret;
 923 }
 924
 925 struct failed_ddw_pdn {
 926         struct device_node *pdn;
 927         struct list_head list;
 928 };
 929
 930 static LIST_HEAD(failed_ddw_pdn_list);
 931
 932 /*
 933  * If the PE supports dynamic dma windows, and there is space for a table
 934  * that can map all pages in a linear offset, then setup such a table,
 935  * and record the dma-offset in the struct device.
 936  *
 937  * dev: the pci device we are checking
 938  * pdn: the parent pe node with the ibm,dma_window property
 939  * Future: also check if we can remap the base window for our base page size
 940  *
 941  * returns the dma offset for use by dma_set_mask
 942  */
 943 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 944 {
 945         int len, ret;
 946         struct ddw_query_response query;
 947         struct ddw_create_response create;
 948         int page_shift;
 949         u64 dma_addr, max_addr;
 950         struct device_node *dn;
 951         u32 ddw_avail[3];
 952         struct direct_window *window;
 953         struct property *win64;
 954         struct dynamic_dma_window_prop *ddwprop;
 955         struct failed_ddw_pdn *fpdn;
 956
 957         mutex_lock(&direct_window_init_mutex);
 958
 959         dma_addr = find_existing_ddw(pdn);
 960         if (dma_addr != 0)
 961                 goto out_unlock;
 962
 963         /*
 964          * If we already went through this for a previous function of
 965          * the same device and failed, we don't want to muck with the
 966          * DMA window again, as it will race with in-flight operations
 967          * and can lead to EEHs. The above mutex protects access to the
 968          * list.
 969          */
 970         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
 971                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
 972                         goto out_unlock;
 973         }
 974
 975         /*
 976          * the ibm,ddw-applicable property holds the tokens for:
 977          * ibm,query-pe-dma-window
 978          * ibm,create-pe-dma-window
 979          * ibm,remove-pe-dma-window
 980          * for the given node in that order.
 981          * the property is actually in the parent, not the PE
 982          */
 983         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
 984                                          &ddw_avail[0], 3);
 985         if (ret)
 986                 goto out_failed;
 987
 988        /*
 989          * Query if there is a second window of size to map the
 990          * whole partition.  Query returns number of windows, largest
 991          * block assigned to PE (partition endpoint), and two bitmasks
 992          * of page sizes: supported and supported for migrate-dma.
 993          */
 994         dn = pci_device_to_OF_node(dev);
 995         ret = query_ddw(dev, ddw_avail, &query);
 996         if (ret != 0)
 997                 goto out_failed;
 998
 999         if (query.windows_available == 0) {
1000                 /*
1001                  * no additional windows are available for this device.
1002                  * We might be able to reallocate the existing window,
1003                  * trading in for a larger page size.
1004                  */
1005                 dev_dbg(&dev->dev, "no free dynamic windows");
1006                 goto out_failed;
1007         }
1008         if (query.page_size & 4) {
1009                 page_shift = 24; /* 16MB */
1010         } else if (query.page_size & 2) {
1011                 page_shift = 16; /* 64kB */
1012         } else if (query.page_size & 1) {
1013                 page_shift = 12; /* 4kB */
1014         } else {
1015                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1016                           query.page_size);
1017                 goto out_failed;
1018         }
1019         /* verify the window * number of ptes will map the partition */
1020         /* check largest block * page size > max memory hotplug addr */
1021         max_addr = memory_hotplug_max();
1022         if (query.largest_available_block < (max_addr >> page_shift)) {
1023                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1024                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1025                           1ULL << page_shift);
1026                 goto out_failed;
1027         }
1028         len = order_base_2(max_addr);
1029         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1030         if (!win64) {
1031                 dev_info(&dev->dev,
1032                         "couldn't allocate property for 64bit dma window\n");
1033                 goto out_failed;
1034         }
1035         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1036         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1037         win64->length = sizeof(*ddwprop);
1038         if (!win64->name || !win64->value) {
1039                 dev_info(&dev->dev,
1040                         "couldn't allocate property name and value\n");
1041                 goto out_free_prop;
1042         }
1043
1044         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1045         if (ret != 0)
1046                 goto out_free_prop;
1047
1048         ddwprop->liobn = cpu_to_be32(create.liobn);
1049         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1050                         create.addr_lo);
1051         ddwprop->tce_shift = cpu_to_be32(page_shift);
1052         ddwprop->window_shift = cpu_to_be32(len);
1053
1054         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1055                   create.liobn, dn->full_name);
1056
1057         window = kzalloc(sizeof(*window), GFP_KERNEL);
1058         if (!window)
1059                 goto out_clear_window;
1060
1061         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1062                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1063         if (ret) {
1064                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1065                          dn->full_name, ret);
1066                 goto out_free_window;
1067         }
1068
1069         ret = of_add_property(pdn, win64);
1070         if (ret) {
1071                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1072                          pdn->full_name, ret);
1073                 goto out_free_window;
1074         }
1075
1076         window->device = pdn;
1077         window->prop = ddwprop;
1078         spin_lock(&direct_window_list_lock);
1079         list_add(&window->list, &direct_window_list);
1080         spin_unlock(&direct_window_list_lock);
1081
1082         dma_addr = be64_to_cpu(ddwprop->dma_base);
1083         goto out_unlock;
1084
1085 out_free_window:
1086         kfree(window);
1087
1088 out_clear_window:
1089         remove_ddw(pdn, true);
1090
1091 out_free_prop:
1092         kfree(win64->name);
1093         kfree(win64->value);
1094         kfree(win64);
1095
1096 out_failed:
1097
1098         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1099         if (!fpdn)
1100                 goto out_unlock;
1101         fpdn->pdn = pdn;
1102         list_add(&fpdn->list, &failed_ddw_pdn_list);
1103
1104 out_unlock:
1105         mutex_unlock(&direct_window_init_mutex);
1106         return dma_addr;
1107 }
1108
1109 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1110 {
1111         struct device_node *pdn, *dn;
1112         struct iommu_table *tbl;
1113         const __be32 *dma_window = NULL;
1114         struct pci_dn *pci;
1115
1116         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1117
1118         /* dev setup for LPAR is a little tricky, since the device tree might
1119          * contain the dma-window properties per-device and not necessarily
1120          * for the bus. So we need to search upwards in the tree until we
1121          * either hit a dma-window property, OR find a parent with a table
1122          * already allocated.
1123          */
1124         dn = pci_device_to_OF_node(dev);
1125         pr_debug("  node is %s\n", dn->full_name);
1126
1127         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1128              pdn = pdn->parent) {
1129                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1130                 if (dma_window)
1131                         break;
1132         }
1133
1134         if (!pdn || !PCI_DN(pdn)) {
1135                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1136                        "no DMA window found for pci dev=%s dn=%s\n",
1137                                  pci_name(dev), of_node_full_name(dn));
1138                 return;
1139         }
1140         pr_debug("  parent is %s\n", pdn->full_name);
1141
1142         pci = PCI_DN(pdn);
1143         if (!pci->table_group) {
1144                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1145                 tbl = pci->table_group->tables[0];
1146                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1147                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1148                 iommu_init_table(tbl, pci->phb->node);
1149                 iommu_register_group(pci->table_group,
1150                                 pci_domain_nr(pci->phb->bus), 0);
1151                 pr_debug("  created table: %p\n", pci->table_group);
1152         } else {
1153                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1154         }
1155
1156         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1157         iommu_add_device(&dev->dev);
1158 }
1159
1160 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1161 {
1162         bool ddw_enabled = false;
1163         struct device_node *pdn, *dn;
1164         struct pci_dev *pdev;
1165         const __be32 *dma_window = NULL;
1166         u64 dma_offset;
1167
1168         if (!dev->dma_mask)
1169                 return -EIO;
1170
1171         if (!dev_is_pci(dev))
1172                 goto check_mask;
1173
1174         pdev = to_pci_dev(dev);
1175
1176         /* only attempt to use a new window if 64-bit DMA is requested */
1177         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1178                 dn = pci_device_to_OF_node(pdev);
1179                 dev_dbg(dev, "node is %s\n", dn->full_name);
1180
1181                 /*
1182                  * the device tree might contain the dma-window properties
1183                  * per-device and not necessarily for the bus. So we need to
1184                  * search upwards in the tree until we either hit a dma-window
1185                  * property, OR find a parent with a table already allocated.
1186                  */
1187                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1188                                 pdn = pdn->parent) {
1189                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1190                         if (dma_window)
1191                                 break;
1192                 }
1193                 if (pdn && PCI_DN(pdn)) {
1194                         dma_offset = enable_ddw(pdev, pdn);
1195                         if (dma_offset != 0) {
1196                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1197                                 set_dma_offset(dev, dma_offset);
1198                                 set_dma_ops(dev, &dma_direct_ops);
1199                                 ddw_enabled = true;
1200                         }
1201                 }
1202         }
1203
1204         /* fall back on iommu ops */
1205         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1206                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1207                 set_dma_ops(dev, &dma_iommu_ops);
1208         }
1209
1210 check_mask:
1211         if (!dma_supported(dev, dma_mask))
1212                 return -EIO;
1213
1214         *dev->dma_mask = dma_mask;
1215         return 0;
1216 }
1217
1218 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1219 {
1220         if (!dev->dma_mask)
1221                 return 0;
1222
1223         if (!disable_ddw && dev_is_pci(dev)) {
1224                 struct pci_dev *pdev = to_pci_dev(dev);
1225                 struct device_node *dn;
1226
1227                 dn = pci_device_to_OF_node(pdev);
1228
1229                 /* search upwards for ibm,dma-window */
1230                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1231                                 dn = dn->parent)
1232                         if (of_get_property(dn, "ibm,dma-window", NULL))
1233                                 break;
1234                 /* if there is a ibm,ddw-applicable property require 64 bits */
1235                 if (dn && PCI_DN(dn) &&
1236                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1237                         return DMA_BIT_MASK(64);
1238         }
1239
1240         return dma_iommu_ops.get_required_mask(dev);
1241 }
1242
1243 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1244                 void *data)
1245 {
1246         struct direct_window *window;
1247         struct memory_notify *arg = data;
1248         int ret = 0;
1249
1250         switch (action) {
1251         case MEM_GOING_ONLINE:
1252                 spin_lock(&direct_window_list_lock);
1253                 list_for_each_entry(window, &direct_window_list, list) {
1254                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1255                                         arg->nr_pages, window->prop);
1256                         /* XXX log error */
1257                 }
1258                 spin_unlock(&direct_window_list_lock);
1259                 break;
1260         case MEM_CANCEL_ONLINE:
1261         case MEM_OFFLINE:
1262                 spin_lock(&direct_window_list_lock);
1263                 list_for_each_entry(window, &direct_window_list, list) {
1264                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1265                                         arg->nr_pages, window->prop);
1266                         /* XXX log error */
1267                 }
1268                 spin_unlock(&direct_window_list_lock);
1269                 break;
1270         default:
1271                 break;
1272         }
1273         if (ret && action != MEM_CANCEL_ONLINE)
1274                 return NOTIFY_BAD;
1275
1276         return NOTIFY_OK;
1277 }
1278
1279 static struct notifier_block iommu_mem_nb = {
1280         .notifier_call = iommu_mem_notifier,
1281 };
1282
1283 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1284 {
1285         int err = NOTIFY_OK;
1286         struct of_reconfig_data *rd = data;
1287         struct device_node *np = rd->dn;
1288         struct pci_dn *pci = PCI_DN(np);
1289         struct direct_window *window;
1290
1291         switch (action) {
1292         case OF_RECONFIG_DETACH_NODE:
1293                 /*
1294                  * Removing the property will invoke the reconfig
1295                  * notifier again, which causes dead-lock on the
1296                  * read-write semaphore of the notifier chain. So
1297                  * we have to remove the property when releasing
1298                  * the device node.
1299                  */
1300                 remove_ddw(np, false);
1301                 if (pci && pci->table_group)
1302                         iommu_pseries_free_group(pci->table_group,
1303                                         np->full_name);
1304
1305                 spin_lock(&direct_window_list_lock);
1306                 list_for_each_entry(window, &direct_window_list, list) {
1307                         if (window->device == np) {
1308                                 list_del(&window->list);
1309                                 kfree(window);
1310                                 break;
1311                         }
1312                 }
1313                 spin_unlock(&direct_window_list_lock);
1314                 break;
1315         default:
1316                 err = NOTIFY_DONE;
1317                 break;
1318         }
1319         return err;
1320 }
1321
1322 static struct notifier_block iommu_reconfig_nb = {
1323         .notifier_call = iommu_reconfig_notifier,
1324 };
1325
1326 /* These are called very early. */
1327 void iommu_init_early_pSeries(void)
1328 {
1329         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1330                 return;
1331
1332         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1333                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1334                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1335                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1336                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1337         } else {
1338                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1339                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1340         }
1341
1342
1343         of_reconfig_notifier_register(&iommu_reconfig_nb);
1344         register_memory_notifier(&iommu_mem_nb);
1345
1346         set_pci_dma_ops(&dma_iommu_ops);
1347 }
1348
1349 static int __init disable_multitce(char *str)
1350 {
1351         if (strcmp(str, "off") == 0 &&
1352             firmware_has_feature(FW_FEATURE_LPAR) &&
1353             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1354                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1355                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1356         }
1357         return 1;
1358 }
1359
1360 __setup("multitce=", disable_multitce);
1361
1362 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);