arch/powerpc/sysdev/xics/ics-opal.c

   1 /*
   2  * ICS backend for OPAL managed interrupts.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/irq.h>
  17 #include <linux/smp.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/init.h>
  20 #include <linux/cpu.h>
  21 #include <linux/of.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/msi.h>
  24
  25 #include <asm/prom.h>
  26 #include <asm/smp.h>
  27 #include <asm/machdep.h>
  28 #include <asm/irq.h>
  29 #include <asm/errno.h>
  30 #include <asm/xics.h>
  31 #include <asm/opal.h>
  32 #include <asm/firmware.h>
  33
  34 static int ics_opal_mangle_server(int server)
  35 {
  36         /* No link for now */
  37         return server << 2;
  38 }
  39
  40 static int ics_opal_unmangle_server(int server)
  41 {
  42         /* No link for now */
  43         return server >> 2;
  44 }
  45
  46 static void ics_opal_unmask_irq(struct irq_data *d)
  47 {
  48         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
  49         int64_t rc;
  50         int server;
  51
  52         pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
  53
  54         if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
  55                 return;
  56
  57         server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
  58         server = ics_opal_mangle_server(server);
  59
  60         rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
  61         if (rc != OPAL_SUCCESS)
  62                 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
  63                        " error %lld\n",
  64                        __func__, d->irq, hw_irq, server, rc);
  65 }
  66
  67 static unsigned int ics_opal_startup(struct irq_data *d)
  68 {
  69 #ifdef CONFIG_PCI_MSI
  70         /*
  71          * The generic MSI code returns with the interrupt disabled on the
  72          * card, using the MSI mask bits. Firmware doesn't appear to unmask
  73          * at that level, so we do it here by hand.
  74          */
  75         if (irq_data_get_msi_desc(d))
  76                 pci_msi_unmask_irq(d);
  77 #endif
  78
  79         /* unmask it */
  80         ics_opal_unmask_irq(d);
  81         return 0;
  82 }
  83
  84 static void ics_opal_mask_real_irq(unsigned int hw_irq)
  85 {
  86         int server = ics_opal_mangle_server(xics_default_server);
  87         int64_t rc;
  88
  89         if (hw_irq == XICS_IPI)
  90                 return;
  91
  92         /* Have to set XIVE to 0xff to be able to remove a slot */
  93         rc = opal_set_xive(hw_irq, server, 0xff);
  94         if (rc != OPAL_SUCCESS)
  95                 pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
  96                        __func__, hw_irq, rc);
  97 }
  98
  99 static void ics_opal_mask_irq(struct irq_data *d)
 100 {
 101         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 102
 103         pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 104
 105         if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 106                 return;
 107         ics_opal_mask_real_irq(hw_irq);
 108 }
 109
 110 static int ics_opal_set_affinity(struct irq_data *d,
 111                                  const struct cpumask *cpumask,
 112                                  bool force)
 113 {
 114         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 115         __be16 oserver;
 116         int16_t server;
 117         int8_t priority;
 118         int64_t rc;
 119         int wanted_server;
 120
 121         if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 122                 return -1;
 123
 124         rc = opal_get_xive(hw_irq, &oserver, &priority);
 125         if (rc != OPAL_SUCCESS) {
 126                 pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
 127                        __func__, d->irq, hw_irq, rc);
 128                 return -1;
 129         }
 130         server = be16_to_cpu(oserver);
 131
 132         wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
 133         if (wanted_server < 0) {
 134                 pr_warning("%s: No online cpus in the mask %*pb for irq %d\n",
 135                            __func__, cpumask_pr_args(cpumask), d->irq);
 136                 return -1;
 137         }
 138         server = ics_opal_mangle_server(wanted_server);
 139
 140         pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
 141                  d->irq, hw_irq, wanted_server, server);
 142
 143         rc = opal_set_xive(hw_irq, server, priority);
 144         if (rc != OPAL_SUCCESS) {
 145                 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
 146                        " error %lld\n",
 147                        __func__, d->irq, hw_irq, server, rc);
 148                 return -1;
 149         }
 150         return IRQ_SET_MASK_OK;
 151 }
 152
 153 static struct irq_chip ics_opal_irq_chip = {
 154         .name = "OPAL ICS",
 155         .irq_startup = ics_opal_startup,
 156         .irq_mask = ics_opal_mask_irq,
 157         .irq_unmask = ics_opal_unmask_irq,
 158         .irq_eoi = NULL, /* Patched at init time */
 159         .irq_set_affinity = ics_opal_set_affinity,
 160         .irq_set_type = xics_set_irq_type,
 161         .irq_retrigger = xics_retrigger,
 162 };
 163
 164 static int ics_opal_map(struct ics *ics, unsigned int virq);
 165 static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
 166 static long ics_opal_get_server(struct ics *ics, unsigned long vec);
 167
 168 static int ics_opal_host_match(struct ics *ics, struct device_node *node)
 169 {
 170         return 1;
 171 }
 172
 173 /* Only one global & state struct ics */
 174 static struct ics ics_hal = {
 175         .map            = ics_opal_map,
 176         .mask_unknown   = ics_opal_mask_unknown,
 177         .get_server     = ics_opal_get_server,
 178         .host_match     = ics_opal_host_match,
 179 };
 180
 181 static int ics_opal_map(struct ics *ics, unsigned int virq)
 182 {
 183         unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
 184         int64_t rc;
 185         __be16 server;
 186         int8_t priority;
 187
 188         if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
 189                 return -EINVAL;
 190
 191         /* Check if HAL knows about this interrupt */
 192         rc = opal_get_xive(hw_irq, &server, &priority);
 193         if (rc != OPAL_SUCCESS)
 194                 return -ENXIO;
 195
 196         irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
 197         irq_set_chip_data(virq, &ics_hal);
 198
 199         return 0;
 200 }
 201
 202 static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
 203 {
 204         int64_t rc;
 205         __be16 server;
 206         int8_t priority;
 207
 208         /* Check if HAL knows about this interrupt */
 209         rc = opal_get_xive(vec, &server, &priority);
 210         if (rc != OPAL_SUCCESS)
 211                 return;
 212
 213         ics_opal_mask_real_irq(vec);
 214 }
 215
 216 static long ics_opal_get_server(struct ics *ics, unsigned long vec)
 217 {
 218         int64_t rc;
 219         __be16 server;
 220         int8_t priority;
 221
 222         /* Check if HAL knows about this interrupt */
 223         rc = opal_get_xive(vec, &server, &priority);
 224         if (rc != OPAL_SUCCESS)
 225                 return -1;
 226         return ics_opal_unmangle_server(be16_to_cpu(server));
 227 }
 228
 229 int __init ics_opal_init(void)
 230 {
 231         if (!firmware_has_feature(FW_FEATURE_OPAL))
 232                 return -ENODEV;
 233
 234         /* We need to patch our irq chip's EOI to point to the
 235          * right ICP
 236          */
 237         ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
 238
 239         /* Register ourselves */
 240         xics_register_ics(&ics_hal);
 241
 242         pr_info("ICS OPAL backend registered\n");
 243
 244         return 0;
 245 }