arch/ppc/platforms/k2.c

   1 /*
   2  * arch/ppc/platforms/k2.c
   3  *
   4  * Board setup routines for SBS K2
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Updated by: Randy Vinson <rvinson@mvista.com.
   9  *
  10  * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/types.h>
  25 #include <linux/major.h>
  26 #include <linux/initrd.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/irq.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33
  34 #include <asm/system.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/dma.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/time.h>
  41 #include <asm/i8259.h>
  42 #include <asm/todc.h>
  43 #include <asm/bootinfo.h>
  44
  45 #include <syslib/cpc710.h>
  46 #include "k2.h"
  47
  48 extern unsigned long loops_per_jiffy;
  49 extern void gen550_progress(char *, unsigned short);
  50
  51 static unsigned int cpu_7xx[16] = {
  52         0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
  53 };
  54 static unsigned int cpu_6xx[16] = {
  55         0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
  56 };
  57
  58 static inline int __init
  59 k2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  60 {
  61         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  62         /*
  63          * Check our hose index.  If we are zero then we are on the
  64          * local PCI hose, otherwise we are on the cPCI hose.
  65          */
  66         if (!hose->index) {
  67                 static char pci_irq_table[][4] =
  68                         /*
  69                          *      PCI IDSEL/INTPIN->INTLINE
  70                          *      A       B       C       D
  71                          */
  72                 {
  73                         {1,     0,      0,      0},     /* Ethernet */
  74                         {5,     5,      5,      5},     /* PMC Site 1 */
  75                         {6,     6,      6,      6},     /* PMC Site 2 */
  76                         {0,     0,      0,      0},     /* unused */
  77                         {0,     0,      0,      0},     /* unused */
  78                         {0,     0,      0,      0},     /* PCI-ISA Bridge */
  79                         {0,     0,      0,      0},     /* unused */
  80                         {0,     0,      0,      0},     /* unused */
  81                         {0,     0,      0,      0},     /* unused */
  82                         {0,     0,      0,      0},     /* unused */
  83                         {0,     0,      0,      0},     /* unused */
  84                         {0,     0,      0,      0},     /* unused */
  85                         {0,     0,      0,      0},     /* unused */
  86                         {0,     0,      0,      0},     /* unused */
  87                         {15,    0,      0,      0},     /* M5229 IDE */
  88                 };
  89                 const long min_idsel = 3, max_idsel = 17, irqs_per_slot = 4;
  90                 return PCI_IRQ_TABLE_LOOKUP;
  91         } else {
  92                 static char pci_irq_table[][4] =
  93                 /*
  94                  *      PCI IDSEL/INTPIN->INTLINE
  95                  *      A       B       C       D
  96                  */
  97                 {
  98                         {10,    11,     12,     9},     /* cPCI slot 8 */
  99                         {11,    12,     9,      10},    /* cPCI slot 7 */
 100                         {12,    9,      10,     11},    /* cPCI slot 6 */
 101                         {9,     10,     11,     12},    /* cPCI slot 5 */
 102                         {10,    11,     12,     9},     /* cPCI slot 4 */
 103                         {11,    12,     9,      10},    /* cPCI slot 3 */
 104                         {12,    9,      10,     11},    /* cPCI slot 2 */
 105                 };
 106                 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
 107                 return PCI_IRQ_TABLE_LOOKUP;
 108         }
 109 }
 110
 111 void k2_pcibios_fixup(void)
 112 {
 113 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 114         struct pci_dev *ide_dev;
 115
 116         /*
 117          * Enable DMA support on hdc
 118          */
 119         ide_dev = pci_get_device(PCI_VENDOR_ID_AL,
 120                                   PCI_DEVICE_ID_AL_M5229, NULL);
 121
 122         if (ide_dev) {
 123
 124                 unsigned long ide_dma_base;
 125
 126                 ide_dma_base = pci_resource_start(ide_dev, 4);
 127                 outb(0x00, ide_dma_base + 0x2);
 128                 outb(0x20, ide_dma_base + 0xa);
 129                 pci_dev_put(ide_dev);
 130         }
 131 #endif
 132 }
 133
 134 void k2_pcibios_fixup_resources(struct pci_dev *dev)
 135 {
 136         int i;
 137
 138         if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
 139             (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64)) {
 140                 pr_debug("Fixup CPC710 resources\n");
 141                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 142                         dev->resource[i].start = 0;
 143                         dev->resource[i].end = 0;
 144                 }
 145         }
 146 }
 147
 148 void k2_setup_hoses(void)
 149 {
 150         struct pci_controller *hose_a, *hose_b;
 151
 152         /*
 153          * Reconfigure CPC710 memory map so
 154          * we have some more PCI memory space.
 155          */
 156
 157         /* Set FPHB mode */
 158         __raw_writel(0x808000e0, PGCHP);        /* Set FPHB mode */
 159
 160         /* PCI32 mappings */
 161         __raw_writel(0x00000000, K2_PCI32_BAR + PIBAR); /* PCI I/O base */
 162         __raw_writel(0x00000000, K2_PCI32_BAR + PMBAR); /* PCI Mem base */
 163         __raw_writel(0xf0000000, K2_PCI32_BAR + MSIZE); /* 256MB */
 164         __raw_writel(0xfff00000, K2_PCI32_BAR + IOSIZE); /* 1MB */
 165         __raw_writel(0xc0000000, K2_PCI32_BAR + SMBAR); /* Base@0xc0000000 */
 166         __raw_writel(0x80000000, K2_PCI32_BAR + SIBAR); /* Base@0x80000000 */
 167         __raw_writel(0x000000c0, K2_PCI32_BAR + PSSIZE); /* 1GB space */
 168         __raw_writel(0x000000c0, K2_PCI32_BAR + PPSIZE); /* 1GB space */
 169         __raw_writel(0x00000000, K2_PCI32_BAR + BARPS); /* Base@0x00000000 */
 170         __raw_writel(0x00000000, K2_PCI32_BAR + BARPP); /* Base@0x00000000 */
 171         __raw_writel(0x00000080, K2_PCI32_BAR + PSBAR); /* Base@0x80 */
 172         __raw_writel(0x00000000, K2_PCI32_BAR + PPBAR);
 173
 174         __raw_writel(0xc0000000, K2_PCI32_BAR + BPMDLK);
 175         __raw_writel(0xd0000000, K2_PCI32_BAR + TPMDLK);
 176         __raw_writel(0x80000000, K2_PCI32_BAR + BIODLK);
 177         __raw_writel(0x80100000, K2_PCI32_BAR + TIODLK);
 178         __raw_writel(0xe0008000, K2_PCI32_BAR + DLKCTRL);
 179         __raw_writel(0xffffffff, K2_PCI32_BAR + DLKDEV);
 180
 181         /* PCI64 mappings */
 182         __raw_writel(0x00100000, K2_PCI64_BAR + PIBAR); /* PCI I/O base */
 183         __raw_writel(0x10000000, K2_PCI64_BAR + PMBAR); /* PCI Mem base */
 184         __raw_writel(0xf0000000, K2_PCI64_BAR + MSIZE); /* 256MB */
 185         __raw_writel(0xfff00000, K2_PCI64_BAR + IOSIZE); /* 1MB */
 186         __raw_writel(0xd0000000, K2_PCI64_BAR + SMBAR); /* Base@0xd0000000 */
 187         __raw_writel(0x80100000, K2_PCI64_BAR + SIBAR); /* Base@0x80100000 */
 188         __raw_writel(0x000000c0, K2_PCI64_BAR + PSSIZE); /* 1GB space */
 189         __raw_writel(0x000000c0, K2_PCI64_BAR + PPSIZE); /* 1GB space */
 190         __raw_writel(0x00000000, K2_PCI64_BAR + BARPS); /* Base@0x00000000 */
 191         __raw_writel(0x00000000, K2_PCI64_BAR + BARPP); /* Base@0x00000000 */
 192
 193         /* Setup PCI32 hose */
 194         hose_a = pcibios_alloc_controller();
 195         if (!hose_a)
 196                 return;
 197
 198         hose_a->first_busno = 0;
 199         hose_a->last_busno = 0xff;
 200         hose_a->pci_mem_offset = K2_PCI32_MEM_BASE;
 201
 202         pci_init_resource(&hose_a->io_resource,
 203                           K2_PCI32_LOWER_IO,
 204                           K2_PCI32_UPPER_IO,
 205                           IORESOURCE_IO, "PCI32 host bridge");
 206
 207         pci_init_resource(&hose_a->mem_resources[0],
 208                           K2_PCI32_LOWER_MEM + K2_PCI32_MEM_BASE,
 209                           K2_PCI32_UPPER_MEM + K2_PCI32_MEM_BASE,
 210                           IORESOURCE_MEM, "PCI32 host bridge");
 211
 212         hose_a->io_space.start = K2_PCI32_LOWER_IO;
 213         hose_a->io_space.end = K2_PCI32_UPPER_IO;
 214         hose_a->mem_space.start = K2_PCI32_LOWER_MEM;
 215         hose_a->mem_space.end = K2_PCI32_UPPER_MEM;
 216         hose_a->io_base_virt = (void *)K2_ISA_IO_BASE;
 217
 218         setup_indirect_pci(hose_a, K2_PCI32_CONFIG_ADDR, K2_PCI32_CONFIG_DATA);
 219
 220         /* Initialize PCI32 bus registers */
 221         early_write_config_byte(hose_a,
 222                                 hose_a->first_busno,
 223                                 PCI_DEVFN(0, 0),
 224                                 CPC710_BUS_NUMBER, hose_a->first_busno);
 225
 226         early_write_config_byte(hose_a,
 227                                 hose_a->first_busno,
 228                                 PCI_DEVFN(0, 0),
 229                                 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
 230
 231         /* Enable PCI interrupt polling */
 232         early_write_config_byte(hose_a,
 233                                 hose_a->first_busno,
 234                                 PCI_DEVFN(8, 0), 0x45, 0x80);
 235
 236         /* Route polled PCI interrupts */
 237         early_write_config_byte(hose_a,
 238                                 hose_a->first_busno,
 239                                 PCI_DEVFN(8, 0), 0x48, 0x58);
 240
 241         early_write_config_byte(hose_a,
 242                                 hose_a->first_busno,
 243                                 PCI_DEVFN(8, 0), 0x49, 0x07);
 244
 245         early_write_config_byte(hose_a,
 246                                 hose_a->first_busno,
 247                                 PCI_DEVFN(8, 0), 0x4a, 0x31);
 248
 249         early_write_config_byte(hose_a,
 250                                 hose_a->first_busno,
 251                                 PCI_DEVFN(8, 0), 0x4b, 0xb9);
 252
 253         /* route secondary IDE channel interrupt to IRQ 15 */
 254         early_write_config_byte(hose_a,
 255                                 hose_a->first_busno,
 256                                 PCI_DEVFN(8, 0), 0x75, 0x0f);
 257
 258         /* enable IDE controller IDSEL */
 259         early_write_config_byte(hose_a,
 260                                 hose_a->first_busno,
 261                                 PCI_DEVFN(8, 0), 0x58, 0x48);
 262
 263         /* Enable IDE function */
 264         early_write_config_byte(hose_a,
 265                                 hose_a->first_busno,
 266                                 PCI_DEVFN(17, 0), 0x50, 0x03);
 267
 268         /* Set M5229 IDE controller to native mode */
 269         early_write_config_byte(hose_a,
 270                                 hose_a->first_busno,
 271                                 PCI_DEVFN(17, 0), PCI_CLASS_PROG, 0xdf);
 272
 273         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 274
 275         /* Write out correct max subordinate bus number for hose A */
 276         early_write_config_byte(hose_a,
 277                                 hose_a->first_busno,
 278                                 PCI_DEVFN(0, 0),
 279                                 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
 280
 281         /* Only setup PCI64 hose if we are in the system slot */
 282         if (!(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK)) {
 283                 /* Setup PCI64 hose */
 284                 hose_b = pcibios_alloc_controller();
 285                 if (!hose_b)
 286                         return;
 287
 288                 hose_b->first_busno = hose_a->last_busno + 1;
 289                 hose_b->last_busno = 0xff;
 290
 291                 /* Reminder: quit changing the following, it is correct. */
 292                 hose_b->pci_mem_offset = K2_PCI32_MEM_BASE;
 293
 294                 pci_init_resource(&hose_b->io_resource,
 295                                   K2_PCI64_LOWER_IO,
 296                                   K2_PCI64_UPPER_IO,
 297                                   IORESOURCE_IO, "PCI64 host bridge");
 298
 299                 pci_init_resource(&hose_b->mem_resources[0],
 300                                   K2_PCI64_LOWER_MEM + K2_PCI32_MEM_BASE,
 301                                   K2_PCI64_UPPER_MEM + K2_PCI32_MEM_BASE,
 302                                   IORESOURCE_MEM, "PCI64 host bridge");
 303
 304                 hose_b->io_space.start = K2_PCI64_LOWER_IO;
 305                 hose_b->io_space.end = K2_PCI64_UPPER_IO;
 306                 hose_b->mem_space.start = K2_PCI64_LOWER_MEM;
 307                 hose_b->mem_space.end = K2_PCI64_UPPER_MEM;
 308                 hose_b->io_base_virt = (void *)K2_ISA_IO_BASE;
 309
 310                 setup_indirect_pci(hose_b,
 311                                    K2_PCI64_CONFIG_ADDR, K2_PCI64_CONFIG_DATA);
 312
 313                 /* Initialize PCI64 bus registers */
 314                 early_write_config_byte(hose_b,
 315                                         0,
 316                                         PCI_DEVFN(0, 0),
 317                                         CPC710_SUB_BUS_NUMBER, 0xff);
 318
 319                 early_write_config_byte(hose_b,
 320                                         0,
 321                                         PCI_DEVFN(0, 0),
 322                                         CPC710_BUS_NUMBER, hose_b->first_busno);
 323
 324                 hose_b->last_busno = pciauto_bus_scan(hose_b,
 325                                                       hose_b->first_busno);
 326
 327                 /* Write out correct max subordinate bus number for hose B */
 328                 early_write_config_byte(hose_b,
 329                                         hose_b->first_busno,
 330                                         PCI_DEVFN(0, 0),
 331                                         CPC710_SUB_BUS_NUMBER,
 332                                         hose_b->last_busno);
 333
 334                 /* Configure PCI64 PSBAR */
 335                 early_write_config_dword(hose_b,
 336                                          hose_b->first_busno,
 337                                          PCI_DEVFN(0, 0),
 338                                          PCI_BASE_ADDRESS_0,
 339                                          K2_PCI64_SYS_MEM_BASE);
 340         }
 341
 342         /* Configure i8259 level/edge settings */
 343         outb(0x62, 0x4d0);
 344         outb(0xde, 0x4d1);
 345
 346 #ifdef CONFIG_CPC710_DATA_GATHERING
 347         {
 348                 unsigned int tmp;
 349                 tmp = __raw_readl(ABCNTL);
 350                 /* Enable data gathering on both PCI interfaces */
 351                 __raw_writel(tmp | 0x05000000, ABCNTL);
 352         }
 353 #endif
 354
 355         ppc_md.pcibios_fixup = k2_pcibios_fixup;
 356         ppc_md.pcibios_fixup_resources = k2_pcibios_fixup_resources;
 357         ppc_md.pci_swizzle = common_swizzle;
 358         ppc_md.pci_map_irq = k2_map_irq;
 359 }
 360
 361 static int k2_get_bus_speed(void)
 362 {
 363         int bus_speed;
 364         unsigned char board_id;
 365
 366         board_id = *(unsigned char *)K2_BOARD_ID_REG;
 367
 368         switch (K2_BUS_SPD(board_id)) {
 369
 370         case 0:
 371         default:
 372                 bus_speed = 100000000;
 373                 break;
 374
 375         case 1:
 376                 bus_speed = 83333333;
 377                 break;
 378
 379         case 2:
 380                 bus_speed = 75000000;
 381                 break;
 382
 383         case 3:
 384                 bus_speed = 66666666;
 385                 break;
 386         }
 387         return bus_speed;
 388 }
 389
 390 static int k2_get_cpu_speed(void)
 391 {
 392         unsigned long hid1;
 393         int cpu_speed;
 394
 395         hid1 = mfspr(SPRN_HID1) >> 28;
 396
 397         if ((mfspr(SPRN_PVR) >> 16) == 8)
 398                 hid1 = cpu_7xx[hid1];
 399         else
 400                 hid1 = cpu_6xx[hid1];
 401
 402         cpu_speed = k2_get_bus_speed() * hid1 / 2;
 403         return cpu_speed;
 404 }
 405
 406 static void __init k2_calibrate_decr(void)
 407 {
 408         int freq, divisor = 4;
 409
 410         /* determine processor bus speed */
 411         freq = k2_get_bus_speed();
 412         tb_ticks_per_jiffy = freq / HZ / divisor;
 413         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
 414 }
 415
 416 static int k2_show_cpuinfo(struct seq_file *m)
 417 {
 418         unsigned char k2_geo_bits, k2_system_slot;
 419
 420         seq_printf(m, "vendor\t\t: SBS\n");
 421         seq_printf(m, "machine\t\t: K2\n");
 422         seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed() / 1000000);
 423         seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed() / 1000000);
 424         seq_printf(m, "memory type\t: SDRAM\n");
 425
 426         k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
 427         k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
 428         seq_printf(m, "backplane\t: %s slot board",
 429                    k2_system_slot ? "System" : "Non system");
 430         seq_printf(m, "with geographical address %x\n", k2_geo_bits);
 431
 432         return 0;
 433 }
 434
 435 TODC_ALLOC();
 436
 437 static void __init k2_setup_arch(void)
 438 {
 439         unsigned int cpu;
 440
 441         /* Setup TODC access */
 442         TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
 443                   ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE), 8);
 444
 445         /* init to some ~sane value until calibrate_delay() runs */
 446         loops_per_jiffy = 50000000 / HZ;
 447
 448         /* make FLASH transactions higher priority than PCI to avoid deadlock */
 449         __raw_writel(__raw_readl(SIOC1) | 0x80000000, SIOC1);
 450
 451         /* Set hardware to access FLASH page 2 */
 452         __raw_writel(1 << 29, GPOUT);
 453
 454         /* Setup PCI host bridges */
 455         k2_setup_hoses();
 456
 457 #ifdef CONFIG_BLK_DEV_INITRD
 458         if (initrd_start)
 459                 ROOT_DEV = Root_RAM0;
 460         else
 461 #endif
 462 #ifdef CONFIG_ROOT_NFS
 463                 ROOT_DEV = Root_NFS;
 464 #else
 465                 ROOT_DEV = Root_HDC1;
 466 #endif
 467
 468         /* Identify the system */
 469         printk(KERN_INFO "System Identification: SBS K2 - PowerPC 750 @ "
 470                         "%d Mhz\n", k2_get_cpu_speed() / 1000000);
 471         printk(KERN_INFO "Port by MontaVista Software, Inc. "
 472                         "(source@mvista.com)\n");
 473
 474         /* Identify the CPU manufacturer */
 475         cpu = PVR_REV(mfspr(SPRN_PVR));
 476         printk(KERN_INFO "CPU manufacturer: %s [rev=%04x]\n",
 477                         (cpu & (1 << 15)) ? "IBM" : "Motorola", cpu);
 478 }
 479
 480 static void k2_restart(char *cmd)
 481 {
 482         local_irq_disable();
 483
 484         /* Flip FLASH back to page 1 to access firmware image */
 485         __raw_writel(0, GPOUT);
 486
 487         /* SRR0 has system reset vector, SRR1 has default MSR value */
 488         /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
 489         mtspr(SPRN_SRR0, 0xfff00100);
 490         mtspr(SPRN_SRR1, 0);
 491         __asm__ __volatile__("rfi\n\t");
 492
 493         /* not reached */
 494         for (;;) ;
 495 }
 496
 497 static void k2_power_off(void)
 498 {
 499         for (;;) ;
 500 }
 501
 502 static void k2_halt(void)
 503 {
 504         k2_restart(NULL);
 505 }
 506
 507 /*
 508  * Set BAT 3 to map PCI32 I/O space.
 509  */
 510 static __inline__ void k2_set_bat(void)
 511 {
 512         /* wait for all outstanding memory accesses to complete */
 513         mb();
 514
 515         /* setup DBATs */
 516         mtspr(SPRN_DBAT2U, 0x80001ffe);
 517         mtspr(SPRN_DBAT2L, 0x8000002a);
 518         mtspr(SPRN_DBAT3U, 0xf0001ffe);
 519         mtspr(SPRN_DBAT3L, 0xf000002a);
 520
 521         /* wait for updates */
 522         mb();
 523 }
 524
 525 static unsigned long __init k2_find_end_of_memory(void)
 526 {
 527         unsigned long total;
 528         unsigned char msize = 7;        /* Default to 128MB */
 529
 530         msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));
 531
 532         switch (msize) {
 533         case 2:
 534                 /*
 535                  * This will break without a lowered
 536                  * KERNELBASE or CONFIG_HIGHMEM on.
 537                  * It seems non 1GB builds exist yet,
 538                  * though.
 539                  */
 540                 total = K2_MEM_SIZE_1GB;
 541                 break;
 542         case 3:
 543         case 4:
 544                 total = K2_MEM_SIZE_512MB;
 545                 break;
 546         case 5:
 547         case 6:
 548                 total = K2_MEM_SIZE_256MB;
 549                 break;
 550         case 7:
 551                 total = K2_MEM_SIZE_128MB;
 552                 break;
 553         default:
 554                 printk
 555                     ("K2: Invalid memory size detected, defaulting to 128MB\n");
 556                 total = K2_MEM_SIZE_128MB;
 557                 break;
 558         }
 559         return total;
 560 }
 561
 562 static void __init k2_map_io(void)
 563 {
 564         io_block_mapping(K2_PCI32_IO_BASE,
 565                          K2_PCI32_IO_BASE, 0x00200000, _PAGE_IO);
 566         io_block_mapping(0xff000000, 0xff000000, 0x01000000, _PAGE_IO);
 567 }
 568
 569 static void __init k2_init_irq(void)
 570 {
 571         int i;
 572
 573         for (i = 0; i < 16; i++)
 574                 irq_desc[i].handler = &i8259_pic;
 575
 576         i8259_init(0);
 577 }
 578
 579 void __init platform_init(unsigned long r3, unsigned long r4,
 580                           unsigned long r5, unsigned long r6, unsigned long r7)
 581 {
 582         parse_bootinfo((struct bi_record *)(r3 + KERNELBASE));
 583
 584         k2_set_bat();
 585
 586         isa_io_base = K2_ISA_IO_BASE;
 587         isa_mem_base = K2_ISA_MEM_BASE;
 588         pci_dram_offset = K2_PCI32_SYS_MEM_BASE;
 589
 590         ppc_md.setup_arch = k2_setup_arch;
 591         ppc_md.show_cpuinfo = k2_show_cpuinfo;
 592         ppc_md.init_IRQ = k2_init_irq;
 593         ppc_md.get_irq = i8259_irq;
 594
 595         ppc_md.find_end_of_memory = k2_find_end_of_memory;
 596         ppc_md.setup_io_mappings = k2_map_io;
 597
 598         ppc_md.restart = k2_restart;
 599         ppc_md.power_off = k2_power_off;
 600         ppc_md.halt = k2_halt;
 601
 602         ppc_md.time_init = todc_time_init;
 603         ppc_md.set_rtc_time = todc_set_rtc_time;
 604         ppc_md.get_rtc_time = todc_get_rtc_time;
 605         ppc_md.calibrate_decr = k2_calibrate_decr;
 606
 607         ppc_md.nvram_read_val = todc_direct_read_val;
 608         ppc_md.nvram_write_val = todc_direct_write_val;
 609
 610 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 611         ppc_md.progress = gen550_progress;
 612 #endif
 613 }