arch/ppc/platforms/pmac_smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/smp.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kernel_stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/errno.h>
  35 #include <linux/hardirq.h>
  36
  37 #include <asm/ptrace.h>
  38 #include <asm/atomic.h>
  39 #include <asm/irq.h>
  40 #include <asm/page.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/sections.h>
  43 #include <asm/io.h>
  44 #include <asm/prom.h>
  45 #include <asm/smp.h>
  46 #include <asm/residual.h>
  47 #include <asm/machdep.h>
  48 #include <asm/pmac_feature.h>
  49 #include <asm/time.h>
  50 #include <asm/open_pic.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/keylargo.h>
  53
  54 /*
  55  * Powersurge (old powermac SMP) support.
  56  */
  57
  58 extern void __secondary_start_psurge(void);
  59 extern void __secondary_start_psurge2(void);    /* Temporary horrible hack */
  60 extern void __secondary_start_psurge3(void);    /* Temporary horrible hack */
  61
  62 /* Addresses for powersurge registers */
  63 #define HAMMERHEAD_BASE         0xf8000000
  64 #define HHEAD_CONFIG            0x90
  65 #define HHEAD_SEC_INTR          0xc0
  66
  67 /* register for interrupting the primary processor on the powersurge */
  68 /* N.B. this is actually the ethernet ROM! */
  69 #define PSURGE_PRI_INTR         0xf3019000
  70
  71 /* register for storing the start address for the secondary processor */
  72 /* N.B. this is the PCI config space address register for the 1st bridge */
  73 #define PSURGE_START            0xf2800000
  74
  75 /* Daystar/XLR8 4-CPU card */
  76 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  77
  78 #define PSURGE_QUAD_IRQ_SET     0
  79 #define PSURGE_QUAD_IRQ_CLR     1
  80 #define PSURGE_QUAD_IRQ_PRIMARY 2
  81 #define PSURGE_QUAD_CKSTOP_CTL  3
  82 #define PSURGE_QUAD_PRIMARY_ARB 4
  83 #define PSURGE_QUAD_BOARD_ID    6
  84 #define PSURGE_QUAD_WHICH_CPU   7
  85 #define PSURGE_QUAD_CKSTOP_RDBK 8
  86 #define PSURGE_QUAD_RESET_CTL   11
  87
  88 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
  89 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
  90 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
  91 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
  92
  93 /* virtual addresses for the above */
  94 static volatile u8 *hhead_base;
  95 static volatile u8 *quad_base;
  96 static volatile u32 *psurge_pri_intr;
  97 static volatile u8 *psurge_sec_intr;
  98 static volatile u32 *psurge_start;
  99
 100 /* values for psurge_type */
 101 #define PSURGE_NONE             -1
 102 #define PSURGE_DUAL             0
 103 #define PSURGE_QUAD_OKEE        1
 104 #define PSURGE_QUAD_COTTON      2
 105 #define PSURGE_QUAD_ICEGRASS    3
 106
 107 /* what sort of powersurge board we have */
 108 static int psurge_type = PSURGE_NONE;
 109
 110 /* L2 and L3 cache settings to pass from CPU0 to CPU1 */
 111 volatile static long int core99_l2_cache;
 112 volatile static long int core99_l3_cache;
 113
 114 /* Timebase freeze GPIO */
 115 static unsigned int core99_tb_gpio;
 116
 117 /* Sync flag for HW tb sync */
 118 static volatile int sec_tb_reset = 0;
 119
 120 static void __init core99_init_caches(int cpu)
 121 {
 122         if (!cpu_has_feature(CPU_FTR_L2CR))
 123                 return;
 124
 125         if (cpu == 0) {
 126                 core99_l2_cache = _get_L2CR();
 127                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 128         } else {
 129                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 130                 _set_L2CR(0);
 131                 _set_L2CR(core99_l2_cache);
 132                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 133         }
 134
 135         if (!cpu_has_feature(CPU_FTR_L3CR))
 136                 return;
 137
 138         if (cpu == 0){
 139                 core99_l3_cache = _get_L3CR();
 140                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 141         } else {
 142                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 143                 _set_L3CR(0);
 144                 _set_L3CR(core99_l3_cache);
 145                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 146         }
 147 }
 148
 149 /*
 150  * Set and clear IPIs for powersurge.
 151  */
 152 static inline void psurge_set_ipi(int cpu)
 153 {
 154         if (psurge_type == PSURGE_NONE)
 155                 return;
 156         if (cpu == 0)
 157                 in_be32(psurge_pri_intr);
 158         else if (psurge_type == PSURGE_DUAL)
 159                 out_8(psurge_sec_intr, 0);
 160         else
 161                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 162 }
 163
 164 static inline void psurge_clr_ipi(int cpu)
 165 {
 166         if (cpu > 0) {
 167                 switch(psurge_type) {
 168                 case PSURGE_DUAL:
 169                         out_8(psurge_sec_intr, ~0);
 170                 case PSURGE_NONE:
 171                         break;
 172                 default:
 173                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 174                 }
 175         }
 176 }
 177
 178 /*
 179  * On powersurge (old SMP powermac architecture) we don't have
 180  * separate IPIs for separate messages like openpic does.  Instead
 181  * we have a bitmap for each processor, where a 1 bit means that
 182  * the corresponding message is pending for that processor.
 183  * Ideally each cpu's entry would be in a different cache line.
 184  *  -- paulus.
 185  */
 186 static unsigned long psurge_smp_message[NR_CPUS];
 187
 188 void __pmac psurge_smp_message_recv(struct pt_regs *regs)
 189 {
 190         int cpu = smp_processor_id();
 191         int msg;
 192
 193         /* clear interrupt */
 194         psurge_clr_ipi(cpu);
 195
 196         if (num_online_cpus() < 2)
 197                 return;
 198
 199         /* make sure there is a message there */
 200         for (msg = 0; msg < 4; msg++)
 201                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
 202                         smp_message_recv(msg, regs);
 203 }
 204
 205 irqreturn_t __pmac psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
 206 {
 207         psurge_smp_message_recv(regs);
 208         return IRQ_HANDLED;
 209 }
 210
 211 static void __pmac smp_psurge_message_pass(int target, int msg, unsigned long data,
 212                                            int wait)
 213 {
 214         int i;
 215
 216         if (num_online_cpus() < 2)
 217                 return;
 218
 219         for (i = 0; i < NR_CPUS; i++) {
 220                 if (!cpu_online(i))
 221                         continue;
 222                 if (target == MSG_ALL
 223                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
 224                     || target == i) {
 225                         set_bit(msg, &psurge_smp_message[i]);
 226                         psurge_set_ipi(i);
 227                 }
 228         }
 229 }
 230
 231 /*
 232  * Determine a quad card presence. We read the board ID register, we
 233  * force the data bus to change to something else, and we read it again.
 234  * It it's stable, then the register probably exist (ugh !)
 235  */
 236 static int __init psurge_quad_probe(void)
 237 {
 238         int type;
 239         unsigned int i;
 240
 241         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 242         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 243             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 244                 return PSURGE_DUAL;
 245
 246         /* looks OK, try a slightly more rigorous test */
 247         /* bogus is not necessarily cacheline-aligned,
 248            though I don't suppose that really matters.  -- paulus */
 249         for (i = 0; i < 100; i++) {
 250                 volatile u32 bogus[8];
 251                 bogus[(0+i)%8] = 0x00000000;
 252                 bogus[(1+i)%8] = 0x55555555;
 253                 bogus[(2+i)%8] = 0xFFFFFFFF;
 254                 bogus[(3+i)%8] = 0xAAAAAAAA;
 255                 bogus[(4+i)%8] = 0x33333333;
 256                 bogus[(5+i)%8] = 0xCCCCCCCC;
 257                 bogus[(6+i)%8] = 0xCCCCCCCC;
 258                 bogus[(7+i)%8] = 0x33333333;
 259                 wmb();
 260                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 261                 mb();
 262                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 263                         return PSURGE_DUAL;
 264         }
 265         return type;
 266 }
 267
 268 static void __init psurge_quad_init(void)
 269 {
 270         int procbits;
 271
 272         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 273         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 274         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 275                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 276         else
 277                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 278         mdelay(33);
 279         out_8(psurge_sec_intr, ~0);
 280         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 281         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 282         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 283                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 284         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 285         mdelay(33);
 286         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 287         mdelay(33);
 288         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 289         mdelay(33);
 290 }
 291
 292 static int __init smp_psurge_probe(void)
 293 {
 294         int i, ncpus;
 295
 296         /* We don't do SMP on the PPC601 -- paulus */
 297         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
 298                 return 1;
 299
 300         /*
 301          * The powersurge cpu board can be used in the generation
 302          * of powermacs that have a socket for an upgradeable cpu card,
 303          * including the 7500, 8500, 9500, 9600.
 304          * The device tree doesn't tell you if you have 2 cpus because
 305          * OF doesn't know anything about the 2nd processor.
 306          * Instead we look for magic bits in magic registers,
 307          * in the hammerhead memory controller in the case of the
 308          * dual-cpu powersurge board.  -- paulus.
 309          */
 310         if (find_devices("hammerhead") == NULL)
 311                 return 1;
 312
 313         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 314         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 315         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 316
 317         psurge_type = psurge_quad_probe();
 318         if (psurge_type != PSURGE_DUAL) {
 319                 psurge_quad_init();
 320                 /* All released cards using this HW design have 4 CPUs */
 321                 ncpus = 4;
 322         } else {
 323                 iounmap((void *) quad_base);
 324                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 325                         /* not a dual-cpu card */
 326                         iounmap((void *) hhead_base);
 327                         psurge_type = PSURGE_NONE;
 328                         return 1;
 329                 }
 330                 ncpus = 2;
 331         }
 332
 333         psurge_start = ioremap(PSURGE_START, 4);
 334         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 335
 336         /* this is not actually strictly necessary -- paulus. */
 337         for (i = 1; i < ncpus; ++i)
 338                 smp_hw_index[i] = i;
 339
 340         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 341
 342         return ncpus;
 343 }
 344
 345 static void __init smp_psurge_kick_cpu(int nr)
 346 {
 347         void (*start)(void) = __secondary_start_psurge;
 348         unsigned long a;
 349
 350         /* may need to flush here if secondary bats aren't setup */
 351         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 352                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 353         asm volatile("sync");
 354
 355         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 356
 357         /* setup entry point of secondary processor */
 358         switch (nr) {
 359         case 2:
 360                 start = __secondary_start_psurge2;
 361                 break;
 362         case 3:
 363                 start = __secondary_start_psurge3;
 364                 break;
 365         }
 366
 367         out_be32(psurge_start, __pa(start));
 368         mb();
 369
 370         psurge_set_ipi(nr);
 371         udelay(10);
 372         psurge_clr_ipi(nr);
 373
 374         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 375 }
 376
 377 /*
 378  * With the dual-cpu powersurge board, the decrementers and timebases
 379  * of both cpus are frozen after the secondary cpu is started up,
 380  * until we give the secondary cpu another interrupt.  This routine
 381  * uses this to get the timebases synchronized.
 382  *  -- paulus.
 383  */
 384 static void __init psurge_dual_sync_tb(int cpu_nr)
 385 {
 386         int t;
 387
 388         set_dec(tb_ticks_per_jiffy);
 389         set_tb(0, 0);
 390         last_jiffy_stamp(cpu_nr) = 0;
 391
 392         if (cpu_nr > 0) {
 393                 mb();
 394                 sec_tb_reset = 1;
 395                 return;
 396         }
 397
 398         /* wait for the secondary to have reset its TB before proceeding */
 399         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
 400                 ;
 401
 402         /* now interrupt the secondary, starting both TBs */
 403         psurge_set_ipi(1);
 404
 405         smp_tb_synchronized = 1;
 406 }
 407
 408 static struct irqaction psurge_irqaction = {
 409         .handler = psurge_primary_intr,
 410         .flags = SA_INTERRUPT,
 411         .mask = CPU_MASK_NONE,
 412         .name = "primary IPI",
 413 };
 414
 415 static void __init smp_psurge_setup_cpu(int cpu_nr)
 416 {
 417
 418         if (cpu_nr == 0) {
 419                 /* If we failed to start the second CPU, we should still
 420                  * send it an IPI to start the timebase & DEC or we might
 421                  * have them stuck.
 422                  */
 423                 if (num_online_cpus() < 2) {
 424                         if (psurge_type == PSURGE_DUAL)
 425                                 psurge_set_ipi(1);
 426                         return;
 427                 }
 428                 /* reset the entry point so if we get another intr we won't
 429                  * try to startup again */
 430                 out_be32(psurge_start, 0x100);
 431                 if (setup_irq(30, &psurge_irqaction))
 432                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
 433         }
 434
 435         if (psurge_type == PSURGE_DUAL)
 436                 psurge_dual_sync_tb(cpu_nr);
 437 }
 438
 439 void __init smp_psurge_take_timebase(void)
 440 {
 441         /* Dummy implementation */
 442 }
 443
 444 void __init smp_psurge_give_timebase(void)
 445 {
 446         /* Dummy implementation */
 447 }
 448
 449 static int __init smp_core99_probe(void)
 450 {
 451 #ifdef CONFIG_6xx
 452         extern int powersave_nap;
 453 #endif
 454         struct device_node *cpus, *firstcpu;
 455         int i, ncpus = 0, boot_cpu = -1;
 456         u32 *tbprop;
 457
 458         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 459         cpus = firstcpu = find_type_devices("cpu");
 460         while(cpus != NULL) {
 461                 u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
 462                 char *stateprop = (char *)get_property(cpus, "state", NULL);
 463                 if (regprop != NULL && stateprop != NULL &&
 464                     !strncmp(stateprop, "running", 7))
 465                         boot_cpu = *regprop;
 466                 ++ncpus;
 467                 cpus = cpus->next;
 468         }
 469         if (boot_cpu == -1)
 470                 printk(KERN_WARNING "Couldn't detect boot CPU !\n");
 471         if (boot_cpu != 0)
 472                 printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
 473
 474         if (machine_is_compatible("MacRISC4")) {
 475                 extern struct smp_ops_t core99_smp_ops;
 476
 477                 core99_smp_ops.take_timebase = smp_generic_take_timebase;
 478                 core99_smp_ops.give_timebase = smp_generic_give_timebase;
 479         } else {
 480                 if (firstcpu != NULL)
 481                         tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
 482                 if (tbprop)
 483                         core99_tb_gpio = *tbprop;
 484                 else
 485                         core99_tb_gpio = KL_GPIO_TB_ENABLE;
 486         }
 487
 488         if (ncpus > 1) {
 489                 openpic_request_IPIs();
 490                 for (i = 1; i < ncpus; ++i)
 491                         smp_hw_index[i] = i;
 492 #ifdef CONFIG_6xx
 493                 powersave_nap = 0;
 494 #endif
 495                 core99_init_caches(0);
 496         }
 497
 498         return ncpus;
 499 }
 500
 501 static void __init smp_core99_kick_cpu(int nr)
 502 {
 503         unsigned long save_vector, new_vector;
 504         unsigned long flags;
 505
 506         volatile unsigned long *vector
 507                  = ((volatile unsigned long *)(KERNELBASE+0x100));
 508         if (nr < 1 || nr > 3)
 509                 return;
 510         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
 511
 512         local_irq_save(flags);
 513         local_irq_disable();
 514
 515         /* Save reset vector */
 516         save_vector = *vector;
 517
 518         /* Setup fake reset vector that does
 519          *   b __secondary_start_psurge - KERNELBASE
 520          */
 521         switch(nr) {
 522                 case 1:
 523                         new_vector = (unsigned long)__secondary_start_psurge;
 524                         break;
 525                 case 2:
 526                         new_vector = (unsigned long)__secondary_start_psurge2;
 527                         break;
 528                 case 3:
 529                         new_vector = (unsigned long)__secondary_start_psurge3;
 530                         break;
 531         }
 532         *vector = 0x48000002 + new_vector - KERNELBASE;
 533
 534         /* flush data cache and inval instruction cache */
 535         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 536
 537         /* Put some life in our friend */
 538         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 539
 540         /* FIXME: We wait a bit for the CPU to take the exception, I should
 541          * instead wait for the entry code to set something for me. Well,
 542          * ideally, all that crap will be done in prom.c and the CPU left
 543          * in a RAM-based wait loop like CHRP.
 544          */
 545         mdelay(1);
 546
 547         /* Restore our exception vector */
 548         *vector = save_vector;
 549         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 550
 551         local_irq_restore(flags);
 552         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 553 }
 554
 555 static void __init smp_core99_setup_cpu(int cpu_nr)
 556 {
 557         /* Setup L2/L3 */
 558         if (cpu_nr != 0)
 559                 core99_init_caches(cpu_nr);
 560
 561         /* Setup openpic */
 562         do_openpic_setup_cpu();
 563
 564         if (cpu_nr == 0) {
 565 #ifdef CONFIG_POWER4
 566                 extern void g5_phy_disable_cpu1(void);
 567
 568                 /* If we didn't start the second CPU, we must take
 569                  * it off the bus
 570                  */
 571                 if (machine_is_compatible("MacRISC4") &&
 572                     num_online_cpus() < 2)
 573                         g5_phy_disable_cpu1();
 574 #endif /* CONFIG_POWER4 */
 575                 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
 576         }
 577 }
 578
 579 void __init smp_core99_take_timebase(void)
 580 {
 581         /* Secondary processor "takes" the timebase by freezing
 582          * it, resetting its local TB and telling CPU 0 to go on
 583          */
 584         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 585         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 586         mb();
 587
 588         set_dec(tb_ticks_per_jiffy);
 589         set_tb(0, 0);
 590         last_jiffy_stamp(smp_processor_id()) = 0;
 591
 592         mb();
 593         sec_tb_reset = 1;
 594 }
 595
 596 void __init smp_core99_give_timebase(void)
 597 {
 598         unsigned int t;
 599
 600         /* Primary processor waits for secondary to have frozen
 601          * the timebase, resets local TB, and kick timebase again
 602          */
 603         /* wait for the secondary to have reset its TB before proceeding */
 604         for (t = 1000; t > 0 && !sec_tb_reset; --t)
 605                 udelay(1000);
 606         if (t == 0)
 607                 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
 608
 609         set_dec(tb_ticks_per_jiffy);
 610         set_tb(0, 0);
 611         last_jiffy_stamp(smp_processor_id()) = 0;
 612         mb();
 613
 614         /* Now, restart the timebase by leaving the GPIO to an open collector */
 615         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 616         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 617
 618         smp_tb_synchronized = 1;
 619 }
 620
 621
 622 /* PowerSurge-style Macs */
 623 struct smp_ops_t psurge_smp_ops __pmacdata = {
 624         .message_pass   = smp_psurge_message_pass,
 625         .probe          = smp_psurge_probe,
 626         .kick_cpu       = smp_psurge_kick_cpu,
 627         .setup_cpu      = smp_psurge_setup_cpu,
 628         .give_timebase  = smp_psurge_give_timebase,
 629         .take_timebase  = smp_psurge_take_timebase,
 630 };
 631
 632 /* Core99 Macs (dual G4s) */
 633 struct smp_ops_t core99_smp_ops __pmacdata = {
 634         .message_pass   = smp_openpic_message_pass,
 635         .probe          = smp_core99_probe,
 636         .kick_cpu       = smp_core99_kick_cpu,
 637         .setup_cpu      = smp_core99_setup_cpu,
 638         .give_timebase  = smp_core99_give_timebase,
 639         .take_timebase  = smp_core99_take_timebase,
 640 };