2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
14 * Do not include directly; use <linux/atomic.h>.
17 #ifndef _ASM_TILE_ATOMIC_64_H
18 #define _ASM_TILE_ATOMIC_64_H
22 #include <asm/barrier.h>
23 #include <arch/spr_def.h>
25 /* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
27 #define atomic_set(v, i) ((v)->counter = (i))
30 * The smp_mb() operations throughout are to support the fact that
31 * Linux requires memory barriers before and after the operation,
32 * on any routine which updates memory and returns a value.
35 static inline void atomic_add(int i, atomic_t *v)
37 __insn_fetchadd4((void *)&v->counter, i);
40 static inline int atomic_add_return(int i, atomic_t *v)
43 smp_mb(); /* barrier for proper semantics */
44 val = __insn_fetchadd4((void *)&v->counter, i) + i;
45 barrier(); /* the "+ i" above will wait on memory */
49 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
51 int guess, oldval = v->counter;
56 oldval = cmpxchg(&v->counter, guess, guess + a);
57 } while (guess != oldval);
61 #define CONFIG_ARCH_HAS_ATOMIC_OR
63 static inline void atomic_and(int i, atomic_t *v)
65 __insn_fetchand4((void *)&v->counter, i);
68 static inline void atomic_or(int i, atomic_t *v)
70 __insn_fetchor4((void *)&v->counter, i);
73 static inline void atomic_xor(int i, atomic_t *v)
75 int guess, oldval = v->counter;
78 __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
79 oldval = __insn_cmpexch4(&v->counter, guess ^ i);
80 } while (guess != oldval);
83 /* Now the true 64-bit operations. */
85 #define ATOMIC64_INIT(i) { (i) }
87 #define atomic64_read(v) ((v)->counter)
88 #define atomic64_set(v, i) ((v)->counter = (i))
90 static inline void atomic64_add(long i, atomic64_t *v)
92 __insn_fetchadd((void *)&v->counter, i);
95 static inline long atomic64_add_return(long i, atomic64_t *v)
98 smp_mb(); /* barrier for proper semantics */
99 val = __insn_fetchadd((void *)&v->counter, i) + i;
100 barrier(); /* the "+ i" above will wait on memory */
104 static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
106 long guess, oldval = v->counter;
111 oldval = cmpxchg(&v->counter, guess, guess + a);
112 } while (guess != oldval);
116 static inline void atomic64_and(long i, atomic64_t *v)
118 __insn_fetchand((void *)&v->counter, i);
121 static inline void atomic64_or(long i, atomic64_t *v)
123 __insn_fetchor((void *)&v->counter, i);
126 static inline void atomic64_xor(long i, atomic64_t *v)
128 long guess, oldval = v->counter;
131 __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
132 oldval = __insn_cmpexch(&v->counter, guess ^ i);
133 } while (guess != oldval);
136 #define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
137 #define atomic64_sub(i, v) atomic64_add(-(i), (v))
138 #define atomic64_inc_return(v) atomic64_add_return(1, (v))
139 #define atomic64_dec_return(v) atomic64_sub_return(1, (v))
140 #define atomic64_inc(v) atomic64_add(1, (v))
141 #define atomic64_dec(v) atomic64_sub(1, (v))
143 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
144 #define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
145 #define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
146 #define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
148 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
150 #endif /* !__ASSEMBLY__ */
152 #endif /* _ASM_TILE_ATOMIC_64_H */