2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_BARRIER_H
16 #define _ASM_TILE_BARRIER_H
20 #include <linux/types.h>
21 #include <arch/chip.h>
22 #include <arch/spr_def.h>
23 #include <asm/timex.h>
26 * read_barrier_depends - Flush all pending reads that subsequents reads
29 * No data-dependent reads from memory-like regions are ever reordered
30 * over this barrier. All reads preceding this primitive are guaranteed
31 * to access memory (but not necessarily other CPUs' caches) before any
32 * reads following this primitive that depend on the data return by
33 * any of the preceding reads. This primitive is much lighter weight than
34 * rmb() on most CPUs, and is never heavier weight than is
37 * These ordering constraints are respected by both the local CPU
40 * Ordering is not guaranteed by anything other than these primitives,
41 * not even by data dependencies. See the documentation for
42 * memory_barrier() for examples and URLs to more information.
44 * For example, the following code would force ordering (the initial
45 * value of "a" is zero, "b" is one, and "p" is "&a"):
53 * read_barrier_depends();
57 * because the read of "*q" depends on the read of "p" and these
58 * two reads are separated by a read_barrier_depends(). However,
59 * the following code, with the same initial values for "a" and "b":
67 * read_barrier_depends();
71 * does not enforce ordering, since there is no data dependency between
72 * the read of "a" and the read of "b". Therefore, on some CPUs, such
73 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
74 * in cases like this where there are no data dependencies.
76 #define read_barrier_depends() do { } while (0)
78 #define __sync() __insn_mf()
80 #include <hv/syscall_public.h>
82 * Issue an uncacheable load to each memory controller, then
83 * wait until those loads have completed.
85 static inline void __mb_incoherent(void)
89 : "=R10" (clobber_r10)
90 : "R10" (HV_SYS_fence_incoherent)
91 : "r0", "r1", "r2", "r3", "r4",
92 "r5", "r6", "r7", "r8", "r9",
93 "r11", "r12", "r13", "r14",
94 "r15", "r16", "r17", "r18", "r19",
95 "r20", "r21", "r22", "r23", "r24",
96 "r25", "r26", "r27", "r28", "r29");
99 /* Fence to guarantee visibility of stores to incoherent memory. */
106 #if CHIP_HAS_TILE_WRITE_PENDING()
107 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
108 unsigned long start = get_cycles_low();
110 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
112 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
113 #endif /* CHIP_HAS_TILE_WRITE_PENDING() */
114 (void) __mb_incoherent();
118 #define fast_wmb() __sync()
119 #define fast_rmb() __sync()
120 #define fast_mb() __sync()
121 #define fast_iob() mb_incoherent()
123 #define wmb() fast_wmb()
124 #define rmb() fast_rmb()
125 #define mb() fast_mb()
126 #define iob() fast_iob()
129 #define smp_mb() mb()
130 #define smp_rmb() rmb()
131 #define smp_wmb() wmb()
132 #define smp_read_barrier_depends() read_barrier_depends()
134 #define smp_mb() barrier()
135 #define smp_rmb() barrier()
136 #define smp_wmb() barrier()
137 #define smp_read_barrier_depends() do { } while (0)
140 #define set_mb(var, value) \
141 do { var = value; mb(); } while (0)
143 #endif /* !__ASSEMBLY__ */
144 #endif /* _ASM_TILE_BARRIER_H */