arch/x86/events/intel/cstate.c

   1 /*
   2  * perf_event_intel_cstate.c: support cstate residency counters
   3  *
   4  * Copyright (C) 2015, Intel Corp.
   5  * Author: Kan Liang (kan.liang@intel.com)
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Library General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Library General Public License for more details.
  16  *
  17  */
  18
  19 /*
  20  * This file export cstate related free running (read-only) counters
  21  * for perf. These counters may be use simultaneously by other tools,
  22  * such as turbostat. However, it still make sense to implement them
  23  * in perf. Because we can conveniently collect them together with
  24  * other events, and allow to use them from tools without special MSR
  25  * access code.
  26  *
  27  * The events only support system-wide mode counting. There is no
  28  * sampling support because it is not supported by the hardware.
  29  *
  30  * According to counters' scope and category, two PMUs are registered
  31  * with the perf_event core subsystem.
  32  *  - 'cstate_core': The counter is available for each physical core.
  33  *    The counters include CORE_C*_RESIDENCY.
  34  *  - 'cstate_pkg': The counter is available for each physical package.
  35  *    The counters include PKG_C*_RESIDENCY.
  36  *
  37  * All of these counters are specified in the Intel® 64 and IA-32
  38  * Architectures Software Developer.s Manual Vol3b.
  39  *
  40  * Model specific counters:
  41  *      MSR_CORE_C1_RES: CORE C1 Residency Counter
  42  *                       perf code: 0x00
  43  *                       Available model: SLM,AMT
  44  *                       Scope: Core (each processor core has a MSR)
  45  *      MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  46  *                             perf code: 0x01
  47  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
  48  *                             Scope: Core
  49  *      MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  50  *                             perf code: 0x02
  51  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
  52  *                                              SKL,KNL
  53  *                             Scope: Core
  54  *      MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  55  *                             perf code: 0x03
  56  *                             Available model: SNB,IVB,HSW,BDW,SKL
  57  *                             Scope: Core
  58  *      MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  59  *                             perf code: 0x00
  60  *                             Available model: SNB,IVB,HSW,BDW,SKL,KNL
  61  *                             Scope: Package (physical package)
  62  *      MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  63  *                             perf code: 0x01
  64  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
  65  *                             Scope: Package (physical package)
  66  *      MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  67  *                             perf code: 0x02
  68  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
  69  *                                              SKL,KNL
  70  *                             Scope: Package (physical package)
  71  *      MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  72  *                             perf code: 0x03
  73  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
  74  *                             Scope: Package (physical package)
  75  *      MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  76  *                             perf code: 0x04
  77  *                             Available model: HSW ULT only
  78  *                             Scope: Package (physical package)
  79  *      MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  80  *                             perf code: 0x05
  81  *                             Available model: HSW ULT only
  82  *                             Scope: Package (physical package)
  83  *      MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  84  *                             perf code: 0x06
  85  *                             Available model: HSW ULT only
  86  *                             Scope: Package (physical package)
  87  *
  88  */
  89
  90 #include <linux/module.h>
  91 #include <linux/slab.h>
  92 #include <linux/perf_event.h>
  93 #include <asm/cpu_device_id.h>
  94 #include <asm/intel-family.h>
  95 #include "../perf_event.h"
  96
  97 MODULE_LICENSE("GPL");
  98
  99 #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format)         \
 100 static ssize_t __cstate_##_var##_show(struct kobject *kobj,     \
 101                                 struct kobj_attribute *attr,    \
 102                                 char *page)                     \
 103 {                                                               \
 104         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);             \
 105         return sprintf(page, _format "\n");                     \
 106 }                                                               \
 107 static struct kobj_attribute format_attr_##_var =               \
 108         __ATTR(_name, 0444, __cstate_##_var##_show, NULL)
 109
 110 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 111                                        struct device_attribute *attr,
 112                                        char *buf);
 113
 114 /* Model -> events mapping */
 115 struct cstate_model {
 116         unsigned long           core_events;
 117         unsigned long           pkg_events;
 118         unsigned long           quirks;
 119 };
 120
 121 /* Quirk flags */
 122 #define SLM_PKG_C6_USE_C7_MSR   (1UL << 0)
 123 #define KNL_CORE_C6_MSR         (1UL << 1)
 124
 125 struct perf_cstate_msr {
 126         u64     msr;
 127         struct  perf_pmu_events_attr *attr;
 128 };
 129
 130
 131 /* cstate_core PMU */
 132 static struct pmu cstate_core_pmu;
 133 static bool has_cstate_core;
 134
 135 enum perf_cstate_core_events {
 136         PERF_CSTATE_CORE_C1_RES = 0,
 137         PERF_CSTATE_CORE_C3_RES,
 138         PERF_CSTATE_CORE_C6_RES,
 139         PERF_CSTATE_CORE_C7_RES,
 140
 141         PERF_CSTATE_CORE_EVENT_MAX,
 142 };
 143
 144 PMU_EVENT_ATTR_STRING(c1-residency, evattr_cstate_core_c1, "event=0x00");
 145 PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_core_c3, "event=0x01");
 146 PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_core_c6, "event=0x02");
 147 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_core_c7, "event=0x03");
 148
 149 static struct perf_cstate_msr core_msr[] = {
 150         [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES,          &evattr_cstate_core_c1 },
 151         [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY,    &evattr_cstate_core_c3 },
 152         [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY,    &evattr_cstate_core_c6 },
 153         [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY,    &evattr_cstate_core_c7 },
 154 };
 155
 156 static struct attribute *core_events_attrs[PERF_CSTATE_CORE_EVENT_MAX + 1] = {
 157         NULL,
 158 };
 159
 160 static struct attribute_group core_events_attr_group = {
 161         .name = "events",
 162         .attrs = core_events_attrs,
 163 };
 164
 165 DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63");
 166 static struct attribute *core_format_attrs[] = {
 167         &format_attr_core_event.attr,
 168         NULL,
 169 };
 170
 171 static struct attribute_group core_format_attr_group = {
 172         .name = "format",
 173         .attrs = core_format_attrs,
 174 };
 175
 176 static cpumask_t cstate_core_cpu_mask;
 177 static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL);
 178
 179 static struct attribute *cstate_cpumask_attrs[] = {
 180         &dev_attr_cpumask.attr,
 181         NULL,
 182 };
 183
 184 static struct attribute_group cpumask_attr_group = {
 185         .attrs = cstate_cpumask_attrs,
 186 };
 187
 188 static const struct attribute_group *core_attr_groups[] = {
 189         &core_events_attr_group,
 190         &core_format_attr_group,
 191         &cpumask_attr_group,
 192         NULL,
 193 };
 194
 195 /* cstate_pkg PMU */
 196 static struct pmu cstate_pkg_pmu;
 197 static bool has_cstate_pkg;
 198
 199 enum perf_cstate_pkg_events {
 200         PERF_CSTATE_PKG_C2_RES = 0,
 201         PERF_CSTATE_PKG_C3_RES,
 202         PERF_CSTATE_PKG_C6_RES,
 203         PERF_CSTATE_PKG_C7_RES,
 204         PERF_CSTATE_PKG_C8_RES,
 205         PERF_CSTATE_PKG_C9_RES,
 206         PERF_CSTATE_PKG_C10_RES,
 207
 208         PERF_CSTATE_PKG_EVENT_MAX,
 209 };
 210
 211 PMU_EVENT_ATTR_STRING(c2-residency, evattr_cstate_pkg_c2, "event=0x00");
 212 PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_pkg_c3, "event=0x01");
 213 PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_pkg_c6, "event=0x02");
 214 PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_pkg_c7, "event=0x03");
 215 PMU_EVENT_ATTR_STRING(c8-residency, evattr_cstate_pkg_c8, "event=0x04");
 216 PMU_EVENT_ATTR_STRING(c9-residency, evattr_cstate_pkg_c9, "event=0x05");
 217 PMU_EVENT_ATTR_STRING(c10-residency, evattr_cstate_pkg_c10, "event=0x06");
 218
 219 static struct perf_cstate_msr pkg_msr[] = {
 220         [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY,      &evattr_cstate_pkg_c2 },
 221         [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY,      &evattr_cstate_pkg_c3 },
 222         [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY,      &evattr_cstate_pkg_c6 },
 223         [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY,      &evattr_cstate_pkg_c7 },
 224         [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY,      &evattr_cstate_pkg_c8 },
 225         [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY,      &evattr_cstate_pkg_c9 },
 226         [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY,    &evattr_cstate_pkg_c10 },
 227 };
 228
 229 static struct attribute *pkg_events_attrs[PERF_CSTATE_PKG_EVENT_MAX + 1] = {
 230         NULL,
 231 };
 232
 233 static struct attribute_group pkg_events_attr_group = {
 234         .name = "events",
 235         .attrs = pkg_events_attrs,
 236 };
 237
 238 DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63");
 239 static struct attribute *pkg_format_attrs[] = {
 240         &format_attr_pkg_event.attr,
 241         NULL,
 242 };
 243 static struct attribute_group pkg_format_attr_group = {
 244         .name = "format",
 245         .attrs = pkg_format_attrs,
 246 };
 247
 248 static cpumask_t cstate_pkg_cpu_mask;
 249
 250 static const struct attribute_group *pkg_attr_groups[] = {
 251         &pkg_events_attr_group,
 252         &pkg_format_attr_group,
 253         &cpumask_attr_group,
 254         NULL,
 255 };
 256
 257 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 258                                        struct device_attribute *attr,
 259                                        char *buf)
 260 {
 261         struct pmu *pmu = dev_get_drvdata(dev);
 262
 263         if (pmu == &cstate_core_pmu)
 264                 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask);
 265         else if (pmu == &cstate_pkg_pmu)
 266                 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask);
 267         else
 268                 return 0;
 269 }
 270
 271 static int cstate_pmu_event_init(struct perf_event *event)
 272 {
 273         u64 cfg = event->attr.config;
 274         int cpu;
 275
 276         if (event->attr.type != event->pmu->type)
 277                 return -ENOENT;
 278
 279         /* unsupported modes and filters */
 280         if (event->attr.exclude_user   ||
 281             event->attr.exclude_kernel ||
 282             event->attr.exclude_hv     ||
 283             event->attr.exclude_idle   ||
 284             event->attr.exclude_host   ||
 285             event->attr.exclude_guest  ||
 286             event->attr.sample_period) /* no sampling */
 287                 return -EINVAL;
 288
 289         if (event->cpu < 0)
 290                 return -EINVAL;
 291
 292         if (event->pmu == &cstate_core_pmu) {
 293                 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX)
 294                         return -EINVAL;
 295                 if (!core_msr[cfg].attr)
 296                         return -EINVAL;
 297                 event->hw.event_base = core_msr[cfg].msr;
 298                 cpu = cpumask_any_and(&cstate_core_cpu_mask,
 299                                       topology_sibling_cpumask(event->cpu));
 300         } else if (event->pmu == &cstate_pkg_pmu) {
 301                 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
 302                         return -EINVAL;
 303                 if (!pkg_msr[cfg].attr)
 304                         return -EINVAL;
 305                 event->hw.event_base = pkg_msr[cfg].msr;
 306                 cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
 307                                       topology_core_cpumask(event->cpu));
 308         } else {
 309                 return -ENOENT;
 310         }
 311
 312         if (cpu >= nr_cpu_ids)
 313                 return -ENODEV;
 314
 315         event->cpu = cpu;
 316         event->hw.config = cfg;
 317         event->hw.idx = -1;
 318         return 0;
 319 }
 320
 321 static inline u64 cstate_pmu_read_counter(struct perf_event *event)
 322 {
 323         u64 val;
 324
 325         rdmsrl(event->hw.event_base, val);
 326         return val;
 327 }
 328
 329 static void cstate_pmu_event_update(struct perf_event *event)
 330 {
 331         struct hw_perf_event *hwc = &event->hw;
 332         u64 prev_raw_count, new_raw_count;
 333
 334 again:
 335         prev_raw_count = local64_read(&hwc->prev_count);
 336         new_raw_count = cstate_pmu_read_counter(event);
 337
 338         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 339                             new_raw_count) != prev_raw_count)
 340                 goto again;
 341
 342         local64_add(new_raw_count - prev_raw_count, &event->count);
 343 }
 344
 345 static void cstate_pmu_event_start(struct perf_event *event, int mode)
 346 {
 347         local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event));
 348 }
 349
 350 static void cstate_pmu_event_stop(struct perf_event *event, int mode)
 351 {
 352         cstate_pmu_event_update(event);
 353 }
 354
 355 static void cstate_pmu_event_del(struct perf_event *event, int mode)
 356 {
 357         cstate_pmu_event_stop(event, PERF_EF_UPDATE);
 358 }
 359
 360 static int cstate_pmu_event_add(struct perf_event *event, int mode)
 361 {
 362         if (mode & PERF_EF_START)
 363                 cstate_pmu_event_start(event, mode);
 364
 365         return 0;
 366 }
 367
 368 /*
 369  * Check if exiting cpu is the designated reader. If so migrate the
 370  * events when there is a valid target available
 371  */
 372 static int cstate_cpu_exit(unsigned int cpu)
 373 {
 374         unsigned int target;
 375
 376         if (has_cstate_core &&
 377             cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) {
 378
 379                 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
 380                 /* Migrate events if there is a valid target */
 381                 if (target < nr_cpu_ids) {
 382                         cpumask_set_cpu(target, &cstate_core_cpu_mask);
 383                         perf_pmu_migrate_context(&cstate_core_pmu, cpu, target);
 384                 }
 385         }
 386
 387         if (has_cstate_pkg &&
 388             cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
 389
 390                 target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
 391                 /* Migrate events if there is a valid target */
 392                 if (target < nr_cpu_ids) {
 393                         cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
 394                         perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target);
 395                 }
 396         }
 397         return 0;
 398 }
 399
 400 static int cstate_cpu_init(unsigned int cpu)
 401 {
 402         unsigned int target;
 403
 404         /*
 405          * If this is the first online thread of that core, set it in
 406          * the core cpu mask as the designated reader.
 407          */
 408         target = cpumask_any_and(&cstate_core_cpu_mask,
 409                                  topology_sibling_cpumask(cpu));
 410
 411         if (has_cstate_core && target >= nr_cpu_ids)
 412                 cpumask_set_cpu(cpu, &cstate_core_cpu_mask);
 413
 414         /*
 415          * If this is the first online thread of that package, set it
 416          * in the package cpu mask as the designated reader.
 417          */
 418         target = cpumask_any_and(&cstate_pkg_cpu_mask,
 419                                  topology_core_cpumask(cpu));
 420         if (has_cstate_pkg && target >= nr_cpu_ids)
 421                 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
 422
 423         return 0;
 424 }
 425
 426 static struct pmu cstate_core_pmu = {
 427         .attr_groups    = core_attr_groups,
 428         .name           = "cstate_core",
 429         .task_ctx_nr    = perf_invalid_context,
 430         .event_init     = cstate_pmu_event_init,
 431         .add            = cstate_pmu_event_add,
 432         .del            = cstate_pmu_event_del,
 433         .start          = cstate_pmu_event_start,
 434         .stop           = cstate_pmu_event_stop,
 435         .read           = cstate_pmu_event_update,
 436         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT,
 437 };
 438
 439 static struct pmu cstate_pkg_pmu = {
 440         .attr_groups    = pkg_attr_groups,
 441         .name           = "cstate_pkg",
 442         .task_ctx_nr    = perf_invalid_context,
 443         .event_init     = cstate_pmu_event_init,
 444         .add            = cstate_pmu_event_add,
 445         .del            = cstate_pmu_event_del,
 446         .start          = cstate_pmu_event_start,
 447         .stop           = cstate_pmu_event_stop,
 448         .read           = cstate_pmu_event_update,
 449         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT,
 450 };
 451
 452 static const struct cstate_model nhm_cstates __initconst = {
 453         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 454                                   BIT(PERF_CSTATE_CORE_C6_RES),
 455
 456         .pkg_events             = BIT(PERF_CSTATE_PKG_C3_RES) |
 457                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 458                                   BIT(PERF_CSTATE_PKG_C7_RES),
 459 };
 460
 461 static const struct cstate_model snb_cstates __initconst = {
 462         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 463                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 464                                   BIT(PERF_CSTATE_CORE_C7_RES),
 465
 466         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 467                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 468                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 469                                   BIT(PERF_CSTATE_PKG_C7_RES),
 470 };
 471
 472 static const struct cstate_model hswult_cstates __initconst = {
 473         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 474                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 475                                   BIT(PERF_CSTATE_CORE_C7_RES),
 476
 477         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 478                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 479                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 480                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 481                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 482                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 483                                   BIT(PERF_CSTATE_PKG_C10_RES),
 484 };
 485
 486 static const struct cstate_model slm_cstates __initconst = {
 487         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 488                                   BIT(PERF_CSTATE_CORE_C6_RES),
 489
 490         .pkg_events             = BIT(PERF_CSTATE_PKG_C6_RES),
 491         .quirks                 = SLM_PKG_C6_USE_C7_MSR,
 492 };
 493
 494
 495 static const struct cstate_model knl_cstates __initconst = {
 496         .core_events            = BIT(PERF_CSTATE_CORE_C6_RES),
 497
 498         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 499                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 500                                   BIT(PERF_CSTATE_PKG_C6_RES),
 501         .quirks                 = KNL_CORE_C6_MSR,
 502 };
 503
 504
 505
 506 #define X86_CSTATES_MODEL(model, states)                                \
 507         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
 508
 509 static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 510         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM,    nhm_cstates),
 511         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates),
 512         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates),
 513
 514         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE,    nhm_cstates),
 515         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates),
 516         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates),
 517
 518         X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE,   snb_cstates),
 519         X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates),
 520
 521         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE,   snb_cstates),
 522         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
 523
 524         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_CORE, snb_cstates),
 525         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X,    snb_cstates),
 526         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),
 527
 528         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),
 529
 530         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT1, slm_cstates),
 531         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT2, slm_cstates),
 532         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT,     slm_cstates),
 533
 534         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE,   snb_cstates),
 535         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
 536         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E,   snb_cstates),
 537         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X,      snb_cstates),
 538
 539         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE,  snb_cstates),
 540         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
 541
 542         X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
 543         { },
 544 };
 545 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
 546
 547 /*
 548  * Probe the cstate events and insert the available one into sysfs attrs
 549  * Return false if there are no available events.
 550  */
 551 static bool __init cstate_probe_msr(const unsigned long evmsk, int max,
 552                                    struct perf_cstate_msr *msr,
 553                                    struct attribute **attrs)
 554 {
 555         bool found = false;
 556         unsigned int bit;
 557         u64 val;
 558
 559         for (bit = 0; bit < max; bit++) {
 560                 if (test_bit(bit, &evmsk) && !rdmsrl_safe(msr[bit].msr, &val)) {
 561                         *attrs++ = &msr[bit].attr->attr.attr;
 562                         found = true;
 563                 } else {
 564                         msr[bit].attr = NULL;
 565                 }
 566         }
 567         *attrs = NULL;
 568
 569         return found;
 570 }
 571
 572 static int __init cstate_probe(const struct cstate_model *cm)
 573 {
 574         /* SLM has different MSR for PKG C6 */
 575         if (cm->quirks & SLM_PKG_C6_USE_C7_MSR)
 576                 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY;
 577
 578         /* KNL has different MSR for CORE C6 */
 579         if (cm->quirks & KNL_CORE_C6_MSR)
 580                 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;
 581
 582
 583         has_cstate_core = cstate_probe_msr(cm->core_events,
 584                                            PERF_CSTATE_CORE_EVENT_MAX,
 585                                            core_msr, core_events_attrs);
 586
 587         has_cstate_pkg = cstate_probe_msr(cm->pkg_events,
 588                                           PERF_CSTATE_PKG_EVENT_MAX,
 589                                           pkg_msr, pkg_events_attrs);
 590
 591         return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV;
 592 }
 593
 594 static inline void cstate_cleanup(void)
 595 {
 596         if (has_cstate_core)
 597                 perf_pmu_unregister(&cstate_core_pmu);
 598
 599         if (has_cstate_pkg)
 600                 perf_pmu_unregister(&cstate_pkg_pmu);
 601 }
 602
 603 static int __init cstate_init(void)
 604 {
 605         int err;
 606
 607         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING,
 608                           "AP_PERF_X86_CSTATE_STARTING", cstate_cpu_init,
 609                           NULL);
 610         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE,
 611                           "AP_PERF_X86_CSTATE_ONLINE", NULL, cstate_cpu_exit);
 612
 613         if (has_cstate_core) {
 614                 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1);
 615                 if (err) {
 616                         has_cstate_core = false;
 617                         pr_info("Failed to register cstate core pmu\n");
 618                         return err;
 619                 }
 620         }
 621
 622         if (has_cstate_pkg) {
 623                 err = perf_pmu_register(&cstate_pkg_pmu, cstate_pkg_pmu.name, -1);
 624                 if (err) {
 625                         has_cstate_pkg = false;
 626                         pr_info("Failed to register cstate pkg pmu\n");
 627                         cstate_cleanup();
 628                         return err;
 629                 }
 630         }
 631
 632         return err;
 633 }
 634
 635 static int __init cstate_pmu_init(void)
 636 {
 637         const struct x86_cpu_id *id;
 638         int err;
 639
 640         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 641                 return -ENODEV;
 642
 643         id = x86_match_cpu(intel_cstates_match);
 644         if (!id)
 645                 return -ENODEV;
 646
 647         err = cstate_probe((const struct cstate_model *) id->driver_data);
 648         if (err)
 649                 return err;
 650
 651         return cstate_init();
 652 }
 653 module_init(cstate_pmu_init);
 654
 655 static void __exit cstate_pmu_exit(void)
 656 {
 657         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE);
 658         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING);
 659         cstate_cleanup();
 660 }
 661 module_exit(cstate_pmu_exit);