1 #ifndef _ASM_X86_SPECIAL_INSNS_H
2 #define _ASM_X86_SPECIAL_INSNS_H
9 static inline void native_clts(void)
15 * Volatile isn't enough to prevent the compiler from reordering the
16 * read/write functions for the control registers and messing everything up.
17 * A memory clobber would solve the problem, but would prevent reordering of
18 * all loads stores around it, which can hurt performance. Solution is to
19 * use a variable and mimic reads and writes to it to enforce serialization
21 extern unsigned long __force_order;
23 static inline unsigned long native_read_cr0(void)
26 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
30 static inline void native_write_cr0(unsigned long val)
32 asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
35 static inline unsigned long native_read_cr2(void)
38 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
42 static inline void native_write_cr2(unsigned long val)
44 asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
47 static inline unsigned long native_read_cr3(void)
50 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
54 static inline void native_write_cr3(unsigned long val)
56 asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
59 static inline unsigned long native_read_cr4(void)
64 * This could fault if CR4 does not exist. Non-existent CR4
65 * is functionally equivalent to CR4 == 0. Keep it simple and pretend
66 * that CR4 == 0 on CPUs that don't have CR4.
68 asm volatile("1: mov %%cr4, %0\n"
71 : "=r" (val), "=m" (__force_order) : "0" (0));
73 /* CR4 always exists on x86_64. */
74 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
79 static inline void native_write_cr4(unsigned long val)
81 asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
85 static inline unsigned long native_read_cr8(void)
88 asm volatile("movq %%cr8,%0" : "=r" (cr8));
92 static inline void native_write_cr8(unsigned long val)
94 asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
98 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
99 static inline u32 __read_pkru(void)
105 * "rdpkru" instruction. Places PKRU contents in to EAX,
106 * clears EDX and requires that ecx=0.
108 asm volatile(".byte 0x0f,0x01,0xee\n\t"
109 : "=a" (pkru), "=d" (edx)
114 static inline void __write_pkru(u32 pkru)
116 u32 ecx = 0, edx = 0;
119 * "wrpkru" instruction. Loads contents in EAX to PKRU,
120 * requires that ecx = edx = 0.
122 asm volatile(".byte 0x0f,0x01,0xef\n\t"
123 : : "a" (pkru), "c"(ecx), "d"(edx));
126 static inline u32 __read_pkru(void)
131 static inline void __write_pkru(u32 pkru)
136 static inline void native_wbinvd(void)
138 asm volatile("wbinvd": : :"memory");
141 extern asmlinkage void native_load_gs_index(unsigned);
143 #ifdef CONFIG_PARAVIRT
144 #include <asm/paravirt.h>
147 static inline unsigned long read_cr0(void)
149 return native_read_cr0();
152 static inline void write_cr0(unsigned long x)
157 static inline unsigned long read_cr2(void)
159 return native_read_cr2();
162 static inline void write_cr2(unsigned long x)
167 static inline unsigned long read_cr3(void)
169 return native_read_cr3();
172 static inline void write_cr3(unsigned long x)
177 static inline unsigned long __read_cr4(void)
179 return native_read_cr4();
182 static inline void __write_cr4(unsigned long x)
187 static inline void wbinvd(void)
194 static inline unsigned long read_cr8(void)
196 return native_read_cr8();
199 static inline void write_cr8(unsigned long x)
204 static inline void load_gs_index(unsigned selector)
206 native_load_gs_index(selector);
211 /* Clear the 'TS' bit */
212 static inline void clts(void)
217 #endif/* CONFIG_PARAVIRT */
219 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
221 static inline void clflush(volatile void *__p)
223 asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
226 static inline void clflushopt(volatile void *__p)
228 alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
229 ".byte 0x66; clflush %P0",
230 X86_FEATURE_CLFLUSHOPT,
231 "+m" (*(volatile char __force *)__p));
234 static inline void clwb(volatile void *__p)
236 volatile struct { char x[64]; } *p = __p;
238 asm volatile(ALTERNATIVE_2(
239 ".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
240 ".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */
241 X86_FEATURE_CLFLUSHOPT,
242 ".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */
248 #define nop() asm volatile ("nop")
251 #endif /* __KERNEL__ */
253 #endif /* _ASM_X86_SPECIAL_INSNS_H */