2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 * A few random additions are:
19 * Copyright (C) 2006 Qumranet
20 * Avi Kivity <avi@qumranet.com>
21 * Yaniv Kamay <yaniv@qumranet.com>
28 #include <linux/types.h>
29 #include <uapi/asm/vmx.h>
32 * Definitions of Primary Processor-Based VM-Execution Controls.
34 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
35 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
36 #define CPU_BASED_HLT_EXITING 0x00000080
37 #define CPU_BASED_INVLPG_EXITING 0x00000200
38 #define CPU_BASED_MWAIT_EXITING 0x00000400
39 #define CPU_BASED_RDPMC_EXITING 0x00000800
40 #define CPU_BASED_RDTSC_EXITING 0x00001000
41 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000
42 #define CPU_BASED_CR3_STORE_EXITING 0x00010000
43 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
44 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
45 #define CPU_BASED_TPR_SHADOW 0x00200000
46 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
47 #define CPU_BASED_MOV_DR_EXITING 0x00800000
48 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
49 #define CPU_BASED_USE_IO_BITMAPS 0x02000000
50 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000
51 #define CPU_BASED_MONITOR_EXITING 0x20000000
52 #define CPU_BASED_PAUSE_EXITING 0x40000000
53 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
55 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
58 * Definitions of Secondary Processor-Based VM-Execution Controls.
60 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
61 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002
62 #define SECONDARY_EXEC_RDTSCP 0x00000008
63 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
64 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
65 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
66 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
67 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
68 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
69 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
70 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
71 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
72 #define SECONDARY_EXEC_XSAVES 0x00100000
75 #define PIN_BASED_EXT_INTR_MASK 0x00000001
76 #define PIN_BASED_NMI_EXITING 0x00000008
77 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
78 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
79 #define PIN_BASED_POSTED_INTR 0x00000080
81 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
83 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
84 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
85 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
86 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
87 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
88 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
89 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
90 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
91 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
92 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
94 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
96 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
97 #define VM_ENTRY_IA32E_MODE 0x00000200
98 #define VM_ENTRY_SMM 0x00000400
99 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
100 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
101 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
102 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
103 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
105 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
107 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
108 #define VMX_MISC_SAVE_EFER_LMA 0x00000020
109 #define VMX_MISC_ACTIVITY_HLT 0x00000040
113 VIRTUAL_PROCESSOR_ID = 0x00000000,
114 POSTED_INTR_NV = 0x00000002,
115 GUEST_ES_SELECTOR = 0x00000800,
116 GUEST_CS_SELECTOR = 0x00000802,
117 GUEST_SS_SELECTOR = 0x00000804,
118 GUEST_DS_SELECTOR = 0x00000806,
119 GUEST_FS_SELECTOR = 0x00000808,
120 GUEST_GS_SELECTOR = 0x0000080a,
121 GUEST_LDTR_SELECTOR = 0x0000080c,
122 GUEST_TR_SELECTOR = 0x0000080e,
123 GUEST_INTR_STATUS = 0x00000810,
124 HOST_ES_SELECTOR = 0x00000c00,
125 HOST_CS_SELECTOR = 0x00000c02,
126 HOST_SS_SELECTOR = 0x00000c04,
127 HOST_DS_SELECTOR = 0x00000c06,
128 HOST_FS_SELECTOR = 0x00000c08,
129 HOST_GS_SELECTOR = 0x00000c0a,
130 HOST_TR_SELECTOR = 0x00000c0c,
131 IO_BITMAP_A = 0x00002000,
132 IO_BITMAP_A_HIGH = 0x00002001,
133 IO_BITMAP_B = 0x00002002,
134 IO_BITMAP_B_HIGH = 0x00002003,
135 MSR_BITMAP = 0x00002004,
136 MSR_BITMAP_HIGH = 0x00002005,
137 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
138 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
139 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
140 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
141 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
142 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
143 TSC_OFFSET = 0x00002010,
144 TSC_OFFSET_HIGH = 0x00002011,
145 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
146 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
147 APIC_ACCESS_ADDR = 0x00002014,
148 APIC_ACCESS_ADDR_HIGH = 0x00002015,
149 POSTED_INTR_DESC_ADDR = 0x00002016,
150 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
151 EPT_POINTER = 0x0000201a,
152 EPT_POINTER_HIGH = 0x0000201b,
153 EOI_EXIT_BITMAP0 = 0x0000201c,
154 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
155 EOI_EXIT_BITMAP1 = 0x0000201e,
156 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
157 EOI_EXIT_BITMAP2 = 0x00002020,
158 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
159 EOI_EXIT_BITMAP3 = 0x00002022,
160 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
161 VMREAD_BITMAP = 0x00002026,
162 VMWRITE_BITMAP = 0x00002028,
163 XSS_EXIT_BITMAP = 0x0000202C,
164 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
165 GUEST_PHYSICAL_ADDRESS = 0x00002400,
166 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
167 VMCS_LINK_POINTER = 0x00002800,
168 VMCS_LINK_POINTER_HIGH = 0x00002801,
169 GUEST_IA32_DEBUGCTL = 0x00002802,
170 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
171 GUEST_IA32_PAT = 0x00002804,
172 GUEST_IA32_PAT_HIGH = 0x00002805,
173 GUEST_IA32_EFER = 0x00002806,
174 GUEST_IA32_EFER_HIGH = 0x00002807,
175 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
176 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
177 GUEST_PDPTR0 = 0x0000280a,
178 GUEST_PDPTR0_HIGH = 0x0000280b,
179 GUEST_PDPTR1 = 0x0000280c,
180 GUEST_PDPTR1_HIGH = 0x0000280d,
181 GUEST_PDPTR2 = 0x0000280e,
182 GUEST_PDPTR2_HIGH = 0x0000280f,
183 GUEST_PDPTR3 = 0x00002810,
184 GUEST_PDPTR3_HIGH = 0x00002811,
185 GUEST_BNDCFGS = 0x00002812,
186 GUEST_BNDCFGS_HIGH = 0x00002813,
187 HOST_IA32_PAT = 0x00002c00,
188 HOST_IA32_PAT_HIGH = 0x00002c01,
189 HOST_IA32_EFER = 0x00002c02,
190 HOST_IA32_EFER_HIGH = 0x00002c03,
191 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
192 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
193 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
194 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
195 EXCEPTION_BITMAP = 0x00004004,
196 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
197 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
198 CR3_TARGET_COUNT = 0x0000400a,
199 VM_EXIT_CONTROLS = 0x0000400c,
200 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
201 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
202 VM_ENTRY_CONTROLS = 0x00004012,
203 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
204 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
205 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
206 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
207 TPR_THRESHOLD = 0x0000401c,
208 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
209 PLE_GAP = 0x00004020,
210 PLE_WINDOW = 0x00004022,
211 VM_INSTRUCTION_ERROR = 0x00004400,
212 VM_EXIT_REASON = 0x00004402,
213 VM_EXIT_INTR_INFO = 0x00004404,
214 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
215 IDT_VECTORING_INFO_FIELD = 0x00004408,
216 IDT_VECTORING_ERROR_CODE = 0x0000440a,
217 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
218 VMX_INSTRUCTION_INFO = 0x0000440e,
219 GUEST_ES_LIMIT = 0x00004800,
220 GUEST_CS_LIMIT = 0x00004802,
221 GUEST_SS_LIMIT = 0x00004804,
222 GUEST_DS_LIMIT = 0x00004806,
223 GUEST_FS_LIMIT = 0x00004808,
224 GUEST_GS_LIMIT = 0x0000480a,
225 GUEST_LDTR_LIMIT = 0x0000480c,
226 GUEST_TR_LIMIT = 0x0000480e,
227 GUEST_GDTR_LIMIT = 0x00004810,
228 GUEST_IDTR_LIMIT = 0x00004812,
229 GUEST_ES_AR_BYTES = 0x00004814,
230 GUEST_CS_AR_BYTES = 0x00004816,
231 GUEST_SS_AR_BYTES = 0x00004818,
232 GUEST_DS_AR_BYTES = 0x0000481a,
233 GUEST_FS_AR_BYTES = 0x0000481c,
234 GUEST_GS_AR_BYTES = 0x0000481e,
235 GUEST_LDTR_AR_BYTES = 0x00004820,
236 GUEST_TR_AR_BYTES = 0x00004822,
237 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
238 GUEST_ACTIVITY_STATE = 0X00004826,
239 GUEST_SYSENTER_CS = 0x0000482A,
240 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
241 HOST_IA32_SYSENTER_CS = 0x00004c00,
242 CR0_GUEST_HOST_MASK = 0x00006000,
243 CR4_GUEST_HOST_MASK = 0x00006002,
244 CR0_READ_SHADOW = 0x00006004,
245 CR4_READ_SHADOW = 0x00006006,
246 CR3_TARGET_VALUE0 = 0x00006008,
247 CR3_TARGET_VALUE1 = 0x0000600a,
248 CR3_TARGET_VALUE2 = 0x0000600c,
249 CR3_TARGET_VALUE3 = 0x0000600e,
250 EXIT_QUALIFICATION = 0x00006400,
251 GUEST_LINEAR_ADDRESS = 0x0000640a,
252 GUEST_CR0 = 0x00006800,
253 GUEST_CR3 = 0x00006802,
254 GUEST_CR4 = 0x00006804,
255 GUEST_ES_BASE = 0x00006806,
256 GUEST_CS_BASE = 0x00006808,
257 GUEST_SS_BASE = 0x0000680a,
258 GUEST_DS_BASE = 0x0000680c,
259 GUEST_FS_BASE = 0x0000680e,
260 GUEST_GS_BASE = 0x00006810,
261 GUEST_LDTR_BASE = 0x00006812,
262 GUEST_TR_BASE = 0x00006814,
263 GUEST_GDTR_BASE = 0x00006816,
264 GUEST_IDTR_BASE = 0x00006818,
265 GUEST_DR7 = 0x0000681a,
266 GUEST_RSP = 0x0000681c,
267 GUEST_RIP = 0x0000681e,
268 GUEST_RFLAGS = 0x00006820,
269 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
270 GUEST_SYSENTER_ESP = 0x00006824,
271 GUEST_SYSENTER_EIP = 0x00006826,
272 HOST_CR0 = 0x00006c00,
273 HOST_CR3 = 0x00006c02,
274 HOST_CR4 = 0x00006c04,
275 HOST_FS_BASE = 0x00006c06,
276 HOST_GS_BASE = 0x00006c08,
277 HOST_TR_BASE = 0x00006c0a,
278 HOST_GDTR_BASE = 0x00006c0c,
279 HOST_IDTR_BASE = 0x00006c0e,
280 HOST_IA32_SYSENTER_ESP = 0x00006c10,
281 HOST_IA32_SYSENTER_EIP = 0x00006c12,
282 HOST_RSP = 0x00006c14,
283 HOST_RIP = 0x00006c16,
287 * Interruption-information format
289 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
290 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
291 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
292 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
293 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
294 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
296 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
297 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
298 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
299 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
301 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
302 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
303 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
304 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
305 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
307 /* GUEST_INTERRUPTIBILITY_INFO flags. */
308 #define GUEST_INTR_STATE_STI 0x00000001
309 #define GUEST_INTR_STATE_MOV_SS 0x00000002
310 #define GUEST_INTR_STATE_SMI 0x00000004
311 #define GUEST_INTR_STATE_NMI 0x00000008
313 /* GUEST_ACTIVITY_STATE flags */
314 #define GUEST_ACTIVITY_ACTIVE 0
315 #define GUEST_ACTIVITY_HLT 1
316 #define GUEST_ACTIVITY_SHUTDOWN 2
317 #define GUEST_ACTIVITY_WAIT_SIPI 3
320 * Exit Qualifications for MOV for Control Register Access
322 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
323 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
324 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
325 #define LMSW_SOURCE_DATA_SHIFT 16
326 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
327 #define REG_EAX (0 << 8)
328 #define REG_ECX (1 << 8)
329 #define REG_EDX (2 << 8)
330 #define REG_EBX (3 << 8)
331 #define REG_ESP (4 << 8)
332 #define REG_EBP (5 << 8)
333 #define REG_ESI (6 << 8)
334 #define REG_EDI (7 << 8)
335 #define REG_R8 (8 << 8)
336 #define REG_R9 (9 << 8)
337 #define REG_R10 (10 << 8)
338 #define REG_R11 (11 << 8)
339 #define REG_R12 (12 << 8)
340 #define REG_R13 (13 << 8)
341 #define REG_R14 (14 << 8)
342 #define REG_R15 (15 << 8)
345 * Exit Qualifications for MOV for Debug Register Access
347 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
348 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
349 #define TYPE_MOV_TO_DR (0 << 4)
350 #define TYPE_MOV_FROM_DR (1 << 4)
351 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
355 * Exit Qualifications for APIC-Access
357 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
358 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
359 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
360 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
361 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
362 #define TYPE_LINEAR_APIC_EVENT (3 << 12)
363 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
364 #define TYPE_PHYSICAL_APIC_INST (15 << 12)
367 #define SEGMENT_AR_L_MASK (1 << 13)
369 #define AR_TYPE_ACCESSES_MASK 1
370 #define AR_TYPE_READABLE_MASK (1 << 1)
371 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
372 #define AR_TYPE_CODE_MASK (1 << 3)
373 #define AR_TYPE_MASK 0x0f
374 #define AR_TYPE_BUSY_64_TSS 11
375 #define AR_TYPE_BUSY_32_TSS 11
376 #define AR_TYPE_BUSY_16_TSS 3
377 #define AR_TYPE_LDT 2
379 #define AR_UNUSABLE_MASK (1 << 16)
380 #define AR_S_MASK (1 << 4)
381 #define AR_P_MASK (1 << 7)
382 #define AR_L_MASK (1 << 13)
383 #define AR_DB_MASK (1 << 14)
384 #define AR_G_MASK (1 << 15)
385 #define AR_DPL_SHIFT 5
386 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
388 #define AR_RESERVD_MASK 0xfffe0f00
390 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
391 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
392 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
394 #define VMX_NR_VPIDS (1 << 16)
395 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
396 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
398 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
399 #define VMX_EPT_EXTENT_CONTEXT 1
400 #define VMX_EPT_EXTENT_GLOBAL 2
401 #define VMX_EPT_EXTENT_SHIFT 24
403 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
404 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
405 #define VMX_EPTP_UC_BIT (1ull << 8)
406 #define VMX_EPTP_WB_BIT (1ull << 14)
407 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
408 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
409 #define VMX_EPT_INVEPT_BIT (1ull << 20)
410 #define VMX_EPT_AD_BIT (1ull << 21)
411 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
412 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
414 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
415 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
417 #define VMX_EPT_DEFAULT_GAW 3
418 #define VMX_EPT_MAX_GAW 0x4
419 #define VMX_EPT_MT_EPTE_SHIFT 3
420 #define VMX_EPT_GAW_EPTP_SHIFT 3
421 #define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
422 #define VMX_EPT_DEFAULT_MT 0x6ull
423 #define VMX_EPT_READABLE_MASK 0x1ull
424 #define VMX_EPT_WRITABLE_MASK 0x2ull
425 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
426 #define VMX_EPT_IPAT_BIT (1ull << 6)
427 #define VMX_EPT_ACCESS_BIT (1ull << 8)
428 #define VMX_EPT_DIRTY_BIT (1ull << 9)
430 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
433 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
434 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
435 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
436 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
437 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
438 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
439 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
440 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
441 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
442 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
443 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
445 struct vmx_msr_entry {
452 * Exit Qualifications for entry failure during or after loading guest state
454 #define ENTRY_FAIL_DEFAULT 0
455 #define ENTRY_FAIL_PDPTE 2
456 #define ENTRY_FAIL_NMI 3
457 #define ENTRY_FAIL_VMCS_LINK_PTR 4
460 * VM-instruction error numbers
462 enum vm_instruction_error_number {
463 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
464 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
465 VMXERR_VMCLEAR_VMXON_POINTER = 3,
466 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
467 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
468 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
469 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
470 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
471 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
472 VMXERR_VMPTRLD_VMXON_POINTER = 10,
473 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
474 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
475 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
476 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
477 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
478 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
479 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
480 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
481 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
482 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
483 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
484 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
485 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
486 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
487 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,