2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
40 #include <linux/slab.h>
41 #include <linux/bootmem.h>
42 #include <linux/dmar.h>
43 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
60 #include <asm/hw_irq.h>
64 #define for_each_ioapic(idx) \
65 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
66 #define for_each_ioapic_reverse(idx) \
67 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
68 #define for_each_pin(idx, pin) \
69 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
70 #define for_each_ioapic_pin(idx, pin) \
71 for_each_ioapic((idx)) \
72 for_each_pin((idx), (pin))
74 #define for_each_irq_pin(entry, head) \
75 list_for_each_entry(entry, &head, list)
78 * Is the SiS APIC rmw bug present ?
79 * -1 = don't know, 0 = no, 1 = yes
81 int sis_apic_bug = -1;
83 static DEFINE_RAW_SPINLOCK(ioapic_lock);
84 static DEFINE_MUTEX(ioapic_mutex);
85 static unsigned int ioapic_dynirq_base;
86 static int ioapic_initialized;
96 static struct ioapic {
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry *saved_registers;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config;
109 struct ioapic_domain_cfg irqdomain_cfg;
110 struct irq_domain *irqdomain;
111 struct mp_pin_info *pin_info;
112 struct resource *iomem_res;
113 } ioapics[MAX_IO_APICS];
115 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
117 int mpc_ioapic_id(int ioapic_idx)
119 return ioapics[ioapic_idx].mp_config.apicid;
122 unsigned int mpc_ioapic_addr(int ioapic_idx)
124 return ioapics[ioapic_idx].mp_config.apicaddr;
127 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
129 return &ioapics[ioapic_idx].gsi_config;
132 static inline int mp_ioapic_pin_count(int ioapic)
134 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
136 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
139 u32 mp_pin_to_gsi(int ioapic, int pin)
141 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
145 * Initialize all legacy IRQs and all pins on the first IOAPIC
146 * if we have legacy interrupt controller. Kernel boot option "pirq="
147 * may rely on non-legacy pins on the first IOAPIC.
149 static inline int mp_init_irq_at_boot(int ioapic, int irq)
151 if (!nr_legacy_irqs())
154 return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
157 static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
159 return ioapics[ioapic_idx].pin_info + pin;
162 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
164 return ioapics[ioapic].irqdomain;
169 /* The one past the highest gsi number used */
172 /* MP IRQ source entries */
173 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
175 /* # of MP IRQ source entries */
179 int mp_bus_id_to_type[MAX_MP_BUSSES];
182 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
184 int skip_ioapic_setup;
187 * disable_ioapic_support() - disables ioapic support at runtime
189 void disable_ioapic_support(void)
193 noioapicreroute = -1;
195 skip_ioapic_setup = 1;
198 static int __init parse_noapic(char *str)
200 /* disable IO-APIC */
201 disable_ioapic_support();
204 early_param("noapic", parse_noapic);
206 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
207 void mp_save_irq(struct mpc_intsrc *m)
211 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
212 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
213 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
214 m->srcbusirq, m->dstapic, m->dstirq);
216 for (i = 0; i < mp_irq_entries; i++) {
217 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
221 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
222 if (++mp_irq_entries == MAX_IRQ_SOURCES)
223 panic("Max # of irq sources exceeded!!\n");
226 struct irq_pin_list {
227 struct list_head list;
231 static struct irq_pin_list *alloc_irq_pin_list(int node)
233 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
236 static void alloc_ioapic_saved_registers(int idx)
240 if (ioapics[idx].saved_registers)
243 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
244 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
245 if (!ioapics[idx].saved_registers)
246 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
249 static void free_ioapic_saved_registers(int idx)
251 kfree(ioapics[idx].saved_registers);
252 ioapics[idx].saved_registers = NULL;
255 int __init arch_early_irq_init(void)
258 int i, node = cpu_to_node(0);
260 if (!nr_legacy_irqs())
264 alloc_ioapic_saved_registers(i);
267 * For legacy IRQ's, start with assigning irq0 to irq15 to
268 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
270 for (i = 0; i < nr_legacy_irqs(); i++) {
271 cfg = alloc_irq_and_cfg_at(i, node);
272 cfg->vector = IRQ0_VECTOR + i;
273 cpumask_setall(cfg->domain);
281 unsigned int unused[3];
283 unsigned int unused2[11];
287 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
289 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
290 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
293 void io_apic_eoi(unsigned int apic, unsigned int vector)
295 struct io_apic __iomem *io_apic = io_apic_base(apic);
296 writel(vector, &io_apic->eoi);
299 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
301 struct io_apic __iomem *io_apic = io_apic_base(apic);
302 writel(reg, &io_apic->index);
303 return readl(&io_apic->data);
306 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
308 struct io_apic __iomem *io_apic = io_apic_base(apic);
310 writel(reg, &io_apic->index);
311 writel(value, &io_apic->data);
315 * Re-write a value: to be used for read-modify-write
316 * cycles where the read already set up the index register.
318 * Older SiS APIC requires we rewrite the index register
320 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
322 struct io_apic __iomem *io_apic = io_apic_base(apic);
325 writel(reg, &io_apic->index);
326 writel(value, &io_apic->data);
330 struct { u32 w1, w2; };
331 struct IO_APIC_route_entry entry;
334 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
336 union entry_union eu;
338 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
339 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
344 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
346 union entry_union eu;
349 raw_spin_lock_irqsave(&ioapic_lock, flags);
350 eu.entry = __ioapic_read_entry(apic, pin);
351 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
357 * When we write a new IO APIC routing entry, we need to write the high
358 * word first! If the mask bit in the low word is clear, we will enable
359 * the interrupt, and we need to make sure the entry is fully populated
360 * before that happens.
362 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
364 union entry_union eu = {{0, 0}};
367 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
368 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
371 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
375 raw_spin_lock_irqsave(&ioapic_lock, flags);
376 __ioapic_write_entry(apic, pin, e);
377 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
381 * When we mask an IO APIC routing entry, we need to write the low
382 * word first, in order to set the mask bit before we change the
385 static void ioapic_mask_entry(int apic, int pin)
388 union entry_union eu = { .entry.mask = 1 };
390 raw_spin_lock_irqsave(&ioapic_lock, flags);
391 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
392 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
393 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
397 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
398 * shared ISA-space IRQs, so we have to support them. We are super
399 * fast in the common case, and fast for shared ISA-space IRQs.
401 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
403 struct irq_pin_list *entry;
405 /* don't allow duplicates */
406 for_each_irq_pin(entry, cfg->irq_2_pin)
407 if (entry->apic == apic && entry->pin == pin)
410 entry = alloc_irq_pin_list(node);
412 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
419 list_add_tail(&entry->list, &cfg->irq_2_pin);
423 static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
425 struct irq_pin_list *tmp, *entry;
427 list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list)
428 if (entry->apic == apic && entry->pin == pin) {
429 list_del(&entry->list);
435 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
437 if (__add_pin_to_irq_node(cfg, node, apic, pin))
438 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
442 * Reroute an IRQ to a different pin.
444 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
445 int oldapic, int oldpin,
446 int newapic, int newpin)
448 struct irq_pin_list *entry;
450 for_each_irq_pin(entry, cfg->irq_2_pin) {
451 if (entry->apic == oldapic && entry->pin == oldpin) {
452 entry->apic = newapic;
454 /* every one is different, right? */
459 /* old apic/pin didn't exist, so just add new ones */
460 add_pin_to_irq_node(cfg, node, newapic, newpin);
463 static void __io_apic_modify_irq(struct irq_pin_list *entry,
464 int mask_and, int mask_or,
465 void (*final)(struct irq_pin_list *entry))
467 unsigned int reg, pin;
470 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
473 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
478 static void io_apic_modify_irq(struct irq_cfg *cfg,
479 int mask_and, int mask_or,
480 void (*final)(struct irq_pin_list *entry))
482 struct irq_pin_list *entry;
484 for_each_irq_pin(entry, cfg->irq_2_pin)
485 __io_apic_modify_irq(entry, mask_and, mask_or, final);
488 static void io_apic_sync(struct irq_pin_list *entry)
491 * Synchronize the IO-APIC and the CPU by doing
492 * a dummy read from the IO-APIC
494 struct io_apic __iomem *io_apic;
496 io_apic = io_apic_base(entry->apic);
497 readl(&io_apic->data);
500 static void mask_ioapic(struct irq_cfg *cfg)
504 raw_spin_lock_irqsave(&ioapic_lock, flags);
505 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
506 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
509 static void mask_ioapic_irq(struct irq_data *data)
511 mask_ioapic(data->chip_data);
514 static void __unmask_ioapic(struct irq_cfg *cfg)
516 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
519 static void unmask_ioapic(struct irq_cfg *cfg)
523 raw_spin_lock_irqsave(&ioapic_lock, flags);
524 __unmask_ioapic(cfg);
525 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
528 static void unmask_ioapic_irq(struct irq_data *data)
530 unmask_ioapic(data->chip_data);
534 * IO-APIC versions below 0x20 don't support EOI register.
535 * For the record, here is the information about various versions:
537 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
538 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
541 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
542 * version as 0x2. This is an error with documentation and these ICH chips
543 * use io-apic's of version 0x20.
545 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
546 * Otherwise, we simulate the EOI message manually by changing the trigger
547 * mode to edge and then back to level, with RTE being masked during this.
549 void native_eoi_ioapic_pin(int apic, int pin, int vector)
551 if (mpc_ioapic_ver(apic) >= 0x20) {
552 io_apic_eoi(apic, vector);
554 struct IO_APIC_route_entry entry, entry1;
556 entry = entry1 = __ioapic_read_entry(apic, pin);
559 * Mask the entry and change the trigger mode to edge.
562 entry1.trigger = IOAPIC_EDGE;
564 __ioapic_write_entry(apic, pin, entry1);
567 * Restore the previous level triggered entry.
569 __ioapic_write_entry(apic, pin, entry);
573 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
575 struct irq_pin_list *entry;
578 raw_spin_lock_irqsave(&ioapic_lock, flags);
579 for_each_irq_pin(entry, cfg->irq_2_pin)
580 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
582 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
585 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
587 struct IO_APIC_route_entry entry;
589 /* Check delivery_mode to be sure we're not clearing an SMI pin */
590 entry = ioapic_read_entry(apic, pin);
591 if (entry.delivery_mode == dest_SMI)
595 * Make sure the entry is masked and re-read the contents to check
596 * if it is a level triggered pin and if the remote-IRR is set.
600 ioapic_write_entry(apic, pin, entry);
601 entry = ioapic_read_entry(apic, pin);
608 * Make sure the trigger mode is set to level. Explicit EOI
609 * doesn't clear the remote-IRR if the trigger mode is not
612 if (!entry.trigger) {
613 entry.trigger = IOAPIC_LEVEL;
614 ioapic_write_entry(apic, pin, entry);
617 raw_spin_lock_irqsave(&ioapic_lock, flags);
618 x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
619 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
623 * Clear the rest of the bits in the IO-APIC RTE except for the mask
626 ioapic_mask_entry(apic, pin);
627 entry = ioapic_read_entry(apic, pin);
629 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
630 mpc_ioapic_id(apic), pin);
633 static void clear_IO_APIC (void)
637 for_each_ioapic_pin(apic, pin)
638 clear_IO_APIC_pin(apic, pin);
643 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
644 * specific CPU-side IRQs.
648 static int pirq_entries[MAX_PIRQS] = {
649 [0 ... MAX_PIRQS - 1] = -1
652 static int __init ioapic_pirq_setup(char *str)
655 int ints[MAX_PIRQS+1];
657 get_options(str, ARRAY_SIZE(ints), ints);
659 apic_printk(APIC_VERBOSE, KERN_INFO
660 "PIRQ redirection, working around broken MP-BIOS.\n");
662 if (ints[0] < MAX_PIRQS)
665 for (i = 0; i < max; i++) {
666 apic_printk(APIC_VERBOSE, KERN_DEBUG
667 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
669 * PIRQs are mapped upside down, usually.
671 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
676 __setup("pirq=", ioapic_pirq_setup);
677 #endif /* CONFIG_X86_32 */
680 * Saves all the IO-APIC RTE's
682 int save_ioapic_entries(void)
687 for_each_ioapic(apic) {
688 if (!ioapics[apic].saved_registers) {
693 for_each_pin(apic, pin)
694 ioapics[apic].saved_registers[pin] =
695 ioapic_read_entry(apic, pin);
702 * Mask all IO APIC entries.
704 void mask_ioapic_entries(void)
708 for_each_ioapic(apic) {
709 if (!ioapics[apic].saved_registers)
712 for_each_pin(apic, pin) {
713 struct IO_APIC_route_entry entry;
715 entry = ioapics[apic].saved_registers[pin];
718 ioapic_write_entry(apic, pin, entry);
725 * Restore IO APIC entries which was saved in the ioapic structure.
727 int restore_ioapic_entries(void)
731 for_each_ioapic(apic) {
732 if (!ioapics[apic].saved_registers)
735 for_each_pin(apic, pin)
736 ioapic_write_entry(apic, pin,
737 ioapics[apic].saved_registers[pin]);
743 * Find the IRQ entry number of a certain pin.
745 static int find_irq_entry(int ioapic_idx, int pin, int type)
749 for (i = 0; i < mp_irq_entries; i++)
750 if (mp_irqs[i].irqtype == type &&
751 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
752 mp_irqs[i].dstapic == MP_APIC_ALL) &&
753 mp_irqs[i].dstirq == pin)
760 * Find the pin to which IRQ[irq] (ISA) is connected
762 static int __init find_isa_irq_pin(int irq, int type)
766 for (i = 0; i < mp_irq_entries; i++) {
767 int lbus = mp_irqs[i].srcbus;
769 if (test_bit(lbus, mp_bus_not_pci) &&
770 (mp_irqs[i].irqtype == type) &&
771 (mp_irqs[i].srcbusirq == irq))
773 return mp_irqs[i].dstirq;
778 static int __init find_isa_irq_apic(int irq, int type)
782 for (i = 0; i < mp_irq_entries; i++) {
783 int lbus = mp_irqs[i].srcbus;
785 if (test_bit(lbus, mp_bus_not_pci) &&
786 (mp_irqs[i].irqtype == type) &&
787 (mp_irqs[i].srcbusirq == irq))
791 if (i < mp_irq_entries) {
794 for_each_ioapic(ioapic_idx)
795 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
804 * EISA Edge/Level control register, ELCR
806 static int EISA_ELCR(unsigned int irq)
808 if (irq < nr_legacy_irqs()) {
809 unsigned int port = 0x4d0 + (irq >> 3);
810 return (inb(port) >> (irq & 7)) & 1;
812 apic_printk(APIC_VERBOSE, KERN_INFO
813 "Broken MPtable reports ISA irq %d\n", irq);
819 /* ISA interrupts are always polarity zero edge triggered,
820 * when listed as conforming in the MP table. */
822 #define default_ISA_trigger(idx) (0)
823 #define default_ISA_polarity(idx) (0)
825 /* EISA interrupts are always polarity zero and can be edge or level
826 * trigger depending on the ELCR value. If an interrupt is listed as
827 * EISA conforming in the MP table, that means its trigger type must
828 * be read in from the ELCR */
830 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
831 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
833 /* PCI interrupts are always polarity one level triggered,
834 * when listed as conforming in the MP table. */
836 #define default_PCI_trigger(idx) (1)
837 #define default_PCI_polarity(idx) (1)
839 static int irq_polarity(int idx)
841 int bus = mp_irqs[idx].srcbus;
845 * Determine IRQ line polarity (high active or low active):
847 switch (mp_irqs[idx].irqflag & 3)
849 case 0: /* conforms, ie. bus-type dependent polarity */
850 if (test_bit(bus, mp_bus_not_pci))
851 polarity = default_ISA_polarity(idx);
853 polarity = default_PCI_polarity(idx);
855 case 1: /* high active */
860 case 2: /* reserved */
862 pr_warn("broken BIOS!!\n");
866 case 3: /* low active */
871 default: /* invalid */
873 pr_warn("broken BIOS!!\n");
881 static int irq_trigger(int idx)
883 int bus = mp_irqs[idx].srcbus;
887 * Determine IRQ trigger mode (edge or level sensitive):
889 switch ((mp_irqs[idx].irqflag>>2) & 3)
891 case 0: /* conforms, ie. bus-type dependent */
892 if (test_bit(bus, mp_bus_not_pci))
893 trigger = default_ISA_trigger(idx);
895 trigger = default_PCI_trigger(idx);
897 switch (mp_bus_id_to_type[bus]) {
898 case MP_BUS_ISA: /* ISA pin */
900 /* set before the switch */
903 case MP_BUS_EISA: /* EISA pin */
905 trigger = default_EISA_trigger(idx);
908 case MP_BUS_PCI: /* PCI pin */
910 /* set before the switch */
915 pr_warn("broken BIOS!!\n");
927 case 2: /* reserved */
929 pr_warn("broken BIOS!!\n");
938 default: /* invalid */
940 pr_warn("broken BIOS!!\n");
948 static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin)
951 int ioapic = (int)(long)domain->host_data;
952 int type = ioapics[ioapic].irqdomain_cfg.type;
955 case IOAPIC_DOMAIN_LEGACY:
957 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
958 * GSIs on some weird platforms.
960 if (gsi < nr_legacy_irqs())
961 irq = irq_create_mapping(domain, pin);
962 else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
965 case IOAPIC_DOMAIN_STRICT:
966 if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
969 case IOAPIC_DOMAIN_DYNAMIC:
970 irq = irq_create_mapping(domain, pin);
973 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
977 return irq > 0 ? irq : -1;
980 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
984 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
985 struct mp_pin_info *info = mp_pin_info(ioapic, pin);
990 mutex_lock(&ioapic_mutex);
993 * Don't use irqdomain to manage ISA IRQs because there may be
994 * multiple IOAPIC pins sharing the same ISA IRQ number and
995 * irqdomain only supports 1:1 mapping between IOAPIC pin and
996 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
997 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
998 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
999 * available, and some BIOSes may use MP Interrupt Source records
1000 * to override IRQ numbers for PIRQs instead of reprogramming
1001 * the interrupt routing logic. Thus there may be multiple pins
1002 * sharing the same legacy IRQ number when ACPI is disabled.
1004 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1005 irq = mp_irqs[idx].srcbusirq;
1006 if (flags & IOAPIC_MAP_ALLOC) {
1007 if (info->count == 0 &&
1008 mp_irqdomain_map(domain, irq, pin) != 0)
1011 /* special handling for timer IRQ0 */
1016 irq = irq_find_mapping(domain, pin);
1017 if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
1018 irq = alloc_irq_from_domain(domain, gsi, pin);
1021 if (flags & IOAPIC_MAP_ALLOC) {
1022 /* special handling for legacy IRQs */
1023 if (irq < nr_legacy_irqs() && info->count == 1 &&
1024 mp_irqdomain_map(domain, irq, pin) != 0)
1029 else if (info->count == 0)
1033 mutex_unlock(&ioapic_mutex);
1035 return irq > 0 ? irq : -1;
1038 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1040 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1043 * Debugging check, we are in big trouble if this message pops up!
1045 if (mp_irqs[idx].dstirq != pin)
1046 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1048 #ifdef CONFIG_X86_32
1050 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1052 if ((pin >= 16) && (pin <= 23)) {
1053 if (pirq_entries[pin-16] != -1) {
1054 if (!pirq_entries[pin-16]) {
1055 apic_printk(APIC_VERBOSE, KERN_DEBUG
1056 "disabling PIRQ%d\n", pin-16);
1058 int irq = pirq_entries[pin-16];
1059 apic_printk(APIC_VERBOSE, KERN_DEBUG
1060 "using PIRQ%d -> IRQ %d\n",
1068 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1071 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags)
1073 int ioapic, pin, idx;
1075 ioapic = mp_find_ioapic(gsi);
1079 pin = mp_find_ioapic_pin(ioapic, gsi);
1080 idx = find_irq_entry(ioapic, pin, mp_INT);
1081 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1084 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1087 void mp_unmap_irq(int irq)
1089 struct irq_data *data = irq_get_irq_data(irq);
1090 struct mp_pin_info *info;
1093 if (!data || !data->domain)
1096 ioapic = (int)(long)data->domain->host_data;
1097 pin = (int)data->hwirq;
1098 info = mp_pin_info(ioapic, pin);
1100 mutex_lock(&ioapic_mutex);
1101 if (--info->count == 0) {
1103 if (irq < nr_legacy_irqs() &&
1104 ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY)
1105 mp_irqdomain_unmap(data->domain, irq);
1107 irq_dispose_mapping(irq);
1109 mutex_unlock(&ioapic_mutex);
1113 * Find a specific PCI IRQ entry.
1114 * Not an __init, possibly needed by modules
1116 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1118 int irq, i, best_ioapic = -1, best_idx = -1;
1120 apic_printk(APIC_DEBUG,
1121 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1123 if (test_bit(bus, mp_bus_not_pci)) {
1124 apic_printk(APIC_VERBOSE,
1125 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1129 for (i = 0; i < mp_irq_entries; i++) {
1130 int lbus = mp_irqs[i].srcbus;
1131 int ioapic_idx, found = 0;
1133 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1134 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1137 for_each_ioapic(ioapic_idx)
1138 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1139 mp_irqs[i].dstapic == MP_APIC_ALL) {
1147 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1148 if (irq > 0 && !IO_APIC_IRQ(irq))
1151 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1153 best_ioapic = ioapic_idx;
1158 * Use the first all-but-pin matching entry as a
1159 * best-guess fuzzy result for broken mptables.
1163 best_ioapic = ioapic_idx;
1170 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1173 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1175 static struct irq_chip ioapic_chip;
1177 #ifdef CONFIG_X86_32
1178 static inline int IO_APIC_irq_trigger(int irq)
1182 for_each_ioapic_pin(apic, pin) {
1183 idx = find_irq_entry(apic, pin, mp_INT);
1184 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1185 return irq_trigger(idx);
1188 * nonexistent IRQs are edge default
1193 static inline int IO_APIC_irq_trigger(int irq)
1199 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1200 unsigned long trigger)
1202 struct irq_chip *chip = &ioapic_chip;
1203 irq_flow_handler_t hdl;
1206 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1207 trigger == IOAPIC_LEVEL) {
1208 irq_set_status_flags(irq, IRQ_LEVEL);
1211 irq_clear_status_flags(irq, IRQ_LEVEL);
1215 if (setup_remapped_irq(irq, cfg, chip))
1216 fasteoi = trigger != 0;
1218 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1219 irq_set_chip_and_handler_name(irq, chip, hdl,
1220 fasteoi ? "fasteoi" : "edge");
1223 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1224 unsigned int destination, int vector,
1225 struct io_apic_irq_attr *attr)
1227 memset(entry, 0, sizeof(*entry));
1229 entry->delivery_mode = apic->irq_delivery_mode;
1230 entry->dest_mode = apic->irq_dest_mode;
1231 entry->dest = destination;
1232 entry->vector = vector;
1233 entry->mask = 0; /* enable IRQ */
1234 entry->trigger = attr->trigger;
1235 entry->polarity = attr->polarity;
1238 * Mask level triggered irqs.
1239 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1247 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1248 struct io_apic_irq_attr *attr)
1250 struct IO_APIC_route_entry entry;
1253 if (!IO_APIC_IRQ(irq))
1256 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1259 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1261 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1262 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1263 clear_irq_vector(irq, cfg);
1268 apic_printk(APIC_VERBOSE,KERN_DEBUG
1269 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1270 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1271 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1272 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1274 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1275 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1276 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1277 clear_irq_vector(irq, cfg);
1282 ioapic_register_intr(irq, cfg, attr->trigger);
1283 if (irq < nr_legacy_irqs())
1284 legacy_pic->mask(irq);
1286 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1289 static void __init setup_IO_APIC_irqs(void)
1291 unsigned int ioapic, pin;
1294 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1296 for_each_ioapic_pin(ioapic, pin) {
1297 idx = find_irq_entry(ioapic, pin, mp_INT);
1299 apic_printk(APIC_VERBOSE,
1300 KERN_DEBUG " apic %d pin %d not connected\n",
1301 mpc_ioapic_id(ioapic), pin);
1303 pin_2_irq(idx, ioapic, pin,
1304 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1309 * Set up the timer pin, possibly with the 8259A-master behind.
1311 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1312 unsigned int pin, int vector)
1314 struct IO_APIC_route_entry entry;
1317 memset(&entry, 0, sizeof(entry));
1320 * We use logical delivery to get the timer IRQ
1323 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1324 apic->target_cpus(), &dest)))
1327 entry.dest_mode = apic->irq_dest_mode;
1328 entry.mask = 0; /* don't mask IRQ for edge */
1330 entry.delivery_mode = apic->irq_delivery_mode;
1333 entry.vector = vector;
1336 * The timer IRQ doesn't have to know that behind the
1337 * scene we may have a 8259A-master in AEOI mode ...
1339 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1343 * Add it to the IO-APIC irq-routing table:
1345 ioapic_write_entry(ioapic_idx, pin, entry);
1348 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1352 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1354 for (i = 0; i <= nr_entries; i++) {
1355 struct IO_APIC_route_entry entry;
1357 entry = ioapic_read_entry(apic, i);
1359 pr_debug(" %02x %02X ", i, entry.dest);
1360 pr_cont("%1d %1d %1d %1d %1d "
1366 entry.delivery_status,
1368 entry.delivery_mode,
1373 void intel_ir_io_apic_print_entries(unsigned int apic,
1374 unsigned int nr_entries)
1378 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1380 for (i = 0; i <= nr_entries; i++) {
1381 struct IR_IO_APIC_route_entry *ir_entry;
1382 struct IO_APIC_route_entry entry;
1384 entry = ioapic_read_entry(apic, i);
1386 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1388 pr_debug(" %02x %04X ", i, ir_entry->index);
1389 pr_cont("%1d %1d %1d %1d %1d "
1390 "%1d %1d %X %02X\n",
1396 ir_entry->delivery_status,
1403 void ioapic_zap_locks(void)
1405 raw_spin_lock_init(&ioapic_lock);
1408 static void __init print_IO_APIC(int ioapic_idx)
1410 union IO_APIC_reg_00 reg_00;
1411 union IO_APIC_reg_01 reg_01;
1412 union IO_APIC_reg_02 reg_02;
1413 union IO_APIC_reg_03 reg_03;
1414 unsigned long flags;
1416 raw_spin_lock_irqsave(&ioapic_lock, flags);
1417 reg_00.raw = io_apic_read(ioapic_idx, 0);
1418 reg_01.raw = io_apic_read(ioapic_idx, 1);
1419 if (reg_01.bits.version >= 0x10)
1420 reg_02.raw = io_apic_read(ioapic_idx, 2);
1421 if (reg_01.bits.version >= 0x20)
1422 reg_03.raw = io_apic_read(ioapic_idx, 3);
1423 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1425 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1426 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1427 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1428 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1429 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1431 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1432 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1433 reg_01.bits.entries);
1435 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1436 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1437 reg_01.bits.version);
1440 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1441 * but the value of reg_02 is read as the previous read register
1442 * value, so ignore it if reg_02 == reg_01.
1444 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1445 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1446 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1450 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1451 * or reg_03, but the value of reg_0[23] is read as the previous read
1452 * register value, so ignore it if reg_03 == reg_0[12].
1454 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1455 reg_03.raw != reg_01.raw) {
1456 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1457 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1460 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1462 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1465 void __init print_IO_APICs(void)
1468 struct irq_cfg *cfg;
1470 struct irq_chip *chip;
1472 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1473 for_each_ioapic(ioapic_idx)
1474 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1475 mpc_ioapic_id(ioapic_idx),
1476 ioapics[ioapic_idx].nr_registers);
1479 * We are a bit conservative about what we expect. We have to
1480 * know about every hardware change ASAP.
1482 printk(KERN_INFO "testing the IO APIC.......................\n");
1484 for_each_ioapic(ioapic_idx)
1485 print_IO_APIC(ioapic_idx);
1487 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1488 for_each_active_irq(irq) {
1489 struct irq_pin_list *entry;
1491 chip = irq_get_chip(irq);
1492 if (chip != &ioapic_chip)
1498 if (list_empty(&cfg->irq_2_pin))
1500 printk(KERN_DEBUG "IRQ%d ", irq);
1501 for_each_irq_pin(entry, cfg->irq_2_pin)
1502 pr_cont("-> %d:%d", entry->apic, entry->pin);
1506 printk(KERN_INFO ".................................... done.\n");
1509 /* Where if anywhere is the i8259 connect in external int mode */
1510 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1512 void __init enable_IO_APIC(void)
1514 int i8259_apic, i8259_pin;
1517 if (!nr_legacy_irqs())
1520 for_each_ioapic_pin(apic, pin) {
1521 /* See if any of the pins is in ExtINT mode */
1522 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1524 /* If the interrupt line is enabled and in ExtInt mode
1525 * I have found the pin where the i8259 is connected.
1527 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1528 ioapic_i8259.apic = apic;
1529 ioapic_i8259.pin = pin;
1534 /* Look to see what if the MP table has reported the ExtINT */
1535 /* If we could not find the appropriate pin by looking at the ioapic
1536 * the i8259 probably is not connected the ioapic but give the
1537 * mptable a chance anyway.
1539 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1540 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1541 /* Trust the MP table if nothing is setup in the hardware */
1542 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1543 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1544 ioapic_i8259.pin = i8259_pin;
1545 ioapic_i8259.apic = i8259_apic;
1547 /* Complain if the MP table and the hardware disagree */
1548 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1549 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1551 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1555 * Do not trust the IO-APIC being empty at bootup
1560 void native_disable_io_apic(void)
1563 * If the i8259 is routed through an IOAPIC
1564 * Put that IOAPIC in virtual wire mode
1565 * so legacy interrupts can be delivered.
1567 if (ioapic_i8259.pin != -1) {
1568 struct IO_APIC_route_entry entry;
1570 memset(&entry, 0, sizeof(entry));
1571 entry.mask = 0; /* Enabled */
1572 entry.trigger = 0; /* Edge */
1574 entry.polarity = 0; /* High */
1575 entry.delivery_status = 0;
1576 entry.dest_mode = 0; /* Physical */
1577 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1579 entry.dest = read_apic_id();
1582 * Add it to the IO-APIC irq-routing table:
1584 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1587 if (cpu_has_apic || apic_from_smp_config())
1588 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1593 * Not an __init, needed by the reboot code
1595 void disable_IO_APIC(void)
1598 * Clear the IO-APIC before rebooting:
1602 if (!nr_legacy_irqs())
1605 x86_io_apic_ops.disable();
1608 #ifdef CONFIG_X86_32
1610 * function to set the IO-APIC physical IDs based on the
1611 * values stored in the MPC table.
1613 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1615 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1617 union IO_APIC_reg_00 reg_00;
1618 physid_mask_t phys_id_present_map;
1621 unsigned char old_id;
1622 unsigned long flags;
1625 * This is broken; anything with a real cpu count has to
1626 * circumvent this idiocy regardless.
1628 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1631 * Set the IOAPIC ID to the value stored in the MPC table.
1633 for_each_ioapic(ioapic_idx) {
1634 /* Read the register 0 value */
1635 raw_spin_lock_irqsave(&ioapic_lock, flags);
1636 reg_00.raw = io_apic_read(ioapic_idx, 0);
1637 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1639 old_id = mpc_ioapic_id(ioapic_idx);
1641 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1642 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1643 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1644 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1646 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1650 * Sanity check, is the ID really free? Every APIC in a
1651 * system must have a unique ID or we get lots of nice
1652 * 'stuck on smp_invalidate_needed IPI wait' messages.
1654 if (apic->check_apicid_used(&phys_id_present_map,
1655 mpc_ioapic_id(ioapic_idx))) {
1656 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1657 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1658 for (i = 0; i < get_physical_broadcast(); i++)
1659 if (!physid_isset(i, phys_id_present_map))
1661 if (i >= get_physical_broadcast())
1662 panic("Max APIC ID exceeded!\n");
1663 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1665 physid_set(i, phys_id_present_map);
1666 ioapics[ioapic_idx].mp_config.apicid = i;
1669 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1671 apic_printk(APIC_VERBOSE, "Setting %d in the "
1672 "phys_id_present_map\n",
1673 mpc_ioapic_id(ioapic_idx));
1674 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1678 * We need to adjust the IRQ routing table
1679 * if the ID changed.
1681 if (old_id != mpc_ioapic_id(ioapic_idx))
1682 for (i = 0; i < mp_irq_entries; i++)
1683 if (mp_irqs[i].dstapic == old_id)
1685 = mpc_ioapic_id(ioapic_idx);
1688 * Update the ID register according to the right value
1689 * from the MPC table if they are different.
1691 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1694 apic_printk(APIC_VERBOSE, KERN_INFO
1695 "...changing IO-APIC physical APIC ID to %d ...",
1696 mpc_ioapic_id(ioapic_idx));
1698 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1699 raw_spin_lock_irqsave(&ioapic_lock, flags);
1700 io_apic_write(ioapic_idx, 0, reg_00.raw);
1701 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1706 raw_spin_lock_irqsave(&ioapic_lock, flags);
1707 reg_00.raw = io_apic_read(ioapic_idx, 0);
1708 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1709 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1710 pr_cont("could not set ID!\n");
1712 apic_printk(APIC_VERBOSE, " ok.\n");
1716 void __init setup_ioapic_ids_from_mpc(void)
1722 * Don't check I/O APIC IDs for xAPIC systems. They have
1723 * no meaning without the serial APIC bus.
1725 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1726 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1728 setup_ioapic_ids_from_mpc_nocheck();
1732 int no_timer_check __initdata;
1734 static int __init notimercheck(char *s)
1739 __setup("no_timer_check", notimercheck);
1742 * There is a nasty bug in some older SMP boards, their mptable lies
1743 * about the timer IRQ. We do the following to work around the situation:
1745 * - timer IRQ defaults to IO-APIC IRQ
1746 * - if this function detects that timer IRQs are defunct, then we fall
1747 * back to ISA timer IRQs
1749 static int __init timer_irq_works(void)
1751 unsigned long t1 = jiffies;
1752 unsigned long flags;
1757 local_save_flags(flags);
1759 /* Let ten ticks pass... */
1760 mdelay((10 * 1000) / HZ);
1761 local_irq_restore(flags);
1764 * Expect a few ticks at least, to be sure some possible
1765 * glue logic does not lock up after one or two first
1766 * ticks in a non-ExtINT mode. Also the local APIC
1767 * might have cached one ExtINT interrupt. Finally, at
1768 * least one tick may be lost due to delays.
1772 if (time_after(jiffies, t1 + 4))
1778 * In the SMP+IOAPIC case it might happen that there are an unspecified
1779 * number of pending IRQ events unhandled. These cases are very rare,
1780 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1781 * better to do it this way as thus we do not have to be aware of
1782 * 'pending' interrupts in the IRQ path, except at this point.
1785 * Edge triggered needs to resend any interrupt
1786 * that was delayed but this is now handled in the device
1791 * Starting up a edge-triggered IO-APIC interrupt is
1792 * nasty - we need to make sure that we get the edge.
1793 * If it is already asserted for some reason, we need
1794 * return 1 to indicate that is was pending.
1796 * This is not complete - we should be able to fake
1797 * an edge even if it isn't on the 8259A...
1800 static unsigned int startup_ioapic_irq(struct irq_data *data)
1802 int was_pending = 0, irq = data->irq;
1803 unsigned long flags;
1805 raw_spin_lock_irqsave(&ioapic_lock, flags);
1806 if (irq < nr_legacy_irqs()) {
1807 legacy_pic->mask(irq);
1808 if (legacy_pic->irq_pending(irq))
1811 __unmask_ioapic(data->chip_data);
1812 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1818 * Level and edge triggered IO-APIC interrupts need different handling,
1819 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1820 * handled with the level-triggered descriptor, but that one has slightly
1821 * more overhead. Level-triggered interrupts cannot be handled with the
1822 * edge-triggered handler, without risking IRQ storms and other ugly
1826 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
1829 struct irq_pin_list *entry;
1830 u8 vector = cfg->vector;
1832 for_each_irq_pin(entry, cfg->irq_2_pin) {
1838 io_apic_write(apic, 0x11 + pin*2, dest);
1839 reg = io_apic_read(apic, 0x10 + pin*2);
1840 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
1842 io_apic_modify(apic, 0x10 + pin*2, reg);
1846 int native_ioapic_set_affinity(struct irq_data *data,
1847 const struct cpumask *mask,
1850 unsigned int dest, irq = data->irq;
1851 unsigned long flags;
1854 if (!config_enabled(CONFIG_SMP))
1857 raw_spin_lock_irqsave(&ioapic_lock, flags);
1858 ret = apic_set_affinity(data, mask, &dest);
1860 /* Only the high 8 bits are valid. */
1861 dest = SET_APIC_LOGICAL_ID(dest);
1862 __target_IO_APIC_irq(irq, dest, data->chip_data);
1863 ret = IRQ_SET_MASK_OK_NOCOPY;
1865 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1869 atomic_t irq_mis_count;
1871 #ifdef CONFIG_GENERIC_PENDING_IRQ
1872 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
1874 struct irq_pin_list *entry;
1875 unsigned long flags;
1877 raw_spin_lock_irqsave(&ioapic_lock, flags);
1878 for_each_irq_pin(entry, cfg->irq_2_pin) {
1883 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1884 /* Is the remote IRR bit set? */
1885 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1886 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1890 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1895 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
1897 /* If we are moving the irq we need to mask it */
1898 if (unlikely(irqd_is_setaffinity_pending(data))) {
1905 static inline void ioapic_irqd_unmask(struct irq_data *data,
1906 struct irq_cfg *cfg, bool masked)
1908 if (unlikely(masked)) {
1909 /* Only migrate the irq if the ack has been received.
1911 * On rare occasions the broadcast level triggered ack gets
1912 * delayed going to ioapics, and if we reprogram the
1913 * vector while Remote IRR is still set the irq will never
1916 * To prevent this scenario we read the Remote IRR bit
1917 * of the ioapic. This has two effects.
1918 * - On any sane system the read of the ioapic will
1919 * flush writes (and acks) going to the ioapic from
1921 * - We get to see if the ACK has actually been delivered.
1923 * Based on failed experiments of reprogramming the
1924 * ioapic entry from outside of irq context starting
1925 * with masking the ioapic entry and then polling until
1926 * Remote IRR was clear before reprogramming the
1927 * ioapic I don't trust the Remote IRR bit to be
1928 * completey accurate.
1930 * However there appears to be no other way to plug
1931 * this race, so if the Remote IRR bit is not
1932 * accurate and is causing problems then it is a hardware bug
1933 * and you can go talk to the chipset vendor about it.
1935 if (!io_apic_level_ack_pending(cfg))
1936 irq_move_masked_irq(data);
1941 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
1945 static inline void ioapic_irqd_unmask(struct irq_data *data,
1946 struct irq_cfg *cfg, bool masked)
1951 static void ack_ioapic_level(struct irq_data *data)
1953 struct irq_cfg *cfg = data->chip_data;
1954 int i, irq = data->irq;
1958 irq_complete_move(cfg);
1959 masked = ioapic_irqd_mask(data, cfg);
1962 * It appears there is an erratum which affects at least version 0x11
1963 * of I/O APIC (that's the 82093AA and cores integrated into various
1964 * chipsets). Under certain conditions a level-triggered interrupt is
1965 * erroneously delivered as edge-triggered one but the respective IRR
1966 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1967 * message but it will never arrive and further interrupts are blocked
1968 * from the source. The exact reason is so far unknown, but the
1969 * phenomenon was observed when two consecutive interrupt requests
1970 * from a given source get delivered to the same CPU and the source is
1971 * temporarily disabled in between.
1973 * A workaround is to simulate an EOI message manually. We achieve it
1974 * by setting the trigger mode to edge and then to level when the edge
1975 * trigger mode gets detected in the TMR of a local APIC for a
1976 * level-triggered interrupt. We mask the source for the time of the
1977 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1978 * The idea is from Manfred Spraul. --macro
1980 * Also in the case when cpu goes offline, fixup_irqs() will forward
1981 * any unhandled interrupt on the offlined cpu to the new cpu
1982 * destination that is handling the corresponding interrupt. This
1983 * interrupt forwarding is done via IPI's. Hence, in this case also
1984 * level-triggered io-apic interrupt will be seen as an edge
1985 * interrupt in the IRR. And we can't rely on the cpu's EOI
1986 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1987 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1988 * supporting EOI register, we do an explicit EOI to clear the
1989 * remote IRR and on IO-APIC's which don't have an EOI register,
1990 * we use the above logic (mask+edge followed by unmask+level) from
1991 * Manfred Spraul to clear the remote IRR.
1994 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1997 * We must acknowledge the irq before we move it or the acknowledge will
1998 * not propagate properly.
2003 * Tail end of clearing remote IRR bit (either by delivering the EOI
2004 * message via io-apic EOI register write or simulating it using
2005 * mask+edge followed by unnask+level logic) manually when the
2006 * level triggered interrupt is seen as the edge triggered interrupt
2009 if (!(v & (1 << (i & 0x1f)))) {
2010 atomic_inc(&irq_mis_count);
2012 eoi_ioapic_irq(irq, cfg);
2015 ioapic_irqd_unmask(data, cfg, masked);
2018 static struct irq_chip ioapic_chip __read_mostly = {
2020 .irq_startup = startup_ioapic_irq,
2021 .irq_mask = mask_ioapic_irq,
2022 .irq_unmask = unmask_ioapic_irq,
2023 .irq_ack = apic_ack_edge,
2024 .irq_eoi = ack_ioapic_level,
2025 .irq_set_affinity = native_ioapic_set_affinity,
2026 .irq_retrigger = apic_retrigger_irq,
2027 .flags = IRQCHIP_SKIP_SET_WAKE,
2030 static inline void init_IO_APIC_traps(void)
2032 struct irq_cfg *cfg;
2035 for_each_active_irq(irq) {
2037 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2039 * Hmm.. We don't have an entry for this,
2040 * so default to an old-fashioned 8259
2041 * interrupt if we can..
2043 if (irq < nr_legacy_irqs())
2044 legacy_pic->make_irq(irq);
2046 /* Strange. Oh, well.. */
2047 irq_set_chip(irq, &no_irq_chip);
2053 * The local APIC irq-chip implementation:
2056 static void mask_lapic_irq(struct irq_data *data)
2060 v = apic_read(APIC_LVT0);
2061 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2064 static void unmask_lapic_irq(struct irq_data *data)
2068 v = apic_read(APIC_LVT0);
2069 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2072 static void ack_lapic_irq(struct irq_data *data)
2077 static struct irq_chip lapic_chip __read_mostly = {
2078 .name = "local-APIC",
2079 .irq_mask = mask_lapic_irq,
2080 .irq_unmask = unmask_lapic_irq,
2081 .irq_ack = ack_lapic_irq,
2084 static void lapic_register_intr(int irq)
2086 irq_clear_status_flags(irq, IRQ_LEVEL);
2087 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2092 * This looks a bit hackish but it's about the only one way of sending
2093 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2094 * not support the ExtINT mode, unfortunately. We need to send these
2095 * cycles as some i82489DX-based boards have glue logic that keeps the
2096 * 8259A interrupt line asserted until INTA. --macro
2098 static inline void __init unlock_ExtINT_logic(void)
2101 struct IO_APIC_route_entry entry0, entry1;
2102 unsigned char save_control, save_freq_select;
2104 pin = find_isa_irq_pin(8, mp_INT);
2109 apic = find_isa_irq_apic(8, mp_INT);
2115 entry0 = ioapic_read_entry(apic, pin);
2116 clear_IO_APIC_pin(apic, pin);
2118 memset(&entry1, 0, sizeof(entry1));
2120 entry1.dest_mode = 0; /* physical delivery */
2121 entry1.mask = 0; /* unmask IRQ now */
2122 entry1.dest = hard_smp_processor_id();
2123 entry1.delivery_mode = dest_ExtINT;
2124 entry1.polarity = entry0.polarity;
2128 ioapic_write_entry(apic, pin, entry1);
2130 save_control = CMOS_READ(RTC_CONTROL);
2131 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2132 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2134 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2139 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2143 CMOS_WRITE(save_control, RTC_CONTROL);
2144 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2145 clear_IO_APIC_pin(apic, pin);
2147 ioapic_write_entry(apic, pin, entry0);
2150 static int disable_timer_pin_1 __initdata;
2151 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2152 static int __init disable_timer_pin_setup(char *arg)
2154 disable_timer_pin_1 = 1;
2157 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2160 * This code may look a bit paranoid, but it's supposed to cooperate with
2161 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2162 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2163 * fanatically on his truly buggy board.
2165 * FIXME: really need to revamp this for all platforms.
2167 static inline void __init check_timer(void)
2169 struct irq_cfg *cfg = irq_cfg(0);
2170 int node = cpu_to_node(0);
2171 int apic1, pin1, apic2, pin2;
2172 unsigned long flags;
2175 local_irq_save(flags);
2178 * get/set the timer IRQ vector:
2180 legacy_pic->mask(0);
2181 assign_irq_vector(0, cfg, apic->target_cpus());
2184 * As IRQ0 is to be enabled in the 8259A, the virtual
2185 * wire has to be disabled in the local APIC. Also
2186 * timer interrupts need to be acknowledged manually in
2187 * the 8259A for the i82489DX when using the NMI
2188 * watchdog as that APIC treats NMIs as level-triggered.
2189 * The AEOI mode will finish them in the 8259A
2192 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2193 legacy_pic->init(1);
2195 pin1 = find_isa_irq_pin(0, mp_INT);
2196 apic1 = find_isa_irq_apic(0, mp_INT);
2197 pin2 = ioapic_i8259.pin;
2198 apic2 = ioapic_i8259.apic;
2200 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2201 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2202 cfg->vector, apic1, pin1, apic2, pin2);
2205 * Some BIOS writers are clueless and report the ExtINTA
2206 * I/O APIC input from the cascaded 8259A as the timer
2207 * interrupt input. So just in case, if only one pin
2208 * was found above, try it both directly and through the
2212 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2216 } else if (pin2 == -1) {
2223 * Ok, does IRQ0 through the IOAPIC work?
2226 add_pin_to_irq_node(cfg, node, apic1, pin1);
2227 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2229 /* for edge trigger, setup_ioapic_irq already
2230 * leave it unmasked.
2231 * so only need to unmask if it is level-trigger
2232 * do we really have level trigger timer?
2235 idx = find_irq_entry(apic1, pin1, mp_INT);
2236 if (idx != -1 && irq_trigger(idx))
2239 if (timer_irq_works()) {
2240 if (disable_timer_pin_1 > 0)
2241 clear_IO_APIC_pin(0, pin1);
2244 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2245 local_irq_disable();
2246 clear_IO_APIC_pin(apic1, pin1);
2248 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2249 "8254 timer not connected to IO-APIC\n");
2251 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2252 "(IRQ0) through the 8259A ...\n");
2253 apic_printk(APIC_QUIET, KERN_INFO
2254 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2256 * legacy devices should be connected to IO APIC #0
2258 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2259 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2260 legacy_pic->unmask(0);
2261 if (timer_irq_works()) {
2262 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2266 * Cleanup, just in case ...
2268 local_irq_disable();
2269 legacy_pic->mask(0);
2270 clear_IO_APIC_pin(apic2, pin2);
2271 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2274 apic_printk(APIC_QUIET, KERN_INFO
2275 "...trying to set up timer as Virtual Wire IRQ...\n");
2277 lapic_register_intr(0);
2278 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2279 legacy_pic->unmask(0);
2281 if (timer_irq_works()) {
2282 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2285 local_irq_disable();
2286 legacy_pic->mask(0);
2287 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2288 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2290 apic_printk(APIC_QUIET, KERN_INFO
2291 "...trying to set up timer as ExtINT IRQ...\n");
2293 legacy_pic->init(0);
2294 legacy_pic->make_irq(0);
2295 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2297 unlock_ExtINT_logic();
2299 if (timer_irq_works()) {
2300 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2303 local_irq_disable();
2304 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2305 if (x2apic_preenabled)
2306 apic_printk(APIC_QUIET, KERN_INFO
2307 "Perhaps problem with the pre-enabled x2apic mode\n"
2308 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2309 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2310 "report. Then try booting with the 'noapic' option.\n");
2312 local_irq_restore(flags);
2316 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2317 * to devices. However there may be an I/O APIC pin available for
2318 * this interrupt regardless. The pin may be left unconnected, but
2319 * typically it will be reused as an ExtINT cascade interrupt for
2320 * the master 8259A. In the MPS case such a pin will normally be
2321 * reported as an ExtINT interrupt in the MP table. With ACPI
2322 * there is no provision for ExtINT interrupts, and in the absence
2323 * of an override it would be treated as an ordinary ISA I/O APIC
2324 * interrupt, that is edge-triggered and unmasked by default. We
2325 * used to do this, but it caused problems on some systems because
2326 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2327 * the same ExtINT cascade interrupt to drive the local APIC of the
2328 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2329 * the I/O APIC in all cases now. No actual device should request
2330 * it anyway. --macro
2332 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2334 static int mp_irqdomain_create(int ioapic)
2337 int hwirqs = mp_ioapic_pin_count(ioapic);
2338 struct ioapic *ip = &ioapics[ioapic];
2339 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2340 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2342 size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
2343 ip->pin_info = kzalloc(size, GFP_KERNEL);
2347 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2350 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2351 (void *)(long)ioapic);
2352 if(!ip->irqdomain) {
2353 kfree(ip->pin_info);
2354 ip->pin_info = NULL;
2358 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2359 cfg->type == IOAPIC_DOMAIN_STRICT)
2360 ioapic_dynirq_base = max(ioapic_dynirq_base,
2361 gsi_cfg->gsi_end + 1);
2363 if (gsi_cfg->gsi_base == 0)
2364 irq_set_default_host(ip->irqdomain);
2369 static void ioapic_destroy_irqdomain(int idx)
2371 if (ioapics[idx].irqdomain) {
2372 irq_domain_remove(ioapics[idx].irqdomain);
2373 ioapics[idx].irqdomain = NULL;
2375 kfree(ioapics[idx].pin_info);
2376 ioapics[idx].pin_info = NULL;
2379 void __init setup_IO_APIC(void)
2384 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2386 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2388 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2389 for_each_ioapic(ioapic)
2390 BUG_ON(mp_irqdomain_create(ioapic));
2393 * Set up IO-APIC IRQ routing.
2395 x86_init.mpparse.setup_ioapic_ids();
2398 setup_IO_APIC_irqs();
2399 init_IO_APIC_traps();
2400 if (nr_legacy_irqs())
2403 ioapic_initialized = 1;
2407 * Called after all the initialization is done. If we didn't find any
2408 * APIC bugs then we can allow the modify fast path
2411 static int __init io_apic_bug_finalize(void)
2413 if (sis_apic_bug == -1)
2418 late_initcall(io_apic_bug_finalize);
2420 static void resume_ioapic_id(int ioapic_idx)
2422 unsigned long flags;
2423 union IO_APIC_reg_00 reg_00;
2425 raw_spin_lock_irqsave(&ioapic_lock, flags);
2426 reg_00.raw = io_apic_read(ioapic_idx, 0);
2427 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2428 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2429 io_apic_write(ioapic_idx, 0, reg_00.raw);
2431 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2434 static void ioapic_resume(void)
2438 for_each_ioapic_reverse(ioapic_idx)
2439 resume_ioapic_id(ioapic_idx);
2441 restore_ioapic_entries();
2444 static struct syscore_ops ioapic_syscore_ops = {
2445 .suspend = save_ioapic_entries,
2446 .resume = ioapic_resume,
2449 static int __init ioapic_init_ops(void)
2451 register_syscore_ops(&ioapic_syscore_ops);
2456 device_initcall(ioapic_init_ops);
2459 * MSI message composition
2461 void native_compose_msi_msg(struct pci_dev *pdev,
2462 unsigned int irq, unsigned int dest,
2463 struct msi_msg *msg, u8 hpet_id)
2465 struct irq_cfg *cfg = irq_cfg(irq);
2467 msg->address_hi = MSI_ADDR_BASE_HI;
2469 if (x2apic_enabled())
2470 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
2474 ((apic->irq_dest_mode == 0) ?
2475 MSI_ADDR_DEST_MODE_PHYSICAL:
2476 MSI_ADDR_DEST_MODE_LOGICAL) |
2477 ((apic->irq_delivery_mode != dest_LowestPrio) ?
2478 MSI_ADDR_REDIRECTION_CPU:
2479 MSI_ADDR_REDIRECTION_LOWPRI) |
2480 MSI_ADDR_DEST_ID(dest);
2483 MSI_DATA_TRIGGER_EDGE |
2484 MSI_DATA_LEVEL_ASSERT |
2485 ((apic->irq_delivery_mode != dest_LowestPrio) ?
2486 MSI_DATA_DELIVERY_FIXED:
2487 MSI_DATA_DELIVERY_LOWPRI) |
2488 MSI_DATA_VECTOR(cfg->vector);
2491 #ifdef CONFIG_PCI_MSI
2492 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
2493 struct msi_msg *msg, u8 hpet_id)
2495 struct irq_cfg *cfg;
2503 err = assign_irq_vector(irq, cfg, apic->target_cpus());
2507 err = apic->cpu_mask_to_apicid_and(cfg->domain,
2508 apic->target_cpus(), &dest);
2512 x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
2518 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
2520 struct irq_cfg *cfg = data->chip_data;
2525 ret = apic_set_affinity(data, mask, &dest);
2529 __get_cached_msi_msg(data->msi_desc, &msg);
2531 msg.data &= ~MSI_DATA_VECTOR_MASK;
2532 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2533 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2534 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2536 __pci_write_msi_msg(data->msi_desc, &msg);
2538 return IRQ_SET_MASK_OK_NOCOPY;
2542 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2543 * which implement the MSI or MSI-X Capability Structure.
2545 static struct irq_chip msi_chip = {
2547 .irq_unmask = pci_msi_unmask_irq,
2548 .irq_mask = pci_msi_mask_irq,
2549 .irq_ack = apic_ack_edge,
2550 .irq_set_affinity = msi_set_affinity,
2551 .irq_retrigger = apic_retrigger_irq,
2552 .flags = IRQCHIP_SKIP_SET_WAKE,
2555 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
2556 unsigned int irq_base, unsigned int irq_offset)
2558 struct irq_chip *chip = &msi_chip;
2560 unsigned int irq = irq_base + irq_offset;
2563 ret = msi_compose_msg(dev, irq, &msg, -1);
2567 irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
2570 * MSI-X message is written per-IRQ, the offset is always 0.
2571 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
2574 pci_write_msi_msg(irq, &msg);
2576 setup_remapped_irq(irq, irq_cfg(irq), chip);
2578 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
2580 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
2585 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2587 struct msi_desc *msidesc;
2591 /* Multiple MSI vectors only supported with interrupt remapping */
2592 if (type == PCI_CAP_ID_MSI && nvec > 1)
2595 node = dev_to_node(&dev->dev);
2597 list_for_each_entry(msidesc, &dev->msi_list, list) {
2598 irq = irq_alloc_hwirq(node);
2602 ret = setup_msi_irq(dev, msidesc, irq, 0);
2604 irq_free_hwirq(irq);
2612 void native_teardown_msi_irq(unsigned int irq)
2614 irq_free_hwirq(irq);
2617 #ifdef CONFIG_DMAR_TABLE
2619 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
2622 struct irq_cfg *cfg = data->chip_data;
2623 unsigned int dest, irq = data->irq;
2627 ret = apic_set_affinity(data, mask, &dest);
2631 dmar_msi_read(irq, &msg);
2633 msg.data &= ~MSI_DATA_VECTOR_MASK;
2634 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2635 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2636 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2637 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
2639 dmar_msi_write(irq, &msg);
2641 return IRQ_SET_MASK_OK_NOCOPY;
2644 static struct irq_chip dmar_msi_type = {
2646 .irq_unmask = dmar_msi_unmask,
2647 .irq_mask = dmar_msi_mask,
2648 .irq_ack = apic_ack_edge,
2649 .irq_set_affinity = dmar_msi_set_affinity,
2650 .irq_retrigger = apic_retrigger_irq,
2651 .flags = IRQCHIP_SKIP_SET_WAKE,
2654 int arch_setup_dmar_msi(unsigned int irq)
2659 ret = msi_compose_msg(NULL, irq, &msg, -1);
2662 dmar_msi_write(irq, &msg);
2663 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2669 #ifdef CONFIG_HPET_TIMER
2671 static int hpet_msi_set_affinity(struct irq_data *data,
2672 const struct cpumask *mask, bool force)
2674 struct irq_cfg *cfg = data->chip_data;
2679 ret = apic_set_affinity(data, mask, &dest);
2683 hpet_msi_read(data->handler_data, &msg);
2685 msg.data &= ~MSI_DATA_VECTOR_MASK;
2686 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2687 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2688 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2690 hpet_msi_write(data->handler_data, &msg);
2692 return IRQ_SET_MASK_OK_NOCOPY;
2695 static struct irq_chip hpet_msi_type = {
2697 .irq_unmask = hpet_msi_unmask,
2698 .irq_mask = hpet_msi_mask,
2699 .irq_ack = apic_ack_edge,
2700 .irq_set_affinity = hpet_msi_set_affinity,
2701 .irq_retrigger = apic_retrigger_irq,
2702 .flags = IRQCHIP_SKIP_SET_WAKE,
2705 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
2707 struct irq_chip *chip = &hpet_msi_type;
2711 ret = msi_compose_msg(NULL, irq, &msg, id);
2715 hpet_msi_write(irq_get_handler_data(irq), &msg);
2716 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
2717 setup_remapped_irq(irq, irq_cfg(irq), chip);
2719 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
2724 #endif /* CONFIG_PCI_MSI */
2726 * Hypertransport interrupt support
2728 #ifdef CONFIG_HT_IRQ
2730 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2732 struct ht_irq_msg msg;
2733 fetch_ht_irq_msg(irq, &msg);
2735 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2736 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2738 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2739 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2741 write_ht_irq_msg(irq, &msg);
2745 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
2747 struct irq_cfg *cfg = data->chip_data;
2751 ret = apic_set_affinity(data, mask, &dest);
2755 target_ht_irq(data->irq, dest, cfg->vector);
2756 return IRQ_SET_MASK_OK_NOCOPY;
2759 static struct irq_chip ht_irq_chip = {
2761 .irq_mask = mask_ht_irq,
2762 .irq_unmask = unmask_ht_irq,
2763 .irq_ack = apic_ack_edge,
2764 .irq_set_affinity = ht_set_affinity,
2765 .irq_retrigger = apic_retrigger_irq,
2766 .flags = IRQCHIP_SKIP_SET_WAKE,
2769 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2771 struct irq_cfg *cfg;
2772 struct ht_irq_msg msg;
2780 err = assign_irq_vector(irq, cfg, apic->target_cpus());
2784 err = apic->cpu_mask_to_apicid_and(cfg->domain,
2785 apic->target_cpus(), &dest);
2789 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2793 HT_IRQ_LOW_DEST_ID(dest) |
2794 HT_IRQ_LOW_VECTOR(cfg->vector) |
2795 ((apic->irq_dest_mode == 0) ?
2796 HT_IRQ_LOW_DM_PHYSICAL :
2797 HT_IRQ_LOW_DM_LOGICAL) |
2798 HT_IRQ_LOW_RQEOI_EDGE |
2799 ((apic->irq_delivery_mode != dest_LowestPrio) ?
2800 HT_IRQ_LOW_MT_FIXED :
2801 HT_IRQ_LOW_MT_ARBITRATED) |
2802 HT_IRQ_LOW_IRQ_MASKED;
2804 write_ht_irq_msg(irq, &msg);
2806 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
2807 handle_edge_irq, "edge");
2809 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
2813 #endif /* CONFIG_HT_IRQ */
2816 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
2818 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
2823 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
2825 setup_ioapic_irq(irq, cfg, attr);
2829 static int io_apic_get_redir_entries(int ioapic)
2831 union IO_APIC_reg_01 reg_01;
2832 unsigned long flags;
2834 raw_spin_lock_irqsave(&ioapic_lock, flags);
2835 reg_01.raw = io_apic_read(ioapic, 1);
2836 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2838 /* The register returns the maximum index redir index
2839 * supported, which is one less than the total number of redir
2842 return reg_01.bits.entries + 1;
2845 unsigned int arch_dynirq_lower_bound(unsigned int from)
2848 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2849 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2851 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2854 int __init arch_probe_nr_irqs(void)
2858 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
2859 nr_irqs = NR_VECTORS * nr_cpu_ids;
2861 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
2862 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
2864 * for MSI and HT dyn irq
2874 #ifdef CONFIG_X86_32
2875 static int io_apic_get_unique_id(int ioapic, int apic_id)
2877 union IO_APIC_reg_00 reg_00;
2878 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2880 unsigned long flags;
2884 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2885 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2886 * supports up to 16 on one shared APIC bus.
2888 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2889 * advantage of new APIC bus architecture.
2892 if (physids_empty(apic_id_map))
2893 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2895 raw_spin_lock_irqsave(&ioapic_lock, flags);
2896 reg_00.raw = io_apic_read(ioapic, 0);
2897 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2899 if (apic_id >= get_physical_broadcast()) {
2900 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2901 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2902 apic_id = reg_00.bits.ID;
2906 * Every APIC in a system must have a unique ID or we get lots of nice
2907 * 'stuck on smp_invalidate_needed IPI wait' messages.
2909 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2911 for (i = 0; i < get_physical_broadcast(); i++) {
2912 if (!apic->check_apicid_used(&apic_id_map, i))
2916 if (i == get_physical_broadcast())
2917 panic("Max apic_id exceeded!\n");
2919 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2920 "trying %d\n", ioapic, apic_id, i);
2925 apic->apicid_to_cpu_present(apic_id, &tmp);
2926 physids_or(apic_id_map, apic_id_map, tmp);
2928 if (reg_00.bits.ID != apic_id) {
2929 reg_00.bits.ID = apic_id;
2931 raw_spin_lock_irqsave(&ioapic_lock, flags);
2932 io_apic_write(ioapic, 0, reg_00.raw);
2933 reg_00.raw = io_apic_read(ioapic, 0);
2934 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2937 if (reg_00.bits.ID != apic_id) {
2938 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2944 apic_printk(APIC_VERBOSE, KERN_INFO
2945 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2950 static u8 io_apic_unique_id(int idx, u8 id)
2952 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2953 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2954 return io_apic_get_unique_id(idx, id);
2959 static u8 io_apic_unique_id(int idx, u8 id)
2961 union IO_APIC_reg_00 reg_00;
2962 DECLARE_BITMAP(used, 256);
2963 unsigned long flags;
2967 bitmap_zero(used, 256);
2969 __set_bit(mpc_ioapic_id(i), used);
2971 /* Hand out the requested id if available */
2972 if (!test_bit(id, used))
2976 * Read the current id from the ioapic and keep it if
2979 raw_spin_lock_irqsave(&ioapic_lock, flags);
2980 reg_00.raw = io_apic_read(idx, 0);
2981 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2982 new_id = reg_00.bits.ID;
2983 if (!test_bit(new_id, used)) {
2984 apic_printk(APIC_VERBOSE, KERN_INFO
2985 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2991 * Get the next free id and write it to the ioapic.
2993 new_id = find_first_zero_bit(used, 256);
2994 reg_00.bits.ID = new_id;
2995 raw_spin_lock_irqsave(&ioapic_lock, flags);
2996 io_apic_write(idx, 0, reg_00.raw);
2997 reg_00.raw = io_apic_read(idx, 0);
2998 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3000 BUG_ON(reg_00.bits.ID != new_id);
3006 static int io_apic_get_version(int ioapic)
3008 union IO_APIC_reg_01 reg_01;
3009 unsigned long flags;
3011 raw_spin_lock_irqsave(&ioapic_lock, flags);
3012 reg_01.raw = io_apic_read(ioapic, 1);
3013 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3015 return reg_01.bits.version;
3018 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3020 int ioapic, pin, idx;
3022 if (skip_ioapic_setup)
3025 ioapic = mp_find_ioapic(gsi);
3029 pin = mp_find_ioapic_pin(ioapic, gsi);
3033 idx = find_irq_entry(ioapic, pin, mp_INT);
3037 *trigger = irq_trigger(idx);
3038 *polarity = irq_polarity(idx);
3043 * This function currently is only a helper for the i386 smp boot process where
3044 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3045 * so mask in all cases should simply be apic->target_cpus()
3048 void __init setup_ioapic_dest(void)
3050 int pin, ioapic, irq, irq_entry;
3051 const struct cpumask *mask;
3052 struct irq_data *idata;
3054 if (skip_ioapic_setup == 1)
3057 for_each_ioapic_pin(ioapic, pin) {
3058 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3059 if (irq_entry == -1)
3062 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
3063 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
3066 idata = irq_get_irq_data(irq);
3069 * Honour affinities which have been set in early boot
3071 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3072 mask = idata->affinity;
3074 mask = apic->target_cpus();
3076 x86_io_apic_ops.set_affinity(idata, mask, false);
3082 #define IOAPIC_RESOURCE_NAME_SIZE 11
3084 static struct resource *ioapic_resources;
3086 static struct resource * __init ioapic_setup_resources(void)
3089 struct resource *res;
3098 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3101 mem = alloc_bootmem(n);
3104 mem += sizeof(struct resource) * num;
3107 for_each_ioapic(i) {
3108 res[num].name = mem;
3109 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3110 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3111 mem += IOAPIC_RESOURCE_NAME_SIZE;
3113 ioapics[i].iomem_res = res;
3116 ioapic_resources = res;
3121 void __init native_io_apic_init_mappings(void)
3123 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3124 struct resource *ioapic_res;
3127 ioapic_res = ioapic_setup_resources();
3128 for_each_ioapic(i) {
3129 if (smp_found_config) {
3130 ioapic_phys = mpc_ioapic_addr(i);
3131 #ifdef CONFIG_X86_32
3134 "WARNING: bogus zero IO-APIC "
3135 "address found in MPTABLE, "
3136 "disabling IO/APIC support!\n");
3137 smp_found_config = 0;
3138 skip_ioapic_setup = 1;
3139 goto fake_ioapic_page;
3143 #ifdef CONFIG_X86_32
3146 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3147 ioapic_phys = __pa(ioapic_phys);
3149 set_fixmap_nocache(idx, ioapic_phys);
3150 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3151 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3155 ioapic_res->start = ioapic_phys;
3156 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3161 void __init ioapic_insert_resources(void)
3164 struct resource *r = ioapic_resources;
3169 "IO APIC resources couldn't be allocated.\n");
3173 for_each_ioapic(i) {
3174 insert_resource(&iomem_resource, r);
3179 int mp_find_ioapic(u32 gsi)
3183 if (nr_ioapics == 0)
3186 /* Find the IOAPIC that manages this GSI. */
3187 for_each_ioapic(i) {
3188 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3189 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
3193 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3197 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3199 struct mp_ioapic_gsi *gsi_cfg;
3201 if (WARN_ON(ioapic < 0))
3204 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3205 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3208 return gsi - gsi_cfg->gsi_base;
3211 static int bad_ioapic_register(int idx)
3213 union IO_APIC_reg_00 reg_00;
3214 union IO_APIC_reg_01 reg_01;
3215 union IO_APIC_reg_02 reg_02;
3217 reg_00.raw = io_apic_read(idx, 0);
3218 reg_01.raw = io_apic_read(idx, 1);
3219 reg_02.raw = io_apic_read(idx, 2);
3221 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3222 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3223 mpc_ioapic_addr(idx));
3230 static int find_free_ioapic_entry(void)
3234 for (idx = 0; idx < MAX_IO_APICS; idx++)
3235 if (ioapics[idx].nr_registers == 0)
3238 return MAX_IO_APICS;
3242 * mp_register_ioapic - Register an IOAPIC device
3243 * @id: hardware IOAPIC ID
3244 * @address: physical address of IOAPIC register area
3245 * @gsi_base: base of GSI associated with the IOAPIC
3246 * @cfg: configuration information for the IOAPIC
3248 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
3249 struct ioapic_domain_cfg *cfg)
3251 bool hotplug = !!ioapic_initialized;
3252 struct mp_ioapic_gsi *gsi_cfg;
3253 int idx, ioapic, entries;
3257 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
3260 for_each_ioapic(ioapic)
3261 if (ioapics[ioapic].mp_config.apicaddr == address) {
3262 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
3267 idx = find_free_ioapic_entry();
3268 if (idx >= MAX_IO_APICS) {
3269 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3274 ioapics[idx].mp_config.type = MP_IOAPIC;
3275 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3276 ioapics[idx].mp_config.apicaddr = address;
3278 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3279 if (bad_ioapic_register(idx)) {
3280 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3284 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
3285 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3288 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3289 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3291 entries = io_apic_get_redir_entries(idx);
3292 gsi_end = gsi_base + entries - 1;
3293 for_each_ioapic(ioapic) {
3294 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3295 if ((gsi_base >= gsi_cfg->gsi_base &&
3296 gsi_base <= gsi_cfg->gsi_end) ||
3297 (gsi_end >= gsi_cfg->gsi_base &&
3298 gsi_end <= gsi_cfg->gsi_end)) {
3299 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
3301 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3302 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3306 gsi_cfg = mp_ioapic_gsi_routing(idx);
3307 gsi_cfg->gsi_base = gsi_base;
3308 gsi_cfg->gsi_end = gsi_end;
3310 ioapics[idx].irqdomain = NULL;
3311 ioapics[idx].irqdomain_cfg = *cfg;
3314 * If mp_register_ioapic() is called during early boot stage when
3315 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
3316 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
3319 if (mp_irqdomain_create(idx)) {
3320 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3323 alloc_ioapic_saved_registers(idx);
3326 if (gsi_cfg->gsi_end >= gsi_top)
3327 gsi_top = gsi_cfg->gsi_end + 1;
3328 if (nr_ioapics <= idx)
3329 nr_ioapics = idx + 1;
3331 /* Set nr_registers to mark entry present */
3332 ioapics[idx].nr_registers = entries;
3334 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3335 idx, mpc_ioapic_id(idx),
3336 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3337 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3342 int mp_unregister_ioapic(u32 gsi_base)
3346 struct mp_pin_info *pin_info;
3348 for_each_ioapic(ioapic)
3349 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
3354 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
3358 for_each_pin(ioapic, pin) {
3359 pin_info = mp_pin_info(ioapic, pin);
3360 if (pin_info->count) {
3361 pr_warn("pin%d on IOAPIC%d is still in use.\n",
3367 /* Mark entry not present */
3368 ioapics[ioapic].nr_registers = 0;
3369 ioapic_destroy_irqdomain(ioapic);
3370 free_ioapic_saved_registers(ioapic);
3371 if (ioapics[ioapic].iomem_res)
3372 release_resource(ioapics[ioapic].iomem_res);
3373 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
3374 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
3379 int mp_ioapic_registered(u32 gsi_base)
3383 for_each_ioapic(ioapic)
3384 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
3390 int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
3391 irq_hw_number_t hwirq)
3393 int ioapic = (int)(long)domain->host_data;
3394 struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
3395 struct io_apic_irq_attr attr;
3397 /* Get default attribute if not set by caller yet */
3399 u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
3401 if (acpi_get_override_irq(gsi, &info->trigger,
3402 &info->polarity) < 0) {
3404 * PCI interrupts are always polarity one level
3410 info->node = NUMA_NO_NODE;
3413 * setup_IO_APIC_irqs() programs all legacy IRQs with default
3414 * trigger and polarity attributes. Don't set the flag for that
3415 * case so the first legacy IRQ user could reprogram the pin
3416 * with real trigger and polarity attributes.
3418 if (virq >= nr_legacy_irqs() || info->count)
3421 set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
3424 return io_apic_setup_irq_pin(virq, info->node, &attr);
3427 void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq)
3429 struct irq_data *data = irq_get_irq_data(virq);
3430 struct irq_cfg *cfg = irq_cfg(virq);
3431 int ioapic = (int)(long)domain->host_data;
3432 int pin = (int)data->hwirq;
3434 ioapic_mask_entry(ioapic, pin);
3435 __remove_pin_from_irq(cfg, ioapic, pin);
3436 WARN_ON(!list_empty(&cfg->irq_2_pin));
3437 arch_teardown_hwirq(virq);
3440 int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
3444 struct mp_pin_info *info;
3446 ioapic = mp_find_ioapic(gsi);
3450 pin = mp_find_ioapic_pin(ioapic, gsi);
3451 info = mp_pin_info(ioapic, pin);
3452 trigger = trigger ? 1 : 0;
3453 polarity = polarity ? 1 : 0;
3455 mutex_lock(&ioapic_mutex);
3457 info->trigger = trigger;
3458 info->polarity = polarity;
3461 } else if (info->trigger != trigger || info->polarity != polarity) {
3464 mutex_unlock(&ioapic_mutex);
3469 /* Enable IOAPIC early just for system timer */
3470 void __init pre_init_apic_IRQ0(void)
3472 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3474 printk(KERN_INFO "Early APIC setup for system timer0\n");
3476 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3477 &phys_cpu_present_map);
3481 io_apic_setup_irq_pin(0, 0, &attr);
3482 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,