arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51 int uv_min_hub_revision_id;
  52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  53 unsigned int uv_apicid_hibits;
  54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  55
  56 static struct apic apic_x2apic_uv_x;
  57
  58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  59 {
  60         unsigned long val, *mmr;
  61
  62         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  63         val = *mmr;
  64         early_iounmap(mmr, sizeof(*mmr));
  65         return val;
  66 }
  67
  68 static inline bool is_GRU_range(u64 start, u64 end)
  69 {
  70         if (gru_dist_base) {
  71                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  72                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  73                 u64 eu = end & gru_dist_umask;
  74                 u64 el = end & gru_dist_lmask;
  75
  76                 /* Must reside completely within a single GRU range */
  77                 return (sl == gru_dist_base && el == gru_dist_base &&
  78                         su >= gru_first_node_paddr &&
  79                         su <= gru_last_node_paddr &&
  80                         eu == su);
  81         } else {
  82                 return start >= gru_start_paddr && end <= gru_end_paddr;
  83         }
  84 }
  85
  86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  87 {
  88         return is_ISA_range(start, end) || is_GRU_range(start, end);
  89 }
  90
  91 static int __init early_get_pnodeid(void)
  92 {
  93         union uvh_node_id_u node_id;
  94         union uvh_rh_gam_config_mmr_u  m_n_config;
  95         int pnode;
  96
  97         /* Currently, all blades have same revision number */
  98         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  99         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 100         uv_min_hub_revision_id = node_id.s.revision;
 101
 102         switch (node_id.s.part_number) {
 103         case UV2_HUB_PART_NUMBER:
 104         case UV2_HUB_PART_NUMBER_X:
 105                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 106                 break;
 107         case UV3_HUB_PART_NUMBER:
 108         case UV3_HUB_PART_NUMBER_X:
 109                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 110                 break;
 111         }
 112
 113         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 114         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
 115         return pnode;
 116 }
 117
 118 static void __init early_get_apic_pnode_shift(void)
 119 {
 120         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 121         if (!uvh_apicid.v)
 122                 /*
 123                  * Old bios, use default value
 124                  */
 125                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
 126 }
 127
 128 /*
 129  * Add an extra bit as dictated by bios to the destination apicid of
 130  * interrupts potentially passing through the UV HUB.  This prevents
 131  * a deadlock between interrupts and IO port operations.
 132  */
 133 static void __init uv_set_apicid_hibit(void)
 134 {
 135         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 136
 137         if (is_uv1_hub()) {
 138                 apicid_mask.v =
 139                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 140                 uv_apicid_hibits =
 141                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 142         }
 143 }
 144
 145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 146 {
 147         int pnodeid, is_uv1, is_uv2, is_uv3;
 148
 149         is_uv1 = !strcmp(oem_id, "SGI");
 150         is_uv2 = !strcmp(oem_id, "SGI2");
 151         is_uv3 = !strncmp(oem_id, "SGI3", 4);   /* there are varieties of UV3 */
 152         if (is_uv1 || is_uv2 || is_uv3) {
 153                 uv_hub_info->hub_revision =
 154                         (is_uv1 ? UV1_HUB_REVISION_BASE :
 155                         (is_uv2 ? UV2_HUB_REVISION_BASE :
 156                                   UV3_HUB_REVISION_BASE));
 157                 pnodeid = early_get_pnodeid();
 158                 early_get_apic_pnode_shift();
 159                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 160                 x86_platform.nmi_init = uv_nmi_init;
 161                 if (!strcmp(oem_table_id, "UVL"))
 162                         uv_system_type = UV_LEGACY_APIC;
 163                 else if (!strcmp(oem_table_id, "UVX"))
 164                         uv_system_type = UV_X2APIC;
 165                 else if (!strcmp(oem_table_id, "UVH")) {
 166                         __this_cpu_write(x2apic_extra_bits,
 167                                 pnodeid << uvh_apicid.s.pnode_shift);
 168                         uv_system_type = UV_NON_UNIQUE_APIC;
 169                         uv_set_apicid_hibit();
 170                         return 1;
 171                 }
 172         }
 173         return 0;
 174 }
 175
 176 enum uv_system_type get_uv_system_type(void)
 177 {
 178         return uv_system_type;
 179 }
 180
 181 int is_uv_system(void)
 182 {
 183         return uv_system_type != UV_NONE;
 184 }
 185 EXPORT_SYMBOL_GPL(is_uv_system);
 186
 187 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 188 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 189
 190 struct uv_blade_info *uv_blade_info;
 191 EXPORT_SYMBOL_GPL(uv_blade_info);
 192
 193 short *uv_node_to_blade;
 194 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 195
 196 short *uv_cpu_to_blade;
 197 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 198
 199 short uv_possible_blades;
 200 EXPORT_SYMBOL_GPL(uv_possible_blades);
 201
 202 unsigned long sn_rtc_cycles_per_second;
 203 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 204
 205 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 206 {
 207 #ifdef CONFIG_SMP
 208         unsigned long val;
 209         int pnode;
 210
 211         pnode = uv_apicid_to_pnode(phys_apicid);
 212         phys_apicid |= uv_apicid_hibits;
 213         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 214             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 215             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 216             APIC_DM_INIT;
 217         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 218
 219         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 220             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 221             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 222             APIC_DM_STARTUP;
 223         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 224
 225         atomic_set(&init_deasserted, 1);
 226 #endif
 227         return 0;
 228 }
 229
 230 static void uv_send_IPI_one(int cpu, int vector)
 231 {
 232         unsigned long apicid;
 233         int pnode;
 234
 235         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 236         pnode = uv_apicid_to_pnode(apicid);
 237         uv_hub_send_ipi(pnode, apicid, vector);
 238 }
 239
 240 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 241 {
 242         unsigned int cpu;
 243
 244         for_each_cpu(cpu, mask)
 245                 uv_send_IPI_one(cpu, vector);
 246 }
 247
 248 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 249 {
 250         unsigned int this_cpu = smp_processor_id();
 251         unsigned int cpu;
 252
 253         for_each_cpu(cpu, mask) {
 254                 if (cpu != this_cpu)
 255                         uv_send_IPI_one(cpu, vector);
 256         }
 257 }
 258
 259 static void uv_send_IPI_allbutself(int vector)
 260 {
 261         unsigned int this_cpu = smp_processor_id();
 262         unsigned int cpu;
 263
 264         for_each_online_cpu(cpu) {
 265                 if (cpu != this_cpu)
 266                         uv_send_IPI_one(cpu, vector);
 267         }
 268 }
 269
 270 static void uv_send_IPI_all(int vector)
 271 {
 272         uv_send_IPI_mask(cpu_online_mask, vector);
 273 }
 274
 275 static int uv_apic_id_valid(int apicid)
 276 {
 277         return 1;
 278 }
 279
 280 static int uv_apic_id_registered(void)
 281 {
 282         return 1;
 283 }
 284
 285 static void uv_init_apic_ldr(void)
 286 {
 287 }
 288
 289 static int
 290 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 291                           const struct cpumask *andmask,
 292                           unsigned int *apicid)
 293 {
 294         int unsigned cpu;
 295
 296         /*
 297          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 298          * May as well be the first.
 299          */
 300         for_each_cpu_and(cpu, cpumask, andmask) {
 301                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 302                         break;
 303         }
 304
 305         if (likely(cpu < nr_cpu_ids)) {
 306                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 307                 return 0;
 308         }
 309
 310         return -EINVAL;
 311 }
 312
 313 static unsigned int x2apic_get_apic_id(unsigned long x)
 314 {
 315         unsigned int id;
 316
 317         WARN_ON(preemptible() && num_online_cpus() > 1);
 318         id = x | __this_cpu_read(x2apic_extra_bits);
 319
 320         return id;
 321 }
 322
 323 static unsigned long set_apic_id(unsigned int id)
 324 {
 325         unsigned long x;
 326
 327         /* maskout x2apic_extra_bits ? */
 328         x = id;
 329         return x;
 330 }
 331
 332 static unsigned int uv_read_apic_id(void)
 333 {
 334
 335         return x2apic_get_apic_id(apic_read(APIC_ID));
 336 }
 337
 338 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 339 {
 340         return uv_read_apic_id() >> index_msb;
 341 }
 342
 343 static void uv_send_IPI_self(int vector)
 344 {
 345         apic_write(APIC_SELF_IPI, vector);
 346 }
 347
 348 static int uv_probe(void)
 349 {
 350         return apic == &apic_x2apic_uv_x;
 351 }
 352
 353 static struct apic __refdata apic_x2apic_uv_x = {
 354
 355         .name                           = "UV large system",
 356         .probe                          = uv_probe,
 357         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 358         .apic_id_valid                  = uv_apic_id_valid,
 359         .apic_id_registered             = uv_apic_id_registered,
 360
 361         .irq_delivery_mode              = dest_Fixed,
 362         .irq_dest_mode                  = 0, /* physical */
 363
 364         .target_cpus                    = online_target_cpus,
 365         .disable_esr                    = 0,
 366         .dest_logical                   = APIC_DEST_LOGICAL,
 367         .check_apicid_used              = NULL,
 368
 369         .vector_allocation_domain       = default_vector_allocation_domain,
 370         .init_apic_ldr                  = uv_init_apic_ldr,
 371
 372         .ioapic_phys_id_map             = NULL,
 373         .setup_apic_routing             = NULL,
 374         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 375         .apicid_to_cpu_present          = NULL,
 376         .check_phys_apicid_present      = default_check_phys_apicid_present,
 377         .phys_pkg_id                    = uv_phys_pkg_id,
 378
 379         .get_apic_id                    = x2apic_get_apic_id,
 380         .set_apic_id                    = set_apic_id,
 381         .apic_id_mask                   = 0xFFFFFFFFu,
 382
 383         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 384
 385         .send_IPI_mask                  = uv_send_IPI_mask,
 386         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 387         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 388         .send_IPI_all                   = uv_send_IPI_all,
 389         .send_IPI_self                  = uv_send_IPI_self,
 390
 391         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 392         .wait_for_init_deassert         = false,
 393         .inquire_remote_apic            = NULL,
 394
 395         .read                           = native_apic_msr_read,
 396         .write                          = native_apic_msr_write,
 397         .eoi_write                      = native_apic_msr_eoi_write,
 398         .icr_read                       = native_x2apic_icr_read,
 399         .icr_write                      = native_x2apic_icr_write,
 400         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 401         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 402 };
 403
 404 static void set_x2apic_extra_bits(int pnode)
 405 {
 406         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 407 }
 408
 409 /*
 410  * Called on boot cpu.
 411  */
 412 static __init int boot_pnode_to_blade(int pnode)
 413 {
 414         int blade;
 415
 416         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 417                 if (pnode == uv_blade_info[blade].pnode)
 418                         return blade;
 419         BUG();
 420 }
 421
 422 struct redir_addr {
 423         unsigned long redirect;
 424         unsigned long alias;
 425 };
 426
 427 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 428
 429 static __initdata struct redir_addr redir_addrs[] = {
 430         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
 431         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
 432         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 433 };
 434
 435 static unsigned char get_n_lshift(int m_val)
 436 {
 437         union uv3h_gr0_gam_gr_config_u m_gr_config;
 438
 439         if (is_uv1_hub())
 440                 return m_val;
 441
 442         if (is_uv2_hub())
 443                 return m_val == 40 ? 40 : 39;
 444
 445         m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
 446         return m_gr_config.s3.m_skt;
 447 }
 448
 449 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 450 {
 451         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 452         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 453         int i;
 454
 455         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 456                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 457                 if (alias.s.enable && alias.s.base == 0) {
 458                         *size = (1UL << alias.s.m_alias);
 459                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 460                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 461                         return;
 462                 }
 463         }
 464         *base = *size = 0;
 465 }
 466
 467 enum map_type {map_wb, map_uc};
 468
 469 static __init void map_high(char *id, unsigned long base, int pshift,
 470                         int bshift, int max_pnode, enum map_type map_type)
 471 {
 472         unsigned long bytes, paddr;
 473
 474         paddr = base << pshift;
 475         bytes = (1UL << bshift) * (max_pnode + 1);
 476         if (!paddr) {
 477                 pr_info("UV: Map %s_HI base address NULL\n", id);
 478                 return;
 479         }
 480         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 481         if (map_type == map_uc)
 482                 init_extra_mapping_uc(paddr, bytes);
 483         else
 484                 init_extra_mapping_wb(paddr, bytes);
 485 }
 486
 487 static __init void map_gru_distributed(unsigned long c)
 488 {
 489         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 490         u64 paddr;
 491         unsigned long bytes;
 492         int nid;
 493
 494         gru.v = c;
 495         /* only base bits 42:28 relevant in dist mode */
 496         gru_dist_base = gru.v & 0x000007fff0000000UL;
 497         if (!gru_dist_base) {
 498                 pr_info("UV: Map GRU_DIST base address NULL\n");
 499                 return;
 500         }
 501         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 502         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 503         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 504         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 505         for_each_online_node(nid) {
 506                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 507                                 gru_dist_base;
 508                 init_extra_mapping_wb(paddr, bytes);
 509                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 510                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 511         }
 512         /* Save upper (63:M) bits of address only for is_GRU_range */
 513         gru_first_node_paddr &= gru_dist_umask;
 514         gru_last_node_paddr &= gru_dist_umask;
 515         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 516                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 517 }
 518
 519 static __init void map_gru_high(int max_pnode)
 520 {
 521         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 522         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 523
 524         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 525         if (!gru.s.enable) {
 526                 pr_info("UV: GRU disabled\n");
 527                 return;
 528         }
 529
 530         if (is_uv3_hub() && gru.s3.mode) {
 531                 map_gru_distributed(gru.v);
 532                 return;
 533         }
 534         map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 535         gru_start_paddr = ((u64)gru.s.base << shift);
 536         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 537 }
 538
 539 static __init void map_mmr_high(int max_pnode)
 540 {
 541         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 542         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 543
 544         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 545         if (mmr.s.enable)
 546                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 547         else
 548                 pr_info("UV: MMR disabled\n");
 549 }
 550
 551 /*
 552  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 553  * and REDIRECT MMR regs are exactly the same on UV3.
 554  */
 555 struct mmioh_config {
 556         unsigned long overlay;
 557         unsigned long redirect;
 558         char *id;
 559 };
 560
 561 static __initdata struct mmioh_config mmiohs[] = {
 562         {
 563                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 564                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 565                 "MMIOH0"
 566         },
 567         {
 568                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 569                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 570                 "MMIOH1"
 571         },
 572 };
 573
 574 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 575 {
 576         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 577         unsigned long mmr;
 578         unsigned long base;
 579         int i, n, shift, m_io, max_io;
 580         int nasid, lnasid, fi, li;
 581         char *id;
 582
 583         id = mmiohs[index].id;
 584         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 585         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 586                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 587         if (!overlay.s3.enable) {
 588                 pr_info("UV: %s disabled\n", id);
 589                 return;
 590         }
 591
 592         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 593         base = (unsigned long)overlay.s3.base;
 594         m_io = overlay.s3.m_io;
 595         mmr = mmiohs[index].redirect;
 596         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 597         min_pnode *= 2;                         /* convert to NASID */
 598         max_pnode *= 2;
 599         max_io = lnasid = fi = li = -1;
 600
 601         for (i = 0; i < n; i++) {
 602                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 603
 604                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 605                 nasid = redirect.s3.nasid;
 606                 if (nasid < min_pnode || max_pnode < nasid)
 607                         nasid = -1;             /* invalid NASID */
 608
 609                 if (nasid == lnasid) {
 610                         li = i;
 611                         if (i != n-1)           /* last entry check */
 612                                 continue;
 613                 }
 614
 615                 /* check if we have a cached (or last) redirect to print */
 616                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 617                         unsigned long addr1, addr2;
 618                         int f, l;
 619
 620                         if (lnasid == -1) {
 621                                 f = l = i;
 622                                 lnasid = nasid;
 623                         } else {
 624                                 f = fi;
 625                                 l = li;
 626                         }
 627                         addr1 = (base << shift) +
 628                                 f * (unsigned long)(1 << m_io);
 629                         addr2 = (base << shift) +
 630                                 (l + 1) * (unsigned long)(1 << m_io);
 631                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 632                                 id, fi, li, lnasid, addr1, addr2);
 633                         if (max_io < l)
 634                                 max_io = l;
 635                 }
 636                 fi = li = i;
 637                 lnasid = nasid;
 638         }
 639
 640         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 641                 id, base, shift, m_io, max_io);
 642
 643         if (max_io >= 0)
 644                 map_high(id, base, shift, m_io, max_io, map_uc);
 645 }
 646
 647 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 648 {
 649         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 650         unsigned long mmr, base;
 651         int shift, enable, m_io, n_io;
 652
 653         if (is_uv3_hub()) {
 654                 /* Map both MMIOH Regions */
 655                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 656                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 657                 return;
 658         }
 659
 660         if (is_uv1_hub()) {
 661                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 662                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 663                 mmioh.v = uv_read_local_mmr(mmr);
 664                 enable = !!mmioh.s1.enable;
 665                 base = mmioh.s1.base;
 666                 m_io = mmioh.s1.m_io;
 667                 n_io = mmioh.s1.n_io;
 668         } else if (is_uv2_hub()) {
 669                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 670                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 671                 mmioh.v = uv_read_local_mmr(mmr);
 672                 enable = !!mmioh.s2.enable;
 673                 base = mmioh.s2.base;
 674                 m_io = mmioh.s2.m_io;
 675                 n_io = mmioh.s2.n_io;
 676         } else
 677                 return;
 678
 679         if (enable) {
 680                 max_pnode &= (1 << n_io) - 1;
 681                 pr_info(
 682                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 683                         base, shift, m_io, n_io, max_pnode);
 684                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 685         } else {
 686                 pr_info("UV: MMIOH disabled\n");
 687         }
 688 }
 689
 690 static __init void map_low_mmrs(void)
 691 {
 692         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 693         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 694 }
 695
 696 static __init void uv_rtc_init(void)
 697 {
 698         long status;
 699         u64 ticks_per_sec;
 700
 701         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 702                                         &ticks_per_sec);
 703         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 704                 printk(KERN_WARNING
 705                         "unable to determine platform RTC clock frequency, "
 706                         "guessing.\n");
 707                 /* BIOS gives wrong value for clock freq. so guess */
 708                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 709         } else
 710                 sn_rtc_cycles_per_second = ticks_per_sec;
 711 }
 712
 713 /*
 714  * percpu heartbeat timer
 715  */
 716 static void uv_heartbeat(unsigned long ignored)
 717 {
 718         struct timer_list *timer = &uv_hub_info->scir.timer;
 719         unsigned char bits = uv_hub_info->scir.state;
 720
 721         /* flip heartbeat bit */
 722         bits ^= SCIR_CPU_HEARTBEAT;
 723
 724         /* is this cpu idle? */
 725         if (idle_cpu(raw_smp_processor_id()))
 726                 bits &= ~SCIR_CPU_ACTIVITY;
 727         else
 728                 bits |= SCIR_CPU_ACTIVITY;
 729
 730         /* update system controller interface reg */
 731         uv_set_scir_bits(bits);
 732
 733         /* enable next timer period */
 734         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 735 }
 736
 737 static void uv_heartbeat_enable(int cpu)
 738 {
 739         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 740                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 741
 742                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 743                 setup_timer(timer, uv_heartbeat, cpu);
 744                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 745                 add_timer_on(timer, cpu);
 746                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 747
 748                 /* also ensure that boot cpu is enabled */
 749                 cpu = 0;
 750         }
 751 }
 752
 753 #ifdef CONFIG_HOTPLUG_CPU
 754 static void uv_heartbeat_disable(int cpu)
 755 {
 756         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 757                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 758                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 759         }
 760         uv_set_cpu_scir_bits(cpu, 0xff);
 761 }
 762
 763 /*
 764  * cpu hotplug notifier
 765  */
 766 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
 767                               void *hcpu)
 768 {
 769         long cpu = (long)hcpu;
 770
 771         switch (action) {
 772         case CPU_ONLINE:
 773                 uv_heartbeat_enable(cpu);
 774                 break;
 775         case CPU_DOWN_PREPARE:
 776                 uv_heartbeat_disable(cpu);
 777                 break;
 778         default:
 779                 break;
 780         }
 781         return NOTIFY_OK;
 782 }
 783
 784 static __init void uv_scir_register_cpu_notifier(void)
 785 {
 786         hotcpu_notifier(uv_scir_cpu_notify, 0);
 787 }
 788
 789 #else /* !CONFIG_HOTPLUG_CPU */
 790
 791 static __init void uv_scir_register_cpu_notifier(void)
 792 {
 793 }
 794
 795 static __init int uv_init_heartbeat(void)
 796 {
 797         int cpu;
 798
 799         if (is_uv_system())
 800                 for_each_online_cpu(cpu)
 801                         uv_heartbeat_enable(cpu);
 802         return 0;
 803 }
 804
 805 late_initcall(uv_init_heartbeat);
 806
 807 #endif /* !CONFIG_HOTPLUG_CPU */
 808
 809 /* Direct Legacy VGA I/O traffic to designated IOH */
 810 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 811                       unsigned int command_bits, u32 flags)
 812 {
 813         int domain, bus, rc;
 814
 815         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
 816                         pdev->devfn, decode, command_bits, flags);
 817
 818         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 819                 return 0;
 820
 821         if ((command_bits & PCI_COMMAND_IO) == 0)
 822                 return 0;
 823
 824         domain = pci_domain_nr(pdev->bus);
 825         bus = pdev->bus->number;
 826
 827         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 828         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 829
 830         return rc;
 831 }
 832
 833 /*
 834  * Called on each cpu to initialize the per_cpu UV data area.
 835  * FIXME: hotplug not supported yet
 836  */
 837 void uv_cpu_init(void)
 838 {
 839         /* CPU 0 initilization will be done via uv_system_init. */
 840         if (!uv_blade_info)
 841                 return;
 842
 843         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 844
 845         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 846                 set_x2apic_extra_bits(uv_hub_info->pnode);
 847 }
 848
 849 void __init uv_system_init(void)
 850 {
 851         union uvh_rh_gam_config_mmr_u  m_n_config;
 852         union uvh_node_id_u node_id;
 853         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 854         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 855         int gnode_extra, min_pnode = 999999, max_pnode = -1;
 856         unsigned long mmr_base, present, paddr;
 857         unsigned short pnode_mask;
 858         unsigned char n_lshift;
 859         char *hub = (is_uv1_hub() ? "UV1" :
 860                     (is_uv2_hub() ? "UV2" :
 861                                     "UV3"));
 862
 863         pr_info("UV: Found %s hub\n", hub);
 864         map_low_mmrs();
 865
 866         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
 867         m_val = m_n_config.s.m_skt;
 868         n_val = m_n_config.s.n_skt;
 869         pnode_mask = (1 << n_val) - 1;
 870         n_lshift = get_n_lshift(m_val);
 871         mmr_base =
 872             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 873             ~UV_MMR_ENABLE;
 874
 875         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 876         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 877         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 878         pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
 879                         n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
 880                         n_lshift);
 881
 882         pr_info("UV: global MMR base 0x%lx\n", mmr_base);
 883
 884         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 885                 uv_possible_blades +=
 886                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 887
 888         /* uv_num_possible_blades() is really the hub count */
 889         pr_info("UV: Found %d blades, %d hubs\n",
 890                         is_uv1_hub() ? uv_num_possible_blades() :
 891                         (uv_num_possible_blades() + 1) / 2,
 892                         uv_num_possible_blades());
 893
 894         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 895         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
 896         BUG_ON(!uv_blade_info);
 897
 898         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 899                 uv_blade_info[blade].memory_nid = -1;
 900
 901         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 902
 903         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 904         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 905         BUG_ON(!uv_node_to_blade);
 906         memset(uv_node_to_blade, 255, bytes);
 907
 908         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 909         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 910         BUG_ON(!uv_cpu_to_blade);
 911         memset(uv_cpu_to_blade, 255, bytes);
 912
 913         blade = 0;
 914         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 915                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 916                 for (j = 0; j < 64; j++) {
 917                         if (!test_bit(j, &present))
 918                                 continue;
 919                         pnode = (i * 64 + j) & pnode_mask;
 920                         uv_blade_info[blade].pnode = pnode;
 921                         uv_blade_info[blade].nr_possible_cpus = 0;
 922                         uv_blade_info[blade].nr_online_cpus = 0;
 923                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
 924                         min_pnode = min(pnode, min_pnode);
 925                         max_pnode = max(pnode, max_pnode);
 926                         blade++;
 927                 }
 928         }
 929
 930         uv_bios_init();
 931         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 932                             &sn_region_size, &system_serial_number);
 933         uv_rtc_init();
 934
 935         for_each_present_cpu(cpu) {
 936                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 937
 938                 nid = cpu_to_node(cpu);
 939                 /*
 940                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 941                  */
 942                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 943                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 944                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
 945
 946                 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
 947                 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
 948
 949                 pnode = uv_apicid_to_pnode(apicid);
 950                 blade = boot_pnode_to_blade(pnode);
 951                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 952                 uv_blade_info[blade].nr_possible_cpus++;
 953
 954                 /* Any node on the blade, else will contain -1. */
 955                 uv_blade_info[blade].memory_nid = nid;
 956
 957                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 958                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 959                 uv_cpu_hub_info(cpu)->m_val = m_val;
 960                 uv_cpu_hub_info(cpu)->n_val = n_val;
 961                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 962                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 963                 uv_cpu_hub_info(cpu)->pnode = pnode;
 964                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 965                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 966                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 967                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 968                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 969                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 970                 uv_node_to_blade[nid] = blade;
 971                 uv_cpu_to_blade[cpu] = blade;
 972         }
 973
 974         /* Add blade/pnode info for nodes without cpus */
 975         for_each_online_node(nid) {
 976                 if (uv_node_to_blade[nid] >= 0)
 977                         continue;
 978                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 979                 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
 980                 blade = boot_pnode_to_blade(pnode);
 981                 uv_node_to_blade[nid] = blade;
 982         }
 983
 984         map_gru_high(max_pnode);
 985         map_mmr_high(max_pnode);
 986         map_mmioh_high(min_pnode, max_pnode);
 987
 988         uv_nmi_setup();
 989         uv_cpu_init();
 990         uv_scir_register_cpu_notifier();
 991         proc_mkdir("sgi_uv", NULL);
 992
 993         /* register Legacy VGA I/O redirection handler */
 994         pci_register_set_vga_state(uv_set_vga_state);
 995
 996         /*
 997          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
 998          * EFI is not enabled in the kdump kernel.
 999          */
1000         if (is_kdump_kernel())
1001                 reboot_type = BOOT_ACPI;
1002 }
1003
1004 apic_driver(apic_x2apic_uv_x);