1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
44 #include <asm/microcode.h>
45 #include <asm/microcode_intel.h>
47 #ifdef CONFIG_X86_LOCAL_APIC
48 #include <asm/uv/uv.h>
53 /* all of these masks are initialized in setup_cpu_local_masks() */
54 cpumask_var_t cpu_initialized_mask;
55 cpumask_var_t cpu_callout_mask;
56 cpumask_var_t cpu_callin_mask;
58 /* representing cpus for which sibling maps can be computed */
59 cpumask_var_t cpu_sibling_setup_mask;
61 /* correctly size the local cpu masks */
62 void __init setup_cpu_local_masks(void)
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
70 static void default_init(struct cpuinfo_x86 *c)
73 cpu_detect_cache_sizes(c);
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
80 strcpy(c->x86_model_id, "486");
82 strcpy(c->x86_model_id, "386");
87 static const struct cpu_dev default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
93 static const struct cpu_dev *this_cpu = &default_cpu;
95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
149 static int __init x86_mpx_setup(char *s)
151 /* require an exact match without trailing characters */
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX))
159 setup_clear_cpu_cap(X86_FEATURE_MPX);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
163 __setup("nompx", x86_mpx_setup);
165 static int __init x86_noinvpcid_setup(char *s)
167 /* noinvpcid doesn't accept parameters */
171 /* do not emit a message if the feature is not present */
172 if (!boot_cpu_has(X86_FEATURE_INVPCID))
175 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
176 pr_info("noinvpcid: INVPCID feature disabled\n");
179 early_param("noinvpcid", x86_noinvpcid_setup);
182 static int cachesize_override = -1;
183 static int disable_x86_serial_nr = 1;
185 static int __init cachesize_setup(char *str)
187 get_option(&str, &cachesize_override);
190 __setup("cachesize=", cachesize_setup);
192 static int __init x86_sep_setup(char *s)
194 setup_clear_cpu_cap(X86_FEATURE_SEP);
197 __setup("nosep", x86_sep_setup);
199 /* Standard macro to see if a specific flag is changeable */
200 static inline int flag_is_changeable_p(u32 flag)
205 * Cyrix and IDT cpus allow disabling of CPUID
206 * so the code below may return different results
207 * when it is executed before and after enabling
208 * the CPUID. Add "volatile" to not allow gcc to
209 * optimize the subsequent calls to this function.
211 asm volatile ("pushfl \n\t"
222 : "=&r" (f1), "=&r" (f2)
225 return ((f1^f2) & flag) != 0;
228 /* Probe for the CPUID instruction */
229 int have_cpuid_p(void)
231 return flag_is_changeable_p(X86_EFLAGS_ID);
234 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
236 unsigned long lo, hi;
238 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
241 /* Disable processor serial number: */
243 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
245 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247 printk(KERN_NOTICE "CPU serial number disabled.\n");
248 clear_cpu_cap(c, X86_FEATURE_PN);
250 /* Disabling the serial number may affect the cpuid level */
251 c->cpuid_level = cpuid_eax(0);
254 static int __init x86_serial_nr_setup(char *s)
256 disable_x86_serial_nr = 0;
259 __setup("serialnumber", x86_serial_nr_setup);
261 static inline int flag_is_changeable_p(u32 flag)
265 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
270 static __init int setup_disable_smep(char *arg)
272 setup_clear_cpu_cap(X86_FEATURE_SMEP);
275 __setup("nosmep", setup_disable_smep);
277 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
279 if (cpu_has(c, X86_FEATURE_SMEP))
280 cr4_set_bits(X86_CR4_SMEP);
283 static __init int setup_disable_smap(char *arg)
285 setup_clear_cpu_cap(X86_FEATURE_SMAP);
288 __setup("nosmap", setup_disable_smap);
290 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
292 unsigned long eflags = native_save_fl();
294 /* This should have been cleared long ago */
295 BUG_ON(eflags & X86_EFLAGS_AC);
297 if (cpu_has(c, X86_FEATURE_SMAP)) {
298 #ifdef CONFIG_X86_SMAP
299 cr4_set_bits(X86_CR4_SMAP);
301 cr4_clear_bits(X86_CR4_SMAP);
307 * Protection Keys are not available in 32-bit mode.
309 static bool pku_disabled;
311 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
313 if (!cpu_has(c, X86_FEATURE_PKU))
318 cr4_set_bits(X86_CR4_PKE);
320 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
321 * cpuid bit to be set. We need to ensure that we
322 * update that bit in this CPU's "cpu_info".
327 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
328 static __init int setup_disable_pku(char *arg)
331 * Do not clear the X86_FEATURE_PKU bit. All of the
332 * runtime checks are against OSPKE so clearing the
335 * This way, we will see "pku" in cpuinfo, but not
336 * "ospke", which is exactly what we want. It shows
337 * that the CPU has PKU, but the OS has not enabled it.
338 * This happens to be exactly how a system would look
339 * if we disabled the config option.
341 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
345 __setup("nopku", setup_disable_pku);
346 #endif /* CONFIG_X86_64 */
349 * Some CPU features depend on higher CPUID levels, which may not always
350 * be available due to CPUID level capping or broken virtualization
351 * software. Add those features to this table to auto-disable them.
353 struct cpuid_dependent_feature {
358 static const struct cpuid_dependent_feature
359 cpuid_dependent_features[] = {
360 { X86_FEATURE_MWAIT, 0x00000005 },
361 { X86_FEATURE_DCA, 0x00000009 },
362 { X86_FEATURE_XSAVE, 0x0000000d },
366 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
368 const struct cpuid_dependent_feature *df;
370 for (df = cpuid_dependent_features; df->feature; df++) {
372 if (!cpu_has(c, df->feature))
375 * Note: cpuid_level is set to -1 if unavailable, but
376 * extended_extended_level is set to 0 if unavailable
377 * and the legitimate extended levels are all negative
378 * when signed; hence the weird messing around with
381 if (!((s32)df->level < 0 ?
382 (u32)df->level > (u32)c->extended_cpuid_level :
383 (s32)df->level > (s32)c->cpuid_level))
386 clear_cpu_cap(c, df->feature);
391 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
392 x86_cap_flag(df->feature), df->level);
397 * Naming convention should be: <Name> [(<Codename>)]
398 * This table only is used unless init_<vendor>() below doesn't set it;
399 * in particular, if CPUID levels 0x80000002..4 are supported, this
403 /* Look up CPU names by table lookup. */
404 static const char *table_lookup_model(struct cpuinfo_x86 *c)
407 const struct legacy_cpu_model_info *info;
409 if (c->x86_model >= 16)
410 return NULL; /* Range check */
415 info = this_cpu->legacy_models;
417 while (info->family) {
418 if (info->family == c->x86)
419 return info->model_names[c->x86_model];
423 return NULL; /* Not found */
426 __u32 cpu_caps_cleared[NCAPINTS];
427 __u32 cpu_caps_set[NCAPINTS];
429 void load_percpu_segment(int cpu)
432 loadsegment(fs, __KERNEL_PERCPU);
435 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
437 load_stack_canary_segment();
441 * Current gdt points %fs at the "master" per-cpu area: after this,
442 * it's on the real one.
444 void switch_to_new_gdt(int cpu)
446 struct desc_ptr gdt_descr;
448 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
449 gdt_descr.size = GDT_SIZE - 1;
450 load_gdt(&gdt_descr);
451 /* Reload the per-cpu base */
453 load_percpu_segment(cpu);
456 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
458 static void get_model_name(struct cpuinfo_x86 *c)
463 if (c->extended_cpuid_level < 0x80000004)
466 v = (unsigned int *)c->x86_model_id;
467 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
468 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
469 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
470 c->x86_model_id[48] = 0;
472 /* Trim whitespace */
473 p = q = s = &c->x86_model_id[0];
479 /* Note the last non-whitespace index */
489 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
491 unsigned int n, dummy, ebx, ecx, edx, l2size;
493 n = c->extended_cpuid_level;
495 if (n >= 0x80000005) {
496 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
497 c->x86_cache_size = (ecx>>24) + (edx>>24);
499 /* On K8 L1 TLB is inclusive, so don't count it */
504 if (n < 0x80000006) /* Some chips just has a large L1. */
507 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
511 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
513 /* do processor-specific cache resizing */
514 if (this_cpu->legacy_cache_size)
515 l2size = this_cpu->legacy_cache_size(c, l2size);
517 /* Allow user to override all this if necessary. */
518 if (cachesize_override != -1)
519 l2size = cachesize_override;
522 return; /* Again, no L2 cache is possible */
525 c->x86_cache_size = l2size;
528 u16 __read_mostly tlb_lli_4k[NR_INFO];
529 u16 __read_mostly tlb_lli_2m[NR_INFO];
530 u16 __read_mostly tlb_lli_4m[NR_INFO];
531 u16 __read_mostly tlb_lld_4k[NR_INFO];
532 u16 __read_mostly tlb_lld_2m[NR_INFO];
533 u16 __read_mostly tlb_lld_4m[NR_INFO];
534 u16 __read_mostly tlb_lld_1g[NR_INFO];
536 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
538 if (this_cpu->c_detect_tlb)
539 this_cpu->c_detect_tlb(c);
541 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
542 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
543 tlb_lli_4m[ENTRIES]);
545 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
546 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
547 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
550 void detect_ht(struct cpuinfo_x86 *c)
553 u32 eax, ebx, ecx, edx;
554 int index_msb, core_bits;
557 if (!cpu_has(c, X86_FEATURE_HT))
560 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
563 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
566 cpuid(1, &eax, &ebx, &ecx, &edx);
568 smp_num_siblings = (ebx & 0xff0000) >> 16;
570 if (smp_num_siblings == 1) {
571 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
575 if (smp_num_siblings <= 1)
578 index_msb = get_count_order(smp_num_siblings);
579 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
581 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
583 index_msb = get_count_order(smp_num_siblings);
585 core_bits = get_count_order(c->x86_max_cores);
587 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
588 ((1 << core_bits) - 1);
591 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
592 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
594 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
601 static void get_cpu_vendor(struct cpuinfo_x86 *c)
603 char *v = c->x86_vendor_id;
606 for (i = 0; i < X86_VENDOR_NUM; i++) {
610 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
611 (cpu_devs[i]->c_ident[1] &&
612 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
614 this_cpu = cpu_devs[i];
615 c->x86_vendor = this_cpu->c_x86_vendor;
621 "CPU: vendor_id '%s' unknown, using generic init.\n" \
622 "CPU: Your system may be unstable.\n", v);
624 c->x86_vendor = X86_VENDOR_UNKNOWN;
625 this_cpu = &default_cpu;
628 void cpu_detect(struct cpuinfo_x86 *c)
630 /* Get vendor name */
631 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
632 (unsigned int *)&c->x86_vendor_id[0],
633 (unsigned int *)&c->x86_vendor_id[8],
634 (unsigned int *)&c->x86_vendor_id[4]);
637 /* Intel-defined flags: level 0x00000001 */
638 if (c->cpuid_level >= 0x00000001) {
639 u32 junk, tfms, cap0, misc;
641 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
642 c->x86 = x86_family(tfms);
643 c->x86_model = x86_model(tfms);
644 c->x86_mask = x86_stepping(tfms);
646 if (cap0 & (1<<19)) {
647 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
648 c->x86_cache_alignment = c->x86_clflush_size;
653 void get_cpu_cap(struct cpuinfo_x86 *c)
655 u32 eax, ebx, ecx, edx;
657 /* Intel-defined flags: level 0x00000001 */
658 if (c->cpuid_level >= 0x00000001) {
659 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
661 c->x86_capability[CPUID_1_ECX] = ecx;
662 c->x86_capability[CPUID_1_EDX] = edx;
665 /* Additional Intel-defined flags: level 0x00000007 */
666 if (c->cpuid_level >= 0x00000007) {
667 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
669 c->x86_capability[CPUID_7_0_EBX] = ebx;
671 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
672 c->x86_capability[CPUID_7_ECX] = ecx;
675 /* Extended state features: level 0x0000000d */
676 if (c->cpuid_level >= 0x0000000d) {
677 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
679 c->x86_capability[CPUID_D_1_EAX] = eax;
682 /* Additional Intel-defined flags: level 0x0000000F */
683 if (c->cpuid_level >= 0x0000000F) {
685 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
686 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
687 c->x86_capability[CPUID_F_0_EDX] = edx;
689 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
690 /* will be overridden if occupancy monitoring exists */
691 c->x86_cache_max_rmid = ebx;
693 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
694 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
695 c->x86_capability[CPUID_F_1_EDX] = edx;
697 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
698 c->x86_cache_max_rmid = ecx;
699 c->x86_cache_occ_scale = ebx;
702 c->x86_cache_max_rmid = -1;
703 c->x86_cache_occ_scale = -1;
707 /* AMD-defined flags: level 0x80000001 */
708 eax = cpuid_eax(0x80000000);
709 c->extended_cpuid_level = eax;
711 if ((eax & 0xffff0000) == 0x80000000) {
712 if (eax >= 0x80000001) {
713 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
715 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
716 c->x86_capability[CPUID_8000_0001_EDX] = edx;
720 if (c->extended_cpuid_level >= 0x80000008) {
721 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
723 c->x86_virt_bits = (eax >> 8) & 0xff;
724 c->x86_phys_bits = eax & 0xff;
725 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
728 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
729 c->x86_phys_bits = 36;
732 if (c->extended_cpuid_level >= 0x80000007)
733 c->x86_power = cpuid_edx(0x80000007);
735 if (c->extended_cpuid_level >= 0x8000000a)
736 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
738 init_scattered_cpuid_features(c);
741 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
747 * First of all, decide if this is a 486 or higher
748 * It's a 486 if we can modify the AC flag
750 if (flag_is_changeable_p(X86_EFLAGS_AC))
755 for (i = 0; i < X86_VENDOR_NUM; i++)
756 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
757 c->x86_vendor_id[0] = 0;
758 cpu_devs[i]->c_identify(c);
759 if (c->x86_vendor_id[0]) {
768 * Do minimum CPU detection early.
769 * Fields really needed: vendor, cpuid_level, family, model, mask,
771 * The others are not touched to avoid unwanted side effects.
773 * WARNING: this function is only called on the BP. Don't add code here
774 * that is supposed to run on all CPUs.
776 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
779 c->x86_clflush_size = 64;
780 c->x86_phys_bits = 36;
781 c->x86_virt_bits = 48;
783 c->x86_clflush_size = 32;
784 c->x86_phys_bits = 32;
785 c->x86_virt_bits = 32;
787 c->x86_cache_alignment = c->x86_clflush_size;
789 memset(&c->x86_capability, 0, sizeof c->x86_capability);
790 c->extended_cpuid_level = 0;
793 identify_cpu_without_cpuid(c);
795 /* cyrix could have cpuid enabled via c_identify()*/
803 if (this_cpu->c_early_init)
804 this_cpu->c_early_init(c);
807 filter_cpuid_features(c, false);
809 if (this_cpu->c_bsp_init)
810 this_cpu->c_bsp_init(c);
812 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
816 void __init early_cpu_init(void)
818 const struct cpu_dev *const *cdev;
821 #ifdef CONFIG_PROCESSOR_SELECT
822 printk(KERN_INFO "KERNEL supported cpus:\n");
825 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
826 const struct cpu_dev *cpudev = *cdev;
828 if (count >= X86_VENDOR_NUM)
830 cpu_devs[count] = cpudev;
833 #ifdef CONFIG_PROCESSOR_SELECT
837 for (j = 0; j < 2; j++) {
838 if (!cpudev->c_ident[j])
840 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
846 early_identify_cpu(&boot_cpu_data);
850 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
851 * unfortunately, that's not true in practice because of early VIA
852 * chips and (more importantly) broken virtualizers that are not easy
853 * to detect. In the latter case it doesn't even *fail* reliably, so
854 * probing for it doesn't even work. Disable it completely on 32-bit
855 * unless we can find a reliable way to detect all the broken cases.
856 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
858 static void detect_nopl(struct cpuinfo_x86 *c)
861 clear_cpu_cap(c, X86_FEATURE_NOPL);
863 set_cpu_cap(c, X86_FEATURE_NOPL);
867 static void generic_identify(struct cpuinfo_x86 *c)
869 c->extended_cpuid_level = 0;
872 identify_cpu_without_cpuid(c);
874 /* cyrix could have cpuid enabled via c_identify()*/
884 if (c->cpuid_level >= 0x00000001) {
885 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
888 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
890 c->apicid = c->initial_apicid;
893 c->phys_proc_id = c->initial_apicid;
896 get_model_name(c); /* Default name */
901 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
904 * The heavy lifting of max_rmid and cache_occ_scale are handled
905 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
906 * in case CQM bits really aren't there in this CPU.
908 if (c != &boot_cpu_data) {
909 boot_cpu_data.x86_cache_max_rmid =
910 min(boot_cpu_data.x86_cache_max_rmid,
911 c->x86_cache_max_rmid);
916 * This does the hard work of actually picking apart the CPU stuff...
918 static void identify_cpu(struct cpuinfo_x86 *c)
922 c->loops_per_jiffy = loops_per_jiffy;
923 c->x86_cache_size = -1;
924 c->x86_vendor = X86_VENDOR_UNKNOWN;
925 c->x86_model = c->x86_mask = 0; /* So far unknown... */
926 c->x86_vendor_id[0] = '\0'; /* Unset */
927 c->x86_model_id[0] = '\0'; /* Unset */
928 c->x86_max_cores = 1;
929 c->x86_coreid_bits = 0;
931 c->x86_clflush_size = 64;
932 c->x86_phys_bits = 36;
933 c->x86_virt_bits = 48;
935 c->cpuid_level = -1; /* CPUID not detected */
936 c->x86_clflush_size = 32;
937 c->x86_phys_bits = 32;
938 c->x86_virt_bits = 32;
940 c->x86_cache_alignment = c->x86_clflush_size;
941 memset(&c->x86_capability, 0, sizeof c->x86_capability);
945 if (this_cpu->c_identify)
946 this_cpu->c_identify(c);
948 /* Clear/Set all flags overriden by options, after probe */
949 for (i = 0; i < NCAPINTS; i++) {
950 c->x86_capability[i] &= ~cpu_caps_cleared[i];
951 c->x86_capability[i] |= cpu_caps_set[i];
955 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
959 * Vendor-specific initialization. In this section we
960 * canonicalize the feature flags, meaning if there are
961 * features a certain CPU supports which CPUID doesn't
962 * tell us, CPUID claiming incorrect flags, or other bugs,
963 * we handle them here.
965 * At the end of this section, c->x86_capability better
966 * indicate the features this CPU genuinely supports!
968 if (this_cpu->c_init)
971 /* Disable the PN if appropriate */
972 squash_the_stupid_serial_number(c);
974 /* Set up SMEP/SMAP */
979 * The vendor-specific functions might have changed features.
980 * Now we do "generic changes."
983 /* Filter out anything that depends on CPUID levels we don't have */
984 filter_cpuid_features(c, true);
986 /* If the model name is still unset, do table lookup. */
987 if (!c->x86_model_id[0]) {
989 p = table_lookup_model(c);
991 strcpy(c->x86_model_id, p);
994 sprintf(c->x86_model_id, "%02x/%02x",
995 c->x86, c->x86_model);
1004 x86_init_cache_qos(c);
1008 * Clear/Set all flags overriden by options, need do it
1009 * before following smp all cpus cap AND.
1011 for (i = 0; i < NCAPINTS; i++) {
1012 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1013 c->x86_capability[i] |= cpu_caps_set[i];
1017 * On SMP, boot_cpu_data holds the common feature set between
1018 * all CPUs; so make sure that we indicate which features are
1019 * common between the CPUs. The first time this routine gets
1020 * executed, c == &boot_cpu_data.
1022 if (c != &boot_cpu_data) {
1023 /* AND the already accumulated flags with these */
1024 for (i = 0; i < NCAPINTS; i++)
1025 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1027 /* OR, i.e. replicate the bug flags */
1028 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1029 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1032 /* Init Machine Check Exception if available. */
1035 select_idle_routine(c);
1038 numa_add_cpu(smp_processor_id());
1043 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1044 * on 32-bit kernels:
1046 #ifdef CONFIG_X86_32
1047 void enable_sep_cpu(void)
1049 struct tss_struct *tss;
1053 tss = &per_cpu(cpu_tss, cpu);
1055 if (!boot_cpu_has(X86_FEATURE_SEP))
1059 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1060 * see the big comment in struct x86_hw_tss's definition.
1063 tss->x86_tss.ss1 = __KERNEL_CS;
1064 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1066 wrmsr(MSR_IA32_SYSENTER_ESP,
1067 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1070 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1077 void __init identify_boot_cpu(void)
1079 identify_cpu(&boot_cpu_data);
1080 init_amd_e400_c1e_mask();
1081 #ifdef CONFIG_X86_32
1085 cpu_detect_tlb(&boot_cpu_data);
1088 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1090 BUG_ON(c == &boot_cpu_data);
1092 #ifdef CONFIG_X86_32
1103 static const struct msr_range msr_range_array[] = {
1104 { 0x00000000, 0x00000418},
1105 { 0xc0000000, 0xc000040b},
1106 { 0xc0010000, 0xc0010142},
1107 { 0xc0011000, 0xc001103b},
1110 static void __print_cpu_msr(void)
1112 unsigned index_min, index_max;
1117 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1118 index_min = msr_range_array[i].min;
1119 index_max = msr_range_array[i].max;
1121 for (index = index_min; index < index_max; index++) {
1122 if (rdmsrl_safe(index, &val))
1124 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1129 static int show_msr;
1131 static __init int setup_show_msr(char *arg)
1135 get_option(&arg, &num);
1141 __setup("show_msr=", setup_show_msr);
1143 static __init int setup_noclflush(char *arg)
1145 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1146 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1149 __setup("noclflush", setup_noclflush);
1151 void print_cpu_info(struct cpuinfo_x86 *c)
1153 const char *vendor = NULL;
1155 if (c->x86_vendor < X86_VENDOR_NUM) {
1156 vendor = this_cpu->c_vendor;
1158 if (c->cpuid_level >= 0)
1159 vendor = c->x86_vendor_id;
1162 if (vendor && !strstr(c->x86_model_id, vendor))
1163 printk(KERN_CONT "%s ", vendor);
1165 if (c->x86_model_id[0])
1166 printk(KERN_CONT "%s", c->x86_model_id);
1168 printk(KERN_CONT "%d86", c->x86);
1170 printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1172 if (c->x86_mask || c->cpuid_level >= 0)
1173 printk(KERN_CONT ", stepping: 0x%x)\n", c->x86_mask);
1175 printk(KERN_CONT ")\n");
1180 void print_cpu_msr(struct cpuinfo_x86 *c)
1182 if (c->cpu_index < show_msr)
1186 static __init int setup_disablecpuid(char *arg)
1190 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1191 setup_clear_cpu_cap(bit);
1197 __setup("clearcpuid=", setup_disablecpuid);
1199 #ifdef CONFIG_X86_64
1200 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1201 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1202 (unsigned long) debug_idt_table };
1204 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1205 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1208 * The following percpu variables are hot. Align current_task to
1209 * cacheline size such that they fall in the same cacheline.
1211 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1213 EXPORT_PER_CPU_SYMBOL(current_task);
1215 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1216 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1218 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1220 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1221 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1224 * Special IST stacks which the CPU switches to when it calls
1225 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1226 * limit), all of them are 4K, except the debug stack which
1229 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1230 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1231 [DEBUG_STACK - 1] = DEBUG_STKSZ
1234 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1235 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1237 /* May not be marked __init: used by software suspend */
1238 void syscall_init(void)
1241 * LSTAR and STAR live in a bit strange symbiosis.
1242 * They both write to the same internal register. STAR allows to
1243 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1245 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1246 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1248 #ifdef CONFIG_IA32_EMULATION
1249 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1251 * This only works on Intel CPUs.
1252 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1253 * This does not cause SYSENTER to jump to the wrong location, because
1254 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1256 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1257 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1258 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1260 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1261 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1262 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1263 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1266 /* Flags to clear on syscall */
1267 wrmsrl(MSR_SYSCALL_MASK,
1268 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1269 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1273 * Copies of the original ist values from the tss are only accessed during
1274 * debugging, no special alignment required.
1276 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1278 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1279 DEFINE_PER_CPU(int, debug_stack_usage);
1281 int is_debug_stack(unsigned long addr)
1283 return __this_cpu_read(debug_stack_usage) ||
1284 (addr <= __this_cpu_read(debug_stack_addr) &&
1285 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1287 NOKPROBE_SYMBOL(is_debug_stack);
1289 DEFINE_PER_CPU(u32, debug_idt_ctr);
1291 void debug_stack_set_zero(void)
1293 this_cpu_inc(debug_idt_ctr);
1296 NOKPROBE_SYMBOL(debug_stack_set_zero);
1298 void debug_stack_reset(void)
1300 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1302 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1305 NOKPROBE_SYMBOL(debug_stack_reset);
1307 #else /* CONFIG_X86_64 */
1309 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1310 EXPORT_PER_CPU_SYMBOL(current_task);
1311 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1312 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1315 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1316 * the top of the kernel stack. Use an extra percpu variable to track the
1317 * top of the kernel stack directly.
1319 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1320 (unsigned long)&init_thread_union + THREAD_SIZE;
1321 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1323 #ifdef CONFIG_CC_STACKPROTECTOR
1324 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1327 #endif /* CONFIG_X86_64 */
1330 * Clear all 6 debug registers:
1332 static void clear_all_debug_regs(void)
1336 for (i = 0; i < 8; i++) {
1337 /* Ignore db4, db5 */
1338 if ((i == 4) || (i == 5))
1347 * Restore debug regs if using kgdbwait and you have a kernel debugger
1348 * connection established.
1350 static void dbg_restore_debug_regs(void)
1352 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1353 arch_kgdb_ops.correct_hw_break();
1355 #else /* ! CONFIG_KGDB */
1356 #define dbg_restore_debug_regs()
1357 #endif /* ! CONFIG_KGDB */
1359 static void wait_for_master_cpu(int cpu)
1363 * wait for ACK from master CPU before continuing
1364 * with AP initialization
1366 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1367 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1373 * cpu_init() initializes state that is per-CPU. Some data is already
1374 * initialized (naturally) in the bootstrap process, such as the GDT
1375 * and IDT. We reload them nevertheless, this function acts as a
1376 * 'CPU state barrier', nothing should get across.
1377 * A lot of state is already set up in PDA init for 64 bit
1379 #ifdef CONFIG_X86_64
1383 struct orig_ist *oist;
1384 struct task_struct *me;
1385 struct tss_struct *t;
1387 int cpu = stack_smp_processor_id();
1390 wait_for_master_cpu(cpu);
1393 * Initialize the CR4 shadow before doing anything that could
1399 * Load microcode on this cpu if a valid microcode is available.
1400 * This is early microcode loading procedure.
1404 t = &per_cpu(cpu_tss, cpu);
1405 oist = &per_cpu(orig_ist, cpu);
1408 if (this_cpu_read(numa_node) == 0 &&
1409 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1410 set_numa_node(early_cpu_to_node(cpu));
1415 pr_debug("Initializing CPU#%d\n", cpu);
1417 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1420 * Initialize the per-CPU GDT with the boot GDT,
1421 * and set up the GDT descriptor:
1424 switch_to_new_gdt(cpu);
1429 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1432 wrmsrl(MSR_FS_BASE, 0);
1433 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1440 * set up and load the per-CPU TSS
1442 if (!oist->ist[0]) {
1443 char *estacks = per_cpu(exception_stacks, cpu);
1445 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1446 estacks += exception_stack_sizes[v];
1447 oist->ist[v] = t->x86_tss.ist[v] =
1448 (unsigned long)estacks;
1449 if (v == DEBUG_STACK-1)
1450 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1454 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1457 * <= is required because the CPU will access up to
1458 * 8 bits beyond the end of the IO permission bitmap.
1460 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1461 t->io_bitmap[i] = ~0UL;
1463 atomic_inc(&init_mm.mm_count);
1464 me->active_mm = &init_mm;
1466 enter_lazy_tlb(&init_mm, me);
1468 load_sp0(t, ¤t->thread);
1469 set_tss_desc(cpu, t);
1471 load_mm_ldt(&init_mm);
1473 clear_all_debug_regs();
1474 dbg_restore_debug_regs();
1486 int cpu = smp_processor_id();
1487 struct task_struct *curr = current;
1488 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1489 struct thread_struct *thread = &curr->thread;
1491 wait_for_master_cpu(cpu);
1494 * Initialize the CR4 shadow before doing anything that could
1499 show_ucode_info_early();
1501 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1503 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1505 boot_cpu_has(X86_FEATURE_DE))
1506 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1509 switch_to_new_gdt(cpu);
1512 * Set up and load the per-CPU TSS and LDT
1514 atomic_inc(&init_mm.mm_count);
1515 curr->active_mm = &init_mm;
1517 enter_lazy_tlb(&init_mm, curr);
1519 load_sp0(t, thread);
1520 set_tss_desc(cpu, t);
1522 load_mm_ldt(&init_mm);
1524 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1526 #ifdef CONFIG_DOUBLEFAULT
1527 /* Set up doublefault TSS pointer in the GDT */
1528 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1531 clear_all_debug_regs();
1532 dbg_restore_debug_regs();
1538 static void bsp_resume(void)
1540 if (this_cpu->c_bsp_resume)
1541 this_cpu->c_bsp_resume(&boot_cpu_data);
1544 static struct syscore_ops cpu_syscore_ops = {
1545 .resume = bsp_resume,
1548 static int __init init_cpu_syscore(void)
1550 register_syscore_ops(&cpu_syscore_ops);
1553 core_initcall(init_cpu_syscore);