arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15 #include <linux/nmi.h>
  16
  17 #include <asm/cpufeature.h>
  18 #include <asm/hardirq.h>
  19 #include <asm/apic.h>
  20
  21 #include "perf_event.h"
  22
  23 /*
  24  * Intel PerfMon, used on Core and later.
  25  */
  26 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  27 {
  28         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  29         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  30         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  31         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  32         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  33         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  34         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  35         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  36 };
  37
  38 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  39 {
  40         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  41         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  42         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  43         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  44         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  45         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  46         EVENT_CONSTRAINT_END
  47 };
  48
  49 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  50 {
  51         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  52         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  53         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  54         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  55         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  56         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  57         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  58         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  59         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  60         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  61         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  62         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  63         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  64         EVENT_CONSTRAINT_END
  65 };
  66
  67 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  68 {
  69         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  70         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  71         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  72         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  73         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  74         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  75         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  76         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  77         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  78         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  79         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  80         EVENT_CONSTRAINT_END
  81 };
  82
  83 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  84 {
  85         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  86         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  87         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  88         EVENT_EXTRA_END
  89 };
  90
  91 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  92 {
  93         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  94         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  95         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  96         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  97         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  98         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  99         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 100         EVENT_CONSTRAINT_END
 101 };
 102
 103 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 104 {
 105         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 106         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 107         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 108         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 109         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 110         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 111         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 112         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 113         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 114         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 115         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 116         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 117
 118         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 119         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 120         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 121         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 122
 123         EVENT_CONSTRAINT_END
 124 };
 125
 126 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 127 {
 128         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 129         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 130         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 131         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 132         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 133         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 134         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 135         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 136         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 137         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 138         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 139         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 141
 142         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 143         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 144         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 145         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 146
 147         EVENT_CONSTRAINT_END
 148 };
 149
 150 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 151 {
 152         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 153         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 154         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 155         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 156         EVENT_EXTRA_END
 157 };
 158
 159 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 160 {
 161         EVENT_CONSTRAINT_END
 162 };
 163
 164 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 165 {
 166         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 167         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 168         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 169         EVENT_CONSTRAINT_END
 170 };
 171
 172 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 173 {
 174         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 175         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 176         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 177         EVENT_CONSTRAINT_END
 178 };
 179
 180 struct event_constraint intel_skl_event_constraints[] = {
 181         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 182         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 183         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 184         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 185         EVENT_CONSTRAINT_END
 186 };
 187
 188 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
 189         INTEL_UEVENT_EXTRA_REG(0x01b7,
 190                                MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
 191         INTEL_UEVENT_EXTRA_REG(0x02b7,
 192                                MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
 193         EVENT_EXTRA_END
 194 };
 195
 196 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 197         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 198         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 199         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 200         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 201         EVENT_EXTRA_END
 202 };
 203
 204 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 205         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 206         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 207         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 208         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 209         EVENT_EXTRA_END
 210 };
 211
 212 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 213         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 214         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 215         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 216         /*
 217          * Note the low 8 bits eventsel code is not a continuous field, containing
 218          * some #GPing bits. These are masked out.
 219          */
 220         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 221         EVENT_EXTRA_END
 222 };
 223
 224 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 225 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 226 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 227
 228 struct attribute *nhm_events_attrs[] = {
 229         EVENT_PTR(mem_ld_nhm),
 230         NULL,
 231 };
 232
 233 struct attribute *snb_events_attrs[] = {
 234         EVENT_PTR(mem_ld_snb),
 235         EVENT_PTR(mem_st_snb),
 236         NULL,
 237 };
 238
 239 static struct event_constraint intel_hsw_event_constraints[] = {
 240         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 241         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 242         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 243         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 244         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 245         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 246         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 247         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 248         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 249         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 250         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 251         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 252
 253         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 254         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 255         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 256         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 257
 258         EVENT_CONSTRAINT_END
 259 };
 260
 261 struct event_constraint intel_bdw_event_constraints[] = {
 262         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 263         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 264         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 265         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 266         INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 267         EVENT_CONSTRAINT_END
 268 };
 269
 270 static u64 intel_pmu_event_map(int hw_event)
 271 {
 272         return intel_perfmon_event_map[hw_event];
 273 }
 274
 275 /*
 276  * Notes on the events:
 277  * - data reads do not include code reads (comparable to earlier tables)
 278  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 279  * - remote node access includes remote memory, remote cache, remote mmio.
 280  * - prefetches are not included in the counts.
 281  * - icache miss does not include decoded icache
 282  */
 283
 284 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 285 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 286 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 287 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 288 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 289 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 290 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 291 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 292 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 293                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 294                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 295                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 296 #define SKL_SPL_HIT                     BIT_ULL(30)
 297 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 298 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 299 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 300 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 301 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 302 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 303 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 304 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 305                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 306                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 307                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 308 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 309 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 310                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 311                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 312                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 313 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 314 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 315 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 316                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 317                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 318
 319 static __initconst const u64 skl_hw_cache_event_ids
 320                                 [PERF_COUNT_HW_CACHE_MAX]
 321                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 322                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 323 {
 324  [ C(L1D ) ] = {
 325         [ C(OP_READ) ] = {
 326                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 327                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 328         },
 329         [ C(OP_WRITE) ] = {
 330                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 331                 [ C(RESULT_MISS)   ] = 0x0,
 332         },
 333         [ C(OP_PREFETCH) ] = {
 334                 [ C(RESULT_ACCESS) ] = 0x0,
 335                 [ C(RESULT_MISS)   ] = 0x0,
 336         },
 337  },
 338  [ C(L1I ) ] = {
 339         [ C(OP_READ) ] = {
 340                 [ C(RESULT_ACCESS) ] = 0x0,
 341                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 342         },
 343         [ C(OP_WRITE) ] = {
 344                 [ C(RESULT_ACCESS) ] = -1,
 345                 [ C(RESULT_MISS)   ] = -1,
 346         },
 347         [ C(OP_PREFETCH) ] = {
 348                 [ C(RESULT_ACCESS) ] = 0x0,
 349                 [ C(RESULT_MISS)   ] = 0x0,
 350         },
 351  },
 352  [ C(LL  ) ] = {
 353         [ C(OP_READ) ] = {
 354                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 355                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 356         },
 357         [ C(OP_WRITE) ] = {
 358                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 359                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 360         },
 361         [ C(OP_PREFETCH) ] = {
 362                 [ C(RESULT_ACCESS) ] = 0x0,
 363                 [ C(RESULT_MISS)   ] = 0x0,
 364         },
 365  },
 366  [ C(DTLB) ] = {
 367         [ C(OP_READ) ] = {
 368                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 369                 [ C(RESULT_MISS)   ] = 0x608,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 370         },
 371         [ C(OP_WRITE) ] = {
 372                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 373                 [ C(RESULT_MISS)   ] = 0x649,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 374         },
 375         [ C(OP_PREFETCH) ] = {
 376                 [ C(RESULT_ACCESS) ] = 0x0,
 377                 [ C(RESULT_MISS)   ] = 0x0,
 378         },
 379  },
 380  [ C(ITLB) ] = {
 381         [ C(OP_READ) ] = {
 382                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 383                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 384         },
 385         [ C(OP_WRITE) ] = {
 386                 [ C(RESULT_ACCESS) ] = -1,
 387                 [ C(RESULT_MISS)   ] = -1,
 388         },
 389         [ C(OP_PREFETCH) ] = {
 390                 [ C(RESULT_ACCESS) ] = -1,
 391                 [ C(RESULT_MISS)   ] = -1,
 392         },
 393  },
 394  [ C(BPU ) ] = {
 395         [ C(OP_READ) ] = {
 396                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 397                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 398         },
 399         [ C(OP_WRITE) ] = {
 400                 [ C(RESULT_ACCESS) ] = -1,
 401                 [ C(RESULT_MISS)   ] = -1,
 402         },
 403         [ C(OP_PREFETCH) ] = {
 404                 [ C(RESULT_ACCESS) ] = -1,
 405                 [ C(RESULT_MISS)   ] = -1,
 406         },
 407  },
 408  [ C(NODE) ] = {
 409         [ C(OP_READ) ] = {
 410                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 411                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 412         },
 413         [ C(OP_WRITE) ] = {
 414                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 415                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 416         },
 417         [ C(OP_PREFETCH) ] = {
 418                 [ C(RESULT_ACCESS) ] = 0x0,
 419                 [ C(RESULT_MISS)   ] = 0x0,
 420         },
 421  },
 422 };
 423
 424 static __initconst const u64 skl_hw_cache_extra_regs
 425                                 [PERF_COUNT_HW_CACHE_MAX]
 426                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 427                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 428 {
 429  [ C(LL  ) ] = {
 430         [ C(OP_READ) ] = {
 431                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 432                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 433                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 434                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 435                                        SKL_SUPPLIER_NONE,
 436         },
 437         [ C(OP_WRITE) ] = {
 438                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 439                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 440                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 441                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 442                                        SKL_SUPPLIER_NONE,
 443         },
 444         [ C(OP_PREFETCH) ] = {
 445                 [ C(RESULT_ACCESS) ] = 0x0,
 446                 [ C(RESULT_MISS)   ] = 0x0,
 447         },
 448  },
 449  [ C(NODE) ] = {
 450         [ C(OP_READ) ] = {
 451                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 452                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 453                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 454                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 455         },
 456         [ C(OP_WRITE) ] = {
 457                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 458                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 459                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 460                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 461         },
 462         [ C(OP_PREFETCH) ] = {
 463                 [ C(RESULT_ACCESS) ] = 0x0,
 464                 [ C(RESULT_MISS)   ] = 0x0,
 465         },
 466  },
 467 };
 468
 469 #define SNB_DMND_DATA_RD        (1ULL << 0)
 470 #define SNB_DMND_RFO            (1ULL << 1)
 471 #define SNB_DMND_IFETCH         (1ULL << 2)
 472 #define SNB_DMND_WB             (1ULL << 3)
 473 #define SNB_PF_DATA_RD          (1ULL << 4)
 474 #define SNB_PF_RFO              (1ULL << 5)
 475 #define SNB_PF_IFETCH           (1ULL << 6)
 476 #define SNB_LLC_DATA_RD         (1ULL << 7)
 477 #define SNB_LLC_RFO             (1ULL << 8)
 478 #define SNB_LLC_IFETCH          (1ULL << 9)
 479 #define SNB_BUS_LOCKS           (1ULL << 10)
 480 #define SNB_STRM_ST             (1ULL << 11)
 481 #define SNB_OTHER               (1ULL << 15)
 482 #define SNB_RESP_ANY            (1ULL << 16)
 483 #define SNB_NO_SUPP             (1ULL << 17)
 484 #define SNB_LLC_HITM            (1ULL << 18)
 485 #define SNB_LLC_HITE            (1ULL << 19)
 486 #define SNB_LLC_HITS            (1ULL << 20)
 487 #define SNB_LLC_HITF            (1ULL << 21)
 488 #define SNB_LOCAL               (1ULL << 22)
 489 #define SNB_REMOTE              (0xffULL << 23)
 490 #define SNB_SNP_NONE            (1ULL << 31)
 491 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 492 #define SNB_SNP_MISS            (1ULL << 33)
 493 #define SNB_NO_FWD              (1ULL << 34)
 494 #define SNB_SNP_FWD             (1ULL << 35)
 495 #define SNB_HITM                (1ULL << 36)
 496 #define SNB_NON_DRAM            (1ULL << 37)
 497
 498 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 499 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 500 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 501
 502 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 503                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 504                                  SNB_HITM)
 505
 506 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 507 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 508
 509 #define SNB_L3_ACCESS           SNB_RESP_ANY
 510 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 511
 512 static __initconst const u64 snb_hw_cache_extra_regs
 513                                 [PERF_COUNT_HW_CACHE_MAX]
 514                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 515                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 516 {
 517  [ C(LL  ) ] = {
 518         [ C(OP_READ) ] = {
 519                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 520                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 521         },
 522         [ C(OP_WRITE) ] = {
 523                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 524                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 525         },
 526         [ C(OP_PREFETCH) ] = {
 527                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 528                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 529         },
 530  },
 531  [ C(NODE) ] = {
 532         [ C(OP_READ) ] = {
 533                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 534                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 535         },
 536         [ C(OP_WRITE) ] = {
 537                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 538                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 539         },
 540         [ C(OP_PREFETCH) ] = {
 541                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 542                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 543         },
 544  },
 545 };
 546
 547 static __initconst const u64 snb_hw_cache_event_ids
 548                                 [PERF_COUNT_HW_CACHE_MAX]
 549                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 550                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 551 {
 552  [ C(L1D) ] = {
 553         [ C(OP_READ) ] = {
 554                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 555                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 556         },
 557         [ C(OP_WRITE) ] = {
 558                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 559                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 560         },
 561         [ C(OP_PREFETCH) ] = {
 562                 [ C(RESULT_ACCESS) ] = 0x0,
 563                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 564         },
 565  },
 566  [ C(L1I ) ] = {
 567         [ C(OP_READ) ] = {
 568                 [ C(RESULT_ACCESS) ] = 0x0,
 569                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 570         },
 571         [ C(OP_WRITE) ] = {
 572                 [ C(RESULT_ACCESS) ] = -1,
 573                 [ C(RESULT_MISS)   ] = -1,
 574         },
 575         [ C(OP_PREFETCH) ] = {
 576                 [ C(RESULT_ACCESS) ] = 0x0,
 577                 [ C(RESULT_MISS)   ] = 0x0,
 578         },
 579  },
 580  [ C(LL  ) ] = {
 581         [ C(OP_READ) ] = {
 582                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 583                 [ C(RESULT_ACCESS) ] = 0x01b7,
 584                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 585                 [ C(RESULT_MISS)   ] = 0x01b7,
 586         },
 587         [ C(OP_WRITE) ] = {
 588                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 589                 [ C(RESULT_ACCESS) ] = 0x01b7,
 590                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 591                 [ C(RESULT_MISS)   ] = 0x01b7,
 592         },
 593         [ C(OP_PREFETCH) ] = {
 594                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 595                 [ C(RESULT_ACCESS) ] = 0x01b7,
 596                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 597                 [ C(RESULT_MISS)   ] = 0x01b7,
 598         },
 599  },
 600  [ C(DTLB) ] = {
 601         [ C(OP_READ) ] = {
 602                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 603                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 604         },
 605         [ C(OP_WRITE) ] = {
 606                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 607                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 608         },
 609         [ C(OP_PREFETCH) ] = {
 610                 [ C(RESULT_ACCESS) ] = 0x0,
 611                 [ C(RESULT_MISS)   ] = 0x0,
 612         },
 613  },
 614  [ C(ITLB) ] = {
 615         [ C(OP_READ) ] = {
 616                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 617                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 618         },
 619         [ C(OP_WRITE) ] = {
 620                 [ C(RESULT_ACCESS) ] = -1,
 621                 [ C(RESULT_MISS)   ] = -1,
 622         },
 623         [ C(OP_PREFETCH) ] = {
 624                 [ C(RESULT_ACCESS) ] = -1,
 625                 [ C(RESULT_MISS)   ] = -1,
 626         },
 627  },
 628  [ C(BPU ) ] = {
 629         [ C(OP_READ) ] = {
 630                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 631                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 632         },
 633         [ C(OP_WRITE) ] = {
 634                 [ C(RESULT_ACCESS) ] = -1,
 635                 [ C(RESULT_MISS)   ] = -1,
 636         },
 637         [ C(OP_PREFETCH) ] = {
 638                 [ C(RESULT_ACCESS) ] = -1,
 639                 [ C(RESULT_MISS)   ] = -1,
 640         },
 641  },
 642  [ C(NODE) ] = {
 643         [ C(OP_READ) ] = {
 644                 [ C(RESULT_ACCESS) ] = 0x01b7,
 645                 [ C(RESULT_MISS)   ] = 0x01b7,
 646         },
 647         [ C(OP_WRITE) ] = {
 648                 [ C(RESULT_ACCESS) ] = 0x01b7,
 649                 [ C(RESULT_MISS)   ] = 0x01b7,
 650         },
 651         [ C(OP_PREFETCH) ] = {
 652                 [ C(RESULT_ACCESS) ] = 0x01b7,
 653                 [ C(RESULT_MISS)   ] = 0x01b7,
 654         },
 655  },
 656
 657 };
 658
 659 /*
 660  * Notes on the events:
 661  * - data reads do not include code reads (comparable to earlier tables)
 662  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 663  * - remote node access includes remote memory, remote cache, remote mmio.
 664  * - prefetches are not included in the counts because they are not
 665  *   reliably counted.
 666  */
 667
 668 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 669 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 670 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 671 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 672 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 673 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 674 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 675 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 676 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 677                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 678                                          HSW_L3_MISS_REMOTE_HOP2P)
 679 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 680 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 681 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 682 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 683 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 684 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 685 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 686 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 687                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 688                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 689                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 690 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 691 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 692 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 693 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 694                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 695 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 696
 697 #define BDW_L3_MISS_LOCAL               BIT(26)
 698 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 699                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 700                                          HSW_L3_MISS_REMOTE_HOP2P)
 701
 702
 703 static __initconst const u64 hsw_hw_cache_event_ids
 704                                 [PERF_COUNT_HW_CACHE_MAX]
 705                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 706                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 707 {
 708  [ C(L1D ) ] = {
 709         [ C(OP_READ) ] = {
 710                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 711                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 712         },
 713         [ C(OP_WRITE) ] = {
 714                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 715                 [ C(RESULT_MISS)   ] = 0x0,
 716         },
 717         [ C(OP_PREFETCH) ] = {
 718                 [ C(RESULT_ACCESS) ] = 0x0,
 719                 [ C(RESULT_MISS)   ] = 0x0,
 720         },
 721  },
 722  [ C(L1I ) ] = {
 723         [ C(OP_READ) ] = {
 724                 [ C(RESULT_ACCESS) ] = 0x0,
 725                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 726         },
 727         [ C(OP_WRITE) ] = {
 728                 [ C(RESULT_ACCESS) ] = -1,
 729                 [ C(RESULT_MISS)   ] = -1,
 730         },
 731         [ C(OP_PREFETCH) ] = {
 732                 [ C(RESULT_ACCESS) ] = 0x0,
 733                 [ C(RESULT_MISS)   ] = 0x0,
 734         },
 735  },
 736  [ C(LL  ) ] = {
 737         [ C(OP_READ) ] = {
 738                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 739                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 740         },
 741         [ C(OP_WRITE) ] = {
 742                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 743                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 744         },
 745         [ C(OP_PREFETCH) ] = {
 746                 [ C(RESULT_ACCESS) ] = 0x0,
 747                 [ C(RESULT_MISS)   ] = 0x0,
 748         },
 749  },
 750  [ C(DTLB) ] = {
 751         [ C(OP_READ) ] = {
 752                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 753                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
 754         },
 755         [ C(OP_WRITE) ] = {
 756                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 757                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 758         },
 759         [ C(OP_PREFETCH) ] = {
 760                 [ C(RESULT_ACCESS) ] = 0x0,
 761                 [ C(RESULT_MISS)   ] = 0x0,
 762         },
 763  },
 764  [ C(ITLB) ] = {
 765         [ C(OP_READ) ] = {
 766                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
 767                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
 768         },
 769         [ C(OP_WRITE) ] = {
 770                 [ C(RESULT_ACCESS) ] = -1,
 771                 [ C(RESULT_MISS)   ] = -1,
 772         },
 773         [ C(OP_PREFETCH) ] = {
 774                 [ C(RESULT_ACCESS) ] = -1,
 775                 [ C(RESULT_MISS)   ] = -1,
 776         },
 777  },
 778  [ C(BPU ) ] = {
 779         [ C(OP_READ) ] = {
 780                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 781                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 782         },
 783         [ C(OP_WRITE) ] = {
 784                 [ C(RESULT_ACCESS) ] = -1,
 785                 [ C(RESULT_MISS)   ] = -1,
 786         },
 787         [ C(OP_PREFETCH) ] = {
 788                 [ C(RESULT_ACCESS) ] = -1,
 789                 [ C(RESULT_MISS)   ] = -1,
 790         },
 791  },
 792  [ C(NODE) ] = {
 793         [ C(OP_READ) ] = {
 794                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 795                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 796         },
 797         [ C(OP_WRITE) ] = {
 798                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 799                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 800         },
 801         [ C(OP_PREFETCH) ] = {
 802                 [ C(RESULT_ACCESS) ] = 0x0,
 803                 [ C(RESULT_MISS)   ] = 0x0,
 804         },
 805  },
 806 };
 807
 808 static __initconst const u64 hsw_hw_cache_extra_regs
 809                                 [PERF_COUNT_HW_CACHE_MAX]
 810                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 811                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 812 {
 813  [ C(LL  ) ] = {
 814         [ C(OP_READ) ] = {
 815                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 816                                        HSW_LLC_ACCESS,
 817                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 818                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 819         },
 820         [ C(OP_WRITE) ] = {
 821                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 822                                        HSW_LLC_ACCESS,
 823                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 824                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 825         },
 826         [ C(OP_PREFETCH) ] = {
 827                 [ C(RESULT_ACCESS) ] = 0x0,
 828                 [ C(RESULT_MISS)   ] = 0x0,
 829         },
 830  },
 831  [ C(NODE) ] = {
 832         [ C(OP_READ) ] = {
 833                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 834                                        HSW_L3_MISS_LOCAL_DRAM|
 835                                        HSW_SNOOP_DRAM,
 836                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 837                                        HSW_L3_MISS_REMOTE|
 838                                        HSW_SNOOP_DRAM,
 839         },
 840         [ C(OP_WRITE) ] = {
 841                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 842                                        HSW_L3_MISS_LOCAL_DRAM|
 843                                        HSW_SNOOP_DRAM,
 844                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 845                                        HSW_L3_MISS_REMOTE|
 846                                        HSW_SNOOP_DRAM,
 847         },
 848         [ C(OP_PREFETCH) ] = {
 849                 [ C(RESULT_ACCESS) ] = 0x0,
 850                 [ C(RESULT_MISS)   ] = 0x0,
 851         },
 852  },
 853 };
 854
 855 static __initconst const u64 westmere_hw_cache_event_ids
 856                                 [PERF_COUNT_HW_CACHE_MAX]
 857                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 858                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 859 {
 860  [ C(L1D) ] = {
 861         [ C(OP_READ) ] = {
 862                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 863                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 864         },
 865         [ C(OP_WRITE) ] = {
 866                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 867                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 868         },
 869         [ C(OP_PREFETCH) ] = {
 870                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 871                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 872         },
 873  },
 874  [ C(L1I ) ] = {
 875         [ C(OP_READ) ] = {
 876                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 877                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 878         },
 879         [ C(OP_WRITE) ] = {
 880                 [ C(RESULT_ACCESS) ] = -1,
 881                 [ C(RESULT_MISS)   ] = -1,
 882         },
 883         [ C(OP_PREFETCH) ] = {
 884                 [ C(RESULT_ACCESS) ] = 0x0,
 885                 [ C(RESULT_MISS)   ] = 0x0,
 886         },
 887  },
 888  [ C(LL  ) ] = {
 889         [ C(OP_READ) ] = {
 890                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 891                 [ C(RESULT_ACCESS) ] = 0x01b7,
 892                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 893                 [ C(RESULT_MISS)   ] = 0x01b7,
 894         },
 895         /*
 896          * Use RFO, not WRITEBACK, because a write miss would typically occur
 897          * on RFO.
 898          */
 899         [ C(OP_WRITE) ] = {
 900                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 901                 [ C(RESULT_ACCESS) ] = 0x01b7,
 902                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 903                 [ C(RESULT_MISS)   ] = 0x01b7,
 904         },
 905         [ C(OP_PREFETCH) ] = {
 906                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 907                 [ C(RESULT_ACCESS) ] = 0x01b7,
 908                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 909                 [ C(RESULT_MISS)   ] = 0x01b7,
 910         },
 911  },
 912  [ C(DTLB) ] = {
 913         [ C(OP_READ) ] = {
 914                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 915                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 916         },
 917         [ C(OP_WRITE) ] = {
 918                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 919                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 920         },
 921         [ C(OP_PREFETCH) ] = {
 922                 [ C(RESULT_ACCESS) ] = 0x0,
 923                 [ C(RESULT_MISS)   ] = 0x0,
 924         },
 925  },
 926  [ C(ITLB) ] = {
 927         [ C(OP_READ) ] = {
 928                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 929                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 930         },
 931         [ C(OP_WRITE) ] = {
 932                 [ C(RESULT_ACCESS) ] = -1,
 933                 [ C(RESULT_MISS)   ] = -1,
 934         },
 935         [ C(OP_PREFETCH) ] = {
 936                 [ C(RESULT_ACCESS) ] = -1,
 937                 [ C(RESULT_MISS)   ] = -1,
 938         },
 939  },
 940  [ C(BPU ) ] = {
 941         [ C(OP_READ) ] = {
 942                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 943                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 944         },
 945         [ C(OP_WRITE) ] = {
 946                 [ C(RESULT_ACCESS) ] = -1,
 947                 [ C(RESULT_MISS)   ] = -1,
 948         },
 949         [ C(OP_PREFETCH) ] = {
 950                 [ C(RESULT_ACCESS) ] = -1,
 951                 [ C(RESULT_MISS)   ] = -1,
 952         },
 953  },
 954  [ C(NODE) ] = {
 955         [ C(OP_READ) ] = {
 956                 [ C(RESULT_ACCESS) ] = 0x01b7,
 957                 [ C(RESULT_MISS)   ] = 0x01b7,
 958         },
 959         [ C(OP_WRITE) ] = {
 960                 [ C(RESULT_ACCESS) ] = 0x01b7,
 961                 [ C(RESULT_MISS)   ] = 0x01b7,
 962         },
 963         [ C(OP_PREFETCH) ] = {
 964                 [ C(RESULT_ACCESS) ] = 0x01b7,
 965                 [ C(RESULT_MISS)   ] = 0x01b7,
 966         },
 967  },
 968 };
 969
 970 /*
 971  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 972  * See IA32 SDM Vol 3B 30.6.1.3
 973  */
 974
 975 #define NHM_DMND_DATA_RD        (1 << 0)
 976 #define NHM_DMND_RFO            (1 << 1)
 977 #define NHM_DMND_IFETCH         (1 << 2)
 978 #define NHM_DMND_WB             (1 << 3)
 979 #define NHM_PF_DATA_RD          (1 << 4)
 980 #define NHM_PF_DATA_RFO         (1 << 5)
 981 #define NHM_PF_IFETCH           (1 << 6)
 982 #define NHM_OFFCORE_OTHER       (1 << 7)
 983 #define NHM_UNCORE_HIT          (1 << 8)
 984 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 985 #define NHM_OTHER_CORE_HITM     (1 << 10)
 986                                 /* reserved */
 987 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 988 #define NHM_REMOTE_DRAM         (1 << 13)
 989 #define NHM_LOCAL_DRAM          (1 << 14)
 990 #define NHM_NON_DRAM            (1 << 15)
 991
 992 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 993 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 994
 995 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 996 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 997 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 998
 999 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1000 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1001 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
1002
1003 static __initconst const u64 nehalem_hw_cache_extra_regs
1004                                 [PERF_COUNT_HW_CACHE_MAX]
1005                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1006                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1007 {
1008  [ C(LL  ) ] = {
1009         [ C(OP_READ) ] = {
1010                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1011                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1012         },
1013         [ C(OP_WRITE) ] = {
1014                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1015                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1016         },
1017         [ C(OP_PREFETCH) ] = {
1018                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1019                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1020         },
1021  },
1022  [ C(NODE) ] = {
1023         [ C(OP_READ) ] = {
1024                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1025                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1026         },
1027         [ C(OP_WRITE) ] = {
1028                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1029                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1030         },
1031         [ C(OP_PREFETCH) ] = {
1032                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1033                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1034         },
1035  },
1036 };
1037
1038 static __initconst const u64 nehalem_hw_cache_event_ids
1039                                 [PERF_COUNT_HW_CACHE_MAX]
1040                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1041                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1042 {
1043  [ C(L1D) ] = {
1044         [ C(OP_READ) ] = {
1045                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1046                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1047         },
1048         [ C(OP_WRITE) ] = {
1049                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1050                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1051         },
1052         [ C(OP_PREFETCH) ] = {
1053                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1054                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1055         },
1056  },
1057  [ C(L1I ) ] = {
1058         [ C(OP_READ) ] = {
1059                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1060                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1061         },
1062         [ C(OP_WRITE) ] = {
1063                 [ C(RESULT_ACCESS) ] = -1,
1064                 [ C(RESULT_MISS)   ] = -1,
1065         },
1066         [ C(OP_PREFETCH) ] = {
1067                 [ C(RESULT_ACCESS) ] = 0x0,
1068                 [ C(RESULT_MISS)   ] = 0x0,
1069         },
1070  },
1071  [ C(LL  ) ] = {
1072         [ C(OP_READ) ] = {
1073                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1074                 [ C(RESULT_ACCESS) ] = 0x01b7,
1075                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1076                 [ C(RESULT_MISS)   ] = 0x01b7,
1077         },
1078         /*
1079          * Use RFO, not WRITEBACK, because a write miss would typically occur
1080          * on RFO.
1081          */
1082         [ C(OP_WRITE) ] = {
1083                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1084                 [ C(RESULT_ACCESS) ] = 0x01b7,
1085                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1086                 [ C(RESULT_MISS)   ] = 0x01b7,
1087         },
1088         [ C(OP_PREFETCH) ] = {
1089                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1090                 [ C(RESULT_ACCESS) ] = 0x01b7,
1091                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1092                 [ C(RESULT_MISS)   ] = 0x01b7,
1093         },
1094  },
1095  [ C(DTLB) ] = {
1096         [ C(OP_READ) ] = {
1097                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1098                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1099         },
1100         [ C(OP_WRITE) ] = {
1101                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1102                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1103         },
1104         [ C(OP_PREFETCH) ] = {
1105                 [ C(RESULT_ACCESS) ] = 0x0,
1106                 [ C(RESULT_MISS)   ] = 0x0,
1107         },
1108  },
1109  [ C(ITLB) ] = {
1110         [ C(OP_READ) ] = {
1111                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1112                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1113         },
1114         [ C(OP_WRITE) ] = {
1115                 [ C(RESULT_ACCESS) ] = -1,
1116                 [ C(RESULT_MISS)   ] = -1,
1117         },
1118         [ C(OP_PREFETCH) ] = {
1119                 [ C(RESULT_ACCESS) ] = -1,
1120                 [ C(RESULT_MISS)   ] = -1,
1121         },
1122  },
1123  [ C(BPU ) ] = {
1124         [ C(OP_READ) ] = {
1125                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1126                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1127         },
1128         [ C(OP_WRITE) ] = {
1129                 [ C(RESULT_ACCESS) ] = -1,
1130                 [ C(RESULT_MISS)   ] = -1,
1131         },
1132         [ C(OP_PREFETCH) ] = {
1133                 [ C(RESULT_ACCESS) ] = -1,
1134                 [ C(RESULT_MISS)   ] = -1,
1135         },
1136  },
1137  [ C(NODE) ] = {
1138         [ C(OP_READ) ] = {
1139                 [ C(RESULT_ACCESS) ] = 0x01b7,
1140                 [ C(RESULT_MISS)   ] = 0x01b7,
1141         },
1142         [ C(OP_WRITE) ] = {
1143                 [ C(RESULT_ACCESS) ] = 0x01b7,
1144                 [ C(RESULT_MISS)   ] = 0x01b7,
1145         },
1146         [ C(OP_PREFETCH) ] = {
1147                 [ C(RESULT_ACCESS) ] = 0x01b7,
1148                 [ C(RESULT_MISS)   ] = 0x01b7,
1149         },
1150  },
1151 };
1152
1153 static __initconst const u64 core2_hw_cache_event_ids
1154                                 [PERF_COUNT_HW_CACHE_MAX]
1155                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1156                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1157 {
1158  [ C(L1D) ] = {
1159         [ C(OP_READ) ] = {
1160                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1161                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1162         },
1163         [ C(OP_WRITE) ] = {
1164                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1165                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1166         },
1167         [ C(OP_PREFETCH) ] = {
1168                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1169                 [ C(RESULT_MISS)   ] = 0,
1170         },
1171  },
1172  [ C(L1I ) ] = {
1173         [ C(OP_READ) ] = {
1174                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1175                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1176         },
1177         [ C(OP_WRITE) ] = {
1178                 [ C(RESULT_ACCESS) ] = -1,
1179                 [ C(RESULT_MISS)   ] = -1,
1180         },
1181         [ C(OP_PREFETCH) ] = {
1182                 [ C(RESULT_ACCESS) ] = 0,
1183                 [ C(RESULT_MISS)   ] = 0,
1184         },
1185  },
1186  [ C(LL  ) ] = {
1187         [ C(OP_READ) ] = {
1188                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1189                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1190         },
1191         [ C(OP_WRITE) ] = {
1192                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1193                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1194         },
1195         [ C(OP_PREFETCH) ] = {
1196                 [ C(RESULT_ACCESS) ] = 0,
1197                 [ C(RESULT_MISS)   ] = 0,
1198         },
1199  },
1200  [ C(DTLB) ] = {
1201         [ C(OP_READ) ] = {
1202                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1203                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1204         },
1205         [ C(OP_WRITE) ] = {
1206                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1207                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1208         },
1209         [ C(OP_PREFETCH) ] = {
1210                 [ C(RESULT_ACCESS) ] = 0,
1211                 [ C(RESULT_MISS)   ] = 0,
1212         },
1213  },
1214  [ C(ITLB) ] = {
1215         [ C(OP_READ) ] = {
1216                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1217                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1218         },
1219         [ C(OP_WRITE) ] = {
1220                 [ C(RESULT_ACCESS) ] = -1,
1221                 [ C(RESULT_MISS)   ] = -1,
1222         },
1223         [ C(OP_PREFETCH) ] = {
1224                 [ C(RESULT_ACCESS) ] = -1,
1225                 [ C(RESULT_MISS)   ] = -1,
1226         },
1227  },
1228  [ C(BPU ) ] = {
1229         [ C(OP_READ) ] = {
1230                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1231                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1232         },
1233         [ C(OP_WRITE) ] = {
1234                 [ C(RESULT_ACCESS) ] = -1,
1235                 [ C(RESULT_MISS)   ] = -1,
1236         },
1237         [ C(OP_PREFETCH) ] = {
1238                 [ C(RESULT_ACCESS) ] = -1,
1239                 [ C(RESULT_MISS)   ] = -1,
1240         },
1241  },
1242 };
1243
1244 static __initconst const u64 atom_hw_cache_event_ids
1245                                 [PERF_COUNT_HW_CACHE_MAX]
1246                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1247                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1248 {
1249  [ C(L1D) ] = {
1250         [ C(OP_READ) ] = {
1251                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1252                 [ C(RESULT_MISS)   ] = 0,
1253         },
1254         [ C(OP_WRITE) ] = {
1255                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1256                 [ C(RESULT_MISS)   ] = 0,
1257         },
1258         [ C(OP_PREFETCH) ] = {
1259                 [ C(RESULT_ACCESS) ] = 0x0,
1260                 [ C(RESULT_MISS)   ] = 0,
1261         },
1262  },
1263  [ C(L1I ) ] = {
1264         [ C(OP_READ) ] = {
1265                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1266                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1267         },
1268         [ C(OP_WRITE) ] = {
1269                 [ C(RESULT_ACCESS) ] = -1,
1270                 [ C(RESULT_MISS)   ] = -1,
1271         },
1272         [ C(OP_PREFETCH) ] = {
1273                 [ C(RESULT_ACCESS) ] = 0,
1274                 [ C(RESULT_MISS)   ] = 0,
1275         },
1276  },
1277  [ C(LL  ) ] = {
1278         [ C(OP_READ) ] = {
1279                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1280                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1281         },
1282         [ C(OP_WRITE) ] = {
1283                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1284                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1285         },
1286         [ C(OP_PREFETCH) ] = {
1287                 [ C(RESULT_ACCESS) ] = 0,
1288                 [ C(RESULT_MISS)   ] = 0,
1289         },
1290  },
1291  [ C(DTLB) ] = {
1292         [ C(OP_READ) ] = {
1293                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1294                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1295         },
1296         [ C(OP_WRITE) ] = {
1297                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1298                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1299         },
1300         [ C(OP_PREFETCH) ] = {
1301                 [ C(RESULT_ACCESS) ] = 0,
1302                 [ C(RESULT_MISS)   ] = 0,
1303         },
1304  },
1305  [ C(ITLB) ] = {
1306         [ C(OP_READ) ] = {
1307                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1308                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1309         },
1310         [ C(OP_WRITE) ] = {
1311                 [ C(RESULT_ACCESS) ] = -1,
1312                 [ C(RESULT_MISS)   ] = -1,
1313         },
1314         [ C(OP_PREFETCH) ] = {
1315                 [ C(RESULT_ACCESS) ] = -1,
1316                 [ C(RESULT_MISS)   ] = -1,
1317         },
1318  },
1319  [ C(BPU ) ] = {
1320         [ C(OP_READ) ] = {
1321                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1322                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1323         },
1324         [ C(OP_WRITE) ] = {
1325                 [ C(RESULT_ACCESS) ] = -1,
1326                 [ C(RESULT_MISS)   ] = -1,
1327         },
1328         [ C(OP_PREFETCH) ] = {
1329                 [ C(RESULT_ACCESS) ] = -1,
1330                 [ C(RESULT_MISS)   ] = -1,
1331         },
1332  },
1333 };
1334
1335 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1336 {
1337         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1338         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1339         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1340         EVENT_EXTRA_END
1341 };
1342
1343 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1344 #define SLM_DMND_WRITE          SNB_DMND_RFO
1345 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1346
1347 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1348 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1349 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1350
1351 static __initconst const u64 slm_hw_cache_extra_regs
1352                                 [PERF_COUNT_HW_CACHE_MAX]
1353                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1354                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1355 {
1356  [ C(LL  ) ] = {
1357         [ C(OP_READ) ] = {
1358                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1359                 [ C(RESULT_MISS)   ] = 0,
1360         },
1361         [ C(OP_WRITE) ] = {
1362                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1363                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1364         },
1365         [ C(OP_PREFETCH) ] = {
1366                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1367                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1368         },
1369  },
1370 };
1371
1372 static __initconst const u64 slm_hw_cache_event_ids
1373                                 [PERF_COUNT_HW_CACHE_MAX]
1374                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1375                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1376 {
1377  [ C(L1D) ] = {
1378         [ C(OP_READ) ] = {
1379                 [ C(RESULT_ACCESS) ] = 0,
1380                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1381         },
1382         [ C(OP_WRITE) ] = {
1383                 [ C(RESULT_ACCESS) ] = 0,
1384                 [ C(RESULT_MISS)   ] = 0,
1385         },
1386         [ C(OP_PREFETCH) ] = {
1387                 [ C(RESULT_ACCESS) ] = 0,
1388                 [ C(RESULT_MISS)   ] = 0,
1389         },
1390  },
1391  [ C(L1I ) ] = {
1392         [ C(OP_READ) ] = {
1393                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1394                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1395         },
1396         [ C(OP_WRITE) ] = {
1397                 [ C(RESULT_ACCESS) ] = -1,
1398                 [ C(RESULT_MISS)   ] = -1,
1399         },
1400         [ C(OP_PREFETCH) ] = {
1401                 [ C(RESULT_ACCESS) ] = 0,
1402                 [ C(RESULT_MISS)   ] = 0,
1403         },
1404  },
1405  [ C(LL  ) ] = {
1406         [ C(OP_READ) ] = {
1407                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1408                 [ C(RESULT_ACCESS) ] = 0x01b7,
1409                 [ C(RESULT_MISS)   ] = 0,
1410         },
1411         [ C(OP_WRITE) ] = {
1412                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1413                 [ C(RESULT_ACCESS) ] = 0x01b7,
1414                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1415                 [ C(RESULT_MISS)   ] = 0x01b7,
1416         },
1417         [ C(OP_PREFETCH) ] = {
1418                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1419                 [ C(RESULT_ACCESS) ] = 0x01b7,
1420                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1421                 [ C(RESULT_MISS)   ] = 0x01b7,
1422         },
1423  },
1424  [ C(DTLB) ] = {
1425         [ C(OP_READ) ] = {
1426                 [ C(RESULT_ACCESS) ] = 0,
1427                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1428         },
1429         [ C(OP_WRITE) ] = {
1430                 [ C(RESULT_ACCESS) ] = 0,
1431                 [ C(RESULT_MISS)   ] = 0,
1432         },
1433         [ C(OP_PREFETCH) ] = {
1434                 [ C(RESULT_ACCESS) ] = 0,
1435                 [ C(RESULT_MISS)   ] = 0,
1436         },
1437  },
1438  [ C(ITLB) ] = {
1439         [ C(OP_READ) ] = {
1440                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1441                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1442         },
1443         [ C(OP_WRITE) ] = {
1444                 [ C(RESULT_ACCESS) ] = -1,
1445                 [ C(RESULT_MISS)   ] = -1,
1446         },
1447         [ C(OP_PREFETCH) ] = {
1448                 [ C(RESULT_ACCESS) ] = -1,
1449                 [ C(RESULT_MISS)   ] = -1,
1450         },
1451  },
1452  [ C(BPU ) ] = {
1453         [ C(OP_READ) ] = {
1454                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1455                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1456         },
1457         [ C(OP_WRITE) ] = {
1458                 [ C(RESULT_ACCESS) ] = -1,
1459                 [ C(RESULT_MISS)   ] = -1,
1460         },
1461         [ C(OP_PREFETCH) ] = {
1462                 [ C(RESULT_ACCESS) ] = -1,
1463                 [ C(RESULT_MISS)   ] = -1,
1464         },
1465  },
1466 };
1467
1468 #define KNL_OT_L2_HITE          BIT_ULL(19) /* Other Tile L2 Hit */
1469 #define KNL_OT_L2_HITF          BIT_ULL(20) /* Other Tile L2 Hit */
1470 #define KNL_MCDRAM_LOCAL        BIT_ULL(21)
1471 #define KNL_MCDRAM_FAR          BIT_ULL(22)
1472 #define KNL_DDR_LOCAL           BIT_ULL(23)
1473 #define KNL_DDR_FAR             BIT_ULL(24)
1474 #define KNL_DRAM_ANY            (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1475                                     KNL_DDR_LOCAL | KNL_DDR_FAR)
1476 #define KNL_L2_READ             SLM_DMND_READ
1477 #define KNL_L2_WRITE            SLM_DMND_WRITE
1478 #define KNL_L2_PREFETCH         SLM_DMND_PREFETCH
1479 #define KNL_L2_ACCESS           SLM_LLC_ACCESS
1480 #define KNL_L2_MISS             (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1481                                    KNL_DRAM_ANY | SNB_SNP_ANY | \
1482                                                   SNB_NON_DRAM)
1483
1484 static __initconst const u64 knl_hw_cache_extra_regs
1485                                 [PERF_COUNT_HW_CACHE_MAX]
1486                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1487                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1488         [C(LL)] = {
1489                 [C(OP_READ)] = {
1490                         [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1491                         [C(RESULT_MISS)]   = 0,
1492                 },
1493                 [C(OP_WRITE)] = {
1494                         [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1495                         [C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
1496                 },
1497                 [C(OP_PREFETCH)] = {
1498                         [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1499                         [C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
1500                 },
1501         },
1502 };
1503
1504 /*
1505  * Use from PMIs where the LBRs are already disabled.
1506  */
1507 static void __intel_pmu_disable_all(void)
1508 {
1509         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1510
1511         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1512
1513         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1514                 intel_pmu_disable_bts();
1515         else
1516                 intel_bts_disable_local();
1517
1518         intel_pmu_pebs_disable_all();
1519 }
1520
1521 static void intel_pmu_disable_all(void)
1522 {
1523         __intel_pmu_disable_all();
1524         intel_pmu_lbr_disable_all();
1525 }
1526
1527 static void __intel_pmu_enable_all(int added, bool pmi)
1528 {
1529         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1530
1531         intel_pmu_pebs_enable_all();
1532         intel_pmu_lbr_enable_all(pmi);
1533         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1534                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1535
1536         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1537                 struct perf_event *event =
1538                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1539
1540                 if (WARN_ON_ONCE(!event))
1541                         return;
1542
1543                 intel_pmu_enable_bts(event->hw.config);
1544         } else
1545                 intel_bts_enable_local();
1546 }
1547
1548 static void intel_pmu_enable_all(int added)
1549 {
1550         __intel_pmu_enable_all(added, false);
1551 }
1552
1553 /*
1554  * Workaround for:
1555  *   Intel Errata AAK100 (model 26)
1556  *   Intel Errata AAP53  (model 30)
1557  *   Intel Errata BD53   (model 44)
1558  *
1559  * The official story:
1560  *   These chips need to be 'reset' when adding counters by programming the
1561  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1562  *   in sequence on the same PMC or on different PMCs.
1563  *
1564  * In practise it appears some of these events do in fact count, and
1565  * we need to programm all 4 events.
1566  */
1567 static void intel_pmu_nhm_workaround(void)
1568 {
1569         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1570         static const unsigned long nhm_magic[4] = {
1571                 0x4300B5,
1572                 0x4300D2,
1573                 0x4300B1,
1574                 0x4300B1
1575         };
1576         struct perf_event *event;
1577         int i;
1578
1579         /*
1580          * The Errata requires below steps:
1581          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1582          * 2) Configure 4 PERFEVTSELx with the magic events and clear
1583          *    the corresponding PMCx;
1584          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1585          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1586          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1587          */
1588
1589         /*
1590          * The real steps we choose are a little different from above.
1591          * A) To reduce MSR operations, we don't run step 1) as they
1592          *    are already cleared before this function is called;
1593          * B) Call x86_perf_event_update to save PMCx before configuring
1594          *    PERFEVTSELx with magic number;
1595          * C) With step 5), we do clear only when the PERFEVTSELx is
1596          *    not used currently.
1597          * D) Call x86_perf_event_set_period to restore PMCx;
1598          */
1599
1600         /* We always operate 4 pairs of PERF Counters */
1601         for (i = 0; i < 4; i++) {
1602                 event = cpuc->events[i];
1603                 if (event)
1604                         x86_perf_event_update(event);
1605         }
1606
1607         for (i = 0; i < 4; i++) {
1608                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1609                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1610         }
1611
1612         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1613         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1614
1615         for (i = 0; i < 4; i++) {
1616                 event = cpuc->events[i];
1617
1618                 if (event) {
1619                         x86_perf_event_set_period(event);
1620                         __x86_pmu_enable_event(&event->hw,
1621                                         ARCH_PERFMON_EVENTSEL_ENABLE);
1622                 } else
1623                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1624         }
1625 }
1626
1627 static void intel_pmu_nhm_enable_all(int added)
1628 {
1629         if (added)
1630                 intel_pmu_nhm_workaround();
1631         intel_pmu_enable_all(added);
1632 }
1633
1634 static inline u64 intel_pmu_get_status(void)
1635 {
1636         u64 status;
1637
1638         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1639
1640         return status;
1641 }
1642
1643 static inline void intel_pmu_ack_status(u64 ack)
1644 {
1645         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1646 }
1647
1648 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1649 {
1650         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1651         u64 ctrl_val, mask;
1652
1653         mask = 0xfULL << (idx * 4);
1654
1655         rdmsrl(hwc->config_base, ctrl_val);
1656         ctrl_val &= ~mask;
1657         wrmsrl(hwc->config_base, ctrl_val);
1658 }
1659
1660 static inline bool event_is_checkpointed(struct perf_event *event)
1661 {
1662         return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1663 }
1664
1665 static void intel_pmu_disable_event(struct perf_event *event)
1666 {
1667         struct hw_perf_event *hwc = &event->hw;
1668         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1669
1670         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1671                 intel_pmu_disable_bts();
1672                 intel_pmu_drain_bts_buffer();
1673                 return;
1674         }
1675
1676         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1677         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1678         cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1679
1680         /*
1681          * must disable before any actual event
1682          * because any event may be combined with LBR
1683          */
1684         if (needs_branch_stack(event))
1685                 intel_pmu_lbr_disable(event);
1686
1687         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1688                 intel_pmu_disable_fixed(hwc);
1689                 return;
1690         }
1691
1692         x86_pmu_disable_event(event);
1693
1694         if (unlikely(event->attr.precise_ip))
1695                 intel_pmu_pebs_disable(event);
1696 }
1697
1698 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1699 {
1700         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1701         u64 ctrl_val, bits, mask;
1702
1703         /*
1704          * Enable IRQ generation (0x8),
1705          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1706          * if requested:
1707          */
1708         bits = 0x8ULL;
1709         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1710                 bits |= 0x2;
1711         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1712                 bits |= 0x1;
1713
1714         /*
1715          * ANY bit is supported in v3 and up
1716          */
1717         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1718                 bits |= 0x4;
1719
1720         bits <<= (idx * 4);
1721         mask = 0xfULL << (idx * 4);
1722
1723         rdmsrl(hwc->config_base, ctrl_val);
1724         ctrl_val &= ~mask;
1725         ctrl_val |= bits;
1726         wrmsrl(hwc->config_base, ctrl_val);
1727 }
1728
1729 static void intel_pmu_enable_event(struct perf_event *event)
1730 {
1731         struct hw_perf_event *hwc = &event->hw;
1732         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1733
1734         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1735                 if (!__this_cpu_read(cpu_hw_events.enabled))
1736                         return;
1737
1738                 intel_pmu_enable_bts(hwc->config);
1739                 return;
1740         }
1741         /*
1742          * must enabled before any actual event
1743          * because any event may be combined with LBR
1744          */
1745         if (needs_branch_stack(event))
1746                 intel_pmu_lbr_enable(event);
1747
1748         if (event->attr.exclude_host)
1749                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1750         if (event->attr.exclude_guest)
1751                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1752
1753         if (unlikely(event_is_checkpointed(event)))
1754                 cpuc->intel_cp_status |= (1ull << hwc->idx);
1755
1756         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1757                 intel_pmu_enable_fixed(hwc);
1758                 return;
1759         }
1760
1761         if (unlikely(event->attr.precise_ip))
1762                 intel_pmu_pebs_enable(event);
1763
1764         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1765 }
1766
1767 /*
1768  * Save and restart an expired event. Called by NMI contexts,
1769  * so it has to be careful about preempting normal event ops:
1770  */
1771 int intel_pmu_save_and_restart(struct perf_event *event)
1772 {
1773         x86_perf_event_update(event);
1774         /*
1775          * For a checkpointed counter always reset back to 0.  This
1776          * avoids a situation where the counter overflows, aborts the
1777          * transaction and is then set back to shortly before the
1778          * overflow, and overflows and aborts again.
1779          */
1780         if (unlikely(event_is_checkpointed(event))) {
1781                 /* No race with NMIs because the counter should not be armed */
1782                 wrmsrl(event->hw.event_base, 0);
1783                 local64_set(&event->hw.prev_count, 0);
1784         }
1785         return x86_perf_event_set_period(event);
1786 }
1787
1788 static void intel_pmu_reset(void)
1789 {
1790         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1791         unsigned long flags;
1792         int idx;
1793
1794         if (!x86_pmu.num_counters)
1795                 return;
1796
1797         local_irq_save(flags);
1798
1799         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1800
1801         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1802                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1803                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1804         }
1805         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1806                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1807
1808         if (ds)
1809                 ds->bts_index = ds->bts_buffer_base;
1810
1811         /* Ack all overflows and disable fixed counters */
1812         if (x86_pmu.version >= 2) {
1813                 intel_pmu_ack_status(intel_pmu_get_status());
1814                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1815         }
1816
1817         /* Reset LBRs and LBR freezing */
1818         if (x86_pmu.lbr_nr) {
1819                 update_debugctlmsr(get_debugctlmsr() &
1820                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1821         }
1822
1823         local_irq_restore(flags);
1824 }
1825
1826 /*
1827  * This handler is triggered by the local APIC, so the APIC IRQ handling
1828  * rules apply:
1829  */
1830 static int intel_pmu_handle_irq(struct pt_regs *regs)
1831 {
1832         struct perf_sample_data data;
1833         struct cpu_hw_events *cpuc;
1834         int bit, loops;
1835         u64 status;
1836         int handled;
1837
1838         cpuc = this_cpu_ptr(&cpu_hw_events);
1839
1840         /*
1841          * No known reason to not always do late ACK,
1842          * but just in case do it opt-in.
1843          */
1844         if (!x86_pmu.late_ack)
1845                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1846         __intel_pmu_disable_all();
1847         handled = intel_pmu_drain_bts_buffer();
1848         handled += intel_bts_interrupt();
1849         status = intel_pmu_get_status();
1850         if (!status)
1851                 goto done;
1852
1853         loops = 0;
1854 again:
1855         intel_pmu_lbr_read();
1856         intel_pmu_ack_status(status);
1857         if (++loops > 100) {
1858                 static bool warned = false;
1859                 if (!warned) {
1860                         WARN(1, "perfevents: irq loop stuck!\n");
1861                         perf_event_print_debug();
1862                         warned = true;
1863                 }
1864                 intel_pmu_reset();
1865                 goto done;
1866         }
1867
1868         inc_irq_stat(apic_perf_irqs);
1869
1870
1871         /*
1872          * Ignore a range of extra bits in status that do not indicate
1873          * overflow by themselves.
1874          */
1875         status &= ~(GLOBAL_STATUS_COND_CHG |
1876                     GLOBAL_STATUS_ASIF |
1877                     GLOBAL_STATUS_LBRS_FROZEN);
1878         if (!status)
1879                 goto done;
1880
1881         /*
1882          * PEBS overflow sets bit 62 in the global status register
1883          */
1884         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1885                 handled++;
1886                 x86_pmu.drain_pebs(regs);
1887         }
1888
1889         /*
1890          * Intel PT
1891          */
1892         if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1893                 handled++;
1894                 intel_pt_interrupt();
1895         }
1896
1897         /*
1898          * Checkpointed counters can lead to 'spurious' PMIs because the
1899          * rollback caused by the PMI will have cleared the overflow status
1900          * bit. Therefore always force probe these counters.
1901          */
1902         status |= cpuc->intel_cp_status;
1903
1904         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1905                 struct perf_event *event = cpuc->events[bit];
1906
1907                 handled++;
1908
1909                 if (!test_bit(bit, cpuc->active_mask))
1910                         continue;
1911
1912                 if (!intel_pmu_save_and_restart(event))
1913                         continue;
1914
1915                 perf_sample_data_init(&data, 0, event->hw.last_period);
1916
1917                 if (has_branch_stack(event))
1918                         data.br_stack = &cpuc->lbr_stack;
1919
1920                 if (perf_event_overflow(event, &data, regs))
1921                         x86_pmu_stop(event, 0);
1922         }
1923
1924         /*
1925          * Repeat if there is more work to be done:
1926          */
1927         status = intel_pmu_get_status();
1928         if (status)
1929                 goto again;
1930
1931 done:
1932         __intel_pmu_enable_all(0, true);
1933         /*
1934          * Only unmask the NMI after the overflow counters
1935          * have been reset. This avoids spurious NMIs on
1936          * Haswell CPUs.
1937          */
1938         if (x86_pmu.late_ack)
1939                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1940         return handled;
1941 }
1942
1943 static struct event_constraint *
1944 intel_bts_constraints(struct perf_event *event)
1945 {
1946         struct hw_perf_event *hwc = &event->hw;
1947         unsigned int hw_event, bts_event;
1948
1949         if (event->attr.freq)
1950                 return NULL;
1951
1952         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1953         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1954
1955         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1956                 return &bts_constraint;
1957
1958         return NULL;
1959 }
1960
1961 static int intel_alt_er(int idx, u64 config)
1962 {
1963         int alt_idx = idx;
1964
1965         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
1966                 return idx;
1967
1968         if (idx == EXTRA_REG_RSP_0)
1969                 alt_idx = EXTRA_REG_RSP_1;
1970
1971         if (idx == EXTRA_REG_RSP_1)
1972                 alt_idx = EXTRA_REG_RSP_0;
1973
1974         if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1975                 return idx;
1976
1977         return alt_idx;
1978 }
1979
1980 static void intel_fixup_er(struct perf_event *event, int idx)
1981 {
1982         event->hw.extra_reg.idx = idx;
1983
1984         if (idx == EXTRA_REG_RSP_0) {
1985                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1986                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1987                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1988         } else if (idx == EXTRA_REG_RSP_1) {
1989                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1990                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1991                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1992         }
1993 }
1994
1995 /*
1996  * manage allocation of shared extra msr for certain events
1997  *
1998  * sharing can be:
1999  * per-cpu: to be shared between the various events on a single PMU
2000  * per-core: per-cpu + shared by HT threads
2001  */
2002 static struct event_constraint *
2003 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2004                                    struct perf_event *event,
2005                                    struct hw_perf_event_extra *reg)
2006 {
2007         struct event_constraint *c = &emptyconstraint;
2008         struct er_account *era;
2009         unsigned long flags;
2010         int idx = reg->idx;
2011
2012         /*
2013          * reg->alloc can be set due to existing state, so for fake cpuc we
2014          * need to ignore this, otherwise we might fail to allocate proper fake
2015          * state for this extra reg constraint. Also see the comment below.
2016          */
2017         if (reg->alloc && !cpuc->is_fake)
2018                 return NULL; /* call x86_get_event_constraint() */
2019
2020 again:
2021         era = &cpuc->shared_regs->regs[idx];
2022         /*
2023          * we use spin_lock_irqsave() to avoid lockdep issues when
2024          * passing a fake cpuc
2025          */
2026         raw_spin_lock_irqsave(&era->lock, flags);
2027
2028         if (!atomic_read(&era->ref) || era->config == reg->config) {
2029
2030                 /*
2031                  * If its a fake cpuc -- as per validate_{group,event}() we
2032                  * shouldn't touch event state and we can avoid doing so
2033                  * since both will only call get_event_constraints() once
2034                  * on each event, this avoids the need for reg->alloc.
2035                  *
2036                  * Not doing the ER fixup will only result in era->reg being
2037                  * wrong, but since we won't actually try and program hardware
2038                  * this isn't a problem either.
2039                  */
2040                 if (!cpuc->is_fake) {
2041                         if (idx != reg->idx)
2042                                 intel_fixup_er(event, idx);
2043
2044                         /*
2045                          * x86_schedule_events() can call get_event_constraints()
2046                          * multiple times on events in the case of incremental
2047                          * scheduling(). reg->alloc ensures we only do the ER
2048                          * allocation once.
2049                          */
2050                         reg->alloc = 1;
2051                 }
2052
2053                 /* lock in msr value */
2054                 era->config = reg->config;
2055                 era->reg = reg->reg;
2056
2057                 /* one more user */
2058                 atomic_inc(&era->ref);
2059
2060                 /*
2061                  * need to call x86_get_event_constraint()
2062                  * to check if associated event has constraints
2063                  */
2064                 c = NULL;
2065         } else {
2066                 idx = intel_alt_er(idx, reg->config);
2067                 if (idx != reg->idx) {
2068                         raw_spin_unlock_irqrestore(&era->lock, flags);
2069                         goto again;
2070                 }
2071         }
2072         raw_spin_unlock_irqrestore(&era->lock, flags);
2073
2074         return c;
2075 }
2076
2077 static void
2078 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2079                                    struct hw_perf_event_extra *reg)
2080 {
2081         struct er_account *era;
2082
2083         /*
2084          * Only put constraint if extra reg was actually allocated. Also takes
2085          * care of event which do not use an extra shared reg.
2086          *
2087          * Also, if this is a fake cpuc we shouldn't touch any event state
2088          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2089          * either since it'll be thrown out.
2090          */
2091         if (!reg->alloc || cpuc->is_fake)
2092                 return;
2093
2094         era = &cpuc->shared_regs->regs[reg->idx];
2095
2096         /* one fewer user */
2097         atomic_dec(&era->ref);
2098
2099         /* allocate again next time */
2100         reg->alloc = 0;
2101 }
2102
2103 static struct event_constraint *
2104 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2105                               struct perf_event *event)
2106 {
2107         struct event_constraint *c = NULL, *d;
2108         struct hw_perf_event_extra *xreg, *breg;
2109
2110         xreg = &event->hw.extra_reg;
2111         if (xreg->idx != EXTRA_REG_NONE) {
2112                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2113                 if (c == &emptyconstraint)
2114                         return c;
2115         }
2116         breg = &event->hw.branch_reg;
2117         if (breg->idx != EXTRA_REG_NONE) {
2118                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2119                 if (d == &emptyconstraint) {
2120                         __intel_shared_reg_put_constraints(cpuc, xreg);
2121                         c = d;
2122                 }
2123         }
2124         return c;
2125 }
2126
2127 struct event_constraint *
2128 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2129                           struct perf_event *event)
2130 {
2131         struct event_constraint *c;
2132
2133         if (x86_pmu.event_constraints) {
2134                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2135                         if ((event->hw.config & c->cmask) == c->code) {
2136                                 event->hw.flags |= c->flags;
2137                                 return c;
2138                         }
2139                 }
2140         }
2141
2142         return &unconstrained;
2143 }
2144
2145 static struct event_constraint *
2146 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2147                             struct perf_event *event)
2148 {
2149         struct event_constraint *c;
2150
2151         c = intel_bts_constraints(event);
2152         if (c)
2153                 return c;
2154
2155         c = intel_shared_regs_constraints(cpuc, event);
2156         if (c)
2157                 return c;
2158
2159         c = intel_pebs_constraints(event);
2160         if (c)
2161                 return c;
2162
2163         return x86_get_event_constraints(cpuc, idx, event);
2164 }
2165
2166 static void
2167 intel_start_scheduling(struct cpu_hw_events *cpuc)
2168 {
2169         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2170         struct intel_excl_states *xl;
2171         int tid = cpuc->excl_thread_id;
2172
2173         /*
2174          * nothing needed if in group validation mode
2175          */
2176         if (cpuc->is_fake || !is_ht_workaround_enabled())
2177                 return;
2178
2179         /*
2180          * no exclusion needed
2181          */
2182         if (WARN_ON_ONCE(!excl_cntrs))
2183                 return;
2184
2185         xl = &excl_cntrs->states[tid];
2186
2187         xl->sched_started = true;
2188         /*
2189          * lock shared state until we are done scheduling
2190          * in stop_event_scheduling()
2191          * makes scheduling appear as a transaction
2192          */
2193         raw_spin_lock(&excl_cntrs->lock);
2194 }
2195
2196 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2197 {
2198         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2199         struct event_constraint *c = cpuc->event_constraint[idx];
2200         struct intel_excl_states *xl;
2201         int tid = cpuc->excl_thread_id;
2202
2203         if (cpuc->is_fake || !is_ht_workaround_enabled())
2204                 return;
2205
2206         if (WARN_ON_ONCE(!excl_cntrs))
2207                 return;
2208
2209         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2210                 return;
2211
2212         xl = &excl_cntrs->states[tid];
2213
2214         lockdep_assert_held(&excl_cntrs->lock);
2215
2216         if (c->flags & PERF_X86_EVENT_EXCL)
2217                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2218         else
2219                 xl->state[cntr] = INTEL_EXCL_SHARED;
2220 }
2221
2222 static void
2223 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2224 {
2225         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2226         struct intel_excl_states *xl;
2227         int tid = cpuc->excl_thread_id;
2228
2229         /*
2230          * nothing needed if in group validation mode
2231          */
2232         if (cpuc->is_fake || !is_ht_workaround_enabled())
2233                 return;
2234         /*
2235          * no exclusion needed
2236          */
2237         if (WARN_ON_ONCE(!excl_cntrs))
2238                 return;
2239
2240         xl = &excl_cntrs->states[tid];
2241
2242         xl->sched_started = false;
2243         /*
2244          * release shared state lock (acquired in intel_start_scheduling())
2245          */
2246         raw_spin_unlock(&excl_cntrs->lock);
2247 }
2248
2249 static struct event_constraint *
2250 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2251                            int idx, struct event_constraint *c)
2252 {
2253         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2254         struct intel_excl_states *xlo;
2255         int tid = cpuc->excl_thread_id;
2256         int is_excl, i;
2257
2258         /*
2259          * validating a group does not require
2260          * enforcing cross-thread  exclusion
2261          */
2262         if (cpuc->is_fake || !is_ht_workaround_enabled())
2263                 return c;
2264
2265         /*
2266          * no exclusion needed
2267          */
2268         if (WARN_ON_ONCE(!excl_cntrs))
2269                 return c;
2270
2271         /*
2272          * because we modify the constraint, we need
2273          * to make a copy. Static constraints come
2274          * from static const tables.
2275          *
2276          * only needed when constraint has not yet
2277          * been cloned (marked dynamic)
2278          */
2279         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2280                 struct event_constraint *cx;
2281
2282                 /*
2283                  * grab pre-allocated constraint entry
2284                  */
2285                 cx = &cpuc->constraint_list[idx];
2286
2287                 /*
2288                  * initialize dynamic constraint
2289                  * with static constraint
2290                  */
2291                 *cx = *c;
2292
2293                 /*
2294                  * mark constraint as dynamic, so we
2295                  * can free it later on
2296                  */
2297                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2298                 c = cx;
2299         }
2300
2301         /*
2302          * From here on, the constraint is dynamic.
2303          * Either it was just allocated above, or it
2304          * was allocated during a earlier invocation
2305          * of this function
2306          */
2307
2308         /*
2309          * state of sibling HT
2310          */
2311         xlo = &excl_cntrs->states[tid ^ 1];
2312
2313         /*
2314          * event requires exclusive counter access
2315          * across HT threads
2316          */
2317         is_excl = c->flags & PERF_X86_EVENT_EXCL;
2318         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2319                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2320                 if (!cpuc->n_excl++)
2321                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2322         }
2323
2324         /*
2325          * Modify static constraint with current dynamic
2326          * state of thread
2327          *
2328          * EXCLUSIVE: sibling counter measuring exclusive event
2329          * SHARED   : sibling counter measuring non-exclusive event
2330          * UNUSED   : sibling counter unused
2331          */
2332         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2333                 /*
2334                  * exclusive event in sibling counter
2335                  * our corresponding counter cannot be used
2336                  * regardless of our event
2337                  */
2338                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2339                         __clear_bit(i, c->idxmsk);
2340                 /*
2341                  * if measuring an exclusive event, sibling
2342                  * measuring non-exclusive, then counter cannot
2343                  * be used
2344                  */
2345                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2346                         __clear_bit(i, c->idxmsk);
2347         }
2348
2349         /*
2350          * recompute actual bit weight for scheduling algorithm
2351          */
2352         c->weight = hweight64(c->idxmsk64);
2353
2354         /*
2355          * if we return an empty mask, then switch
2356          * back to static empty constraint to avoid
2357          * the cost of freeing later on
2358          */
2359         if (c->weight == 0)
2360                 c = &emptyconstraint;
2361
2362         return c;
2363 }
2364
2365 static struct event_constraint *
2366 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2367                             struct perf_event *event)
2368 {
2369         struct event_constraint *c1 = NULL;
2370         struct event_constraint *c2;
2371
2372         if (idx >= 0) /* fake does < 0 */
2373                 c1 = cpuc->event_constraint[idx];
2374
2375         /*
2376          * first time only
2377          * - static constraint: no change across incremental scheduling calls
2378          * - dynamic constraint: handled by intel_get_excl_constraints()
2379          */
2380         c2 = __intel_get_event_constraints(cpuc, idx, event);
2381         if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2382                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2383                 c1->weight = c2->weight;
2384                 c2 = c1;
2385         }
2386
2387         if (cpuc->excl_cntrs)
2388                 return intel_get_excl_constraints(cpuc, event, idx, c2);
2389
2390         return c2;
2391 }
2392
2393 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2394                 struct perf_event *event)
2395 {
2396         struct hw_perf_event *hwc = &event->hw;
2397         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2398         int tid = cpuc->excl_thread_id;
2399         struct intel_excl_states *xl;
2400
2401         /*
2402          * nothing needed if in group validation mode
2403          */
2404         if (cpuc->is_fake)
2405                 return;
2406
2407         if (WARN_ON_ONCE(!excl_cntrs))
2408                 return;
2409
2410         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2411                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2412                 if (!--cpuc->n_excl)
2413                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2414         }
2415
2416         /*
2417          * If event was actually assigned, then mark the counter state as
2418          * unused now.
2419          */
2420         if (hwc->idx >= 0) {
2421                 xl = &excl_cntrs->states[tid];
2422
2423                 /*
2424                  * put_constraint may be called from x86_schedule_events()
2425                  * which already has the lock held so here make locking
2426                  * conditional.
2427                  */
2428                 if (!xl->sched_started)
2429                         raw_spin_lock(&excl_cntrs->lock);
2430
2431                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2432
2433                 if (!xl->sched_started)
2434                         raw_spin_unlock(&excl_cntrs->lock);
2435         }
2436 }
2437
2438 static void
2439 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2440                                         struct perf_event *event)
2441 {
2442         struct hw_perf_event_extra *reg;
2443
2444         reg = &event->hw.extra_reg;
2445         if (reg->idx != EXTRA_REG_NONE)
2446                 __intel_shared_reg_put_constraints(cpuc, reg);
2447
2448         reg = &event->hw.branch_reg;
2449         if (reg->idx != EXTRA_REG_NONE)
2450                 __intel_shared_reg_put_constraints(cpuc, reg);
2451 }
2452
2453 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2454                                         struct perf_event *event)
2455 {
2456         intel_put_shared_regs_event_constraints(cpuc, event);
2457
2458         /*
2459          * is PMU has exclusive counter restrictions, then
2460          * all events are subject to and must call the
2461          * put_excl_constraints() routine
2462          */
2463         if (cpuc->excl_cntrs)
2464                 intel_put_excl_constraints(cpuc, event);
2465 }
2466
2467 static void intel_pebs_aliases_core2(struct perf_event *event)
2468 {
2469         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2470                 /*
2471                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2472                  * (0x003c) so that we can use it with PEBS.
2473                  *
2474                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2475                  * PEBS capable. However we can use INST_RETIRED.ANY_P
2476                  * (0x00c0), which is a PEBS capable event, to get the same
2477                  * count.
2478                  *
2479                  * INST_RETIRED.ANY_P counts the number of cycles that retires
2480                  * CNTMASK instructions. By setting CNTMASK to a value (16)
2481                  * larger than the maximum number of instructions that can be
2482                  * retired per cycle (4) and then inverting the condition, we
2483                  * count all cycles that retire 16 or less instructions, which
2484                  * is every cycle.
2485                  *
2486                  * Thereby we gain a PEBS capable cycle counter.
2487                  */
2488                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2489
2490                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2491                 event->hw.config = alt_config;
2492         }
2493 }
2494
2495 static void intel_pebs_aliases_snb(struct perf_event *event)
2496 {
2497         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2498                 /*
2499                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2500                  * (0x003c) so that we can use it with PEBS.
2501                  *
2502                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2503                  * PEBS capable. However we can use UOPS_RETIRED.ALL
2504                  * (0x01c2), which is a PEBS capable event, to get the same
2505                  * count.
2506                  *
2507                  * UOPS_RETIRED.ALL counts the number of cycles that retires
2508                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2509                  * larger than the maximum number of micro-ops that can be
2510                  * retired per cycle (4) and then inverting the condition, we
2511                  * count all cycles that retire 16 or less micro-ops, which
2512                  * is every cycle.
2513                  *
2514                  * Thereby we gain a PEBS capable cycle counter.
2515                  */
2516                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2517
2518                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2519                 event->hw.config = alt_config;
2520         }
2521 }
2522
2523 static void intel_pebs_aliases_precdist(struct perf_event *event)
2524 {
2525         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2526                 /*
2527                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2528                  * (0x003c) so that we can use it with PEBS.
2529                  *
2530                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2531                  * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2532                  * (0x01c0), which is a PEBS capable event, to get the same
2533                  * count.
2534                  *
2535                  * The PREC_DIST event has special support to minimize sample
2536                  * shadowing effects. One drawback is that it can be
2537                  * only programmed on counter 1, but that seems like an
2538                  * acceptable trade off.
2539                  */
2540                 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2541
2542                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2543                 event->hw.config = alt_config;
2544         }
2545 }
2546
2547 static void intel_pebs_aliases_ivb(struct perf_event *event)
2548 {
2549         if (event->attr.precise_ip < 3)
2550                 return intel_pebs_aliases_snb(event);
2551         return intel_pebs_aliases_precdist(event);
2552 }
2553
2554 static void intel_pebs_aliases_skl(struct perf_event *event)
2555 {
2556         if (event->attr.precise_ip < 3)
2557                 return intel_pebs_aliases_core2(event);
2558         return intel_pebs_aliases_precdist(event);
2559 }
2560
2561 static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2562 {
2563         unsigned long flags = x86_pmu.free_running_flags;
2564
2565         if (event->attr.use_clockid)
2566                 flags &= ~PERF_SAMPLE_TIME;
2567         return flags;
2568 }
2569
2570 static int intel_pmu_hw_config(struct perf_event *event)
2571 {
2572         int ret = x86_pmu_hw_config(event);
2573
2574         if (ret)
2575                 return ret;
2576
2577         if (event->attr.precise_ip) {
2578                 if (!event->attr.freq) {
2579                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2580                         if (!(event->attr.sample_type &
2581                               ~intel_pmu_free_running_flags(event)))
2582                                 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2583                 }
2584                 if (x86_pmu.pebs_aliases)
2585                         x86_pmu.pebs_aliases(event);
2586         }
2587
2588         if (needs_branch_stack(event)) {
2589                 ret = intel_pmu_setup_lbr_filter(event);
2590                 if (ret)
2591                         return ret;
2592
2593                 /*
2594                  * BTS is set up earlier in this path, so don't account twice
2595                  */
2596                 if (!intel_pmu_has_bts(event)) {
2597                         /* disallow lbr if conflicting events are present */
2598                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2599                                 return -EBUSY;
2600
2601                         event->destroy = hw_perf_lbr_event_destroy;
2602                 }
2603         }
2604
2605         if (event->attr.type != PERF_TYPE_RAW)
2606                 return 0;
2607
2608         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2609                 return 0;
2610
2611         if (x86_pmu.version < 3)
2612                 return -EINVAL;
2613
2614         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2615                 return -EACCES;
2616
2617         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2618
2619         return 0;
2620 }
2621
2622 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2623 {
2624         if (x86_pmu.guest_get_msrs)
2625                 return x86_pmu.guest_get_msrs(nr);
2626         *nr = 0;
2627         return NULL;
2628 }
2629 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2630
2631 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2632 {
2633         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2634         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2635
2636         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2637         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2638         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2639         /*
2640          * If PMU counter has PEBS enabled it is not enough to disable counter
2641          * on a guest entry since PEBS memory write can overshoot guest entry
2642          * and corrupt guest memory. Disabling PEBS solves the problem.
2643          */
2644         arr[1].msr = MSR_IA32_PEBS_ENABLE;
2645         arr[1].host = cpuc->pebs_enabled;
2646         arr[1].guest = 0;
2647
2648         *nr = 2;
2649         return arr;
2650 }
2651
2652 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2653 {
2654         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2655         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2656         int idx;
2657
2658         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
2659                 struct perf_event *event = cpuc->events[idx];
2660
2661                 arr[idx].msr = x86_pmu_config_addr(idx);
2662                 arr[idx].host = arr[idx].guest = 0;
2663
2664                 if (!test_bit(idx, cpuc->active_mask))
2665                         continue;
2666
2667                 arr[idx].host = arr[idx].guest =
2668                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2669
2670                 if (event->attr.exclude_host)
2671                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2672                 else if (event->attr.exclude_guest)
2673                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2674         }
2675
2676         *nr = x86_pmu.num_counters;
2677         return arr;
2678 }
2679
2680 static void core_pmu_enable_event(struct perf_event *event)
2681 {
2682         if (!event->attr.exclude_host)
2683                 x86_pmu_enable_event(event);
2684 }
2685
2686 static void core_pmu_enable_all(int added)
2687 {
2688         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2689         int idx;
2690
2691         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2692                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2693
2694                 if (!test_bit(idx, cpuc->active_mask) ||
2695                                 cpuc->events[idx]->attr.exclude_host)
2696                         continue;
2697
2698                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2699         }
2700 }
2701
2702 static int hsw_hw_config(struct perf_event *event)
2703 {
2704         int ret = intel_pmu_hw_config(event);
2705
2706         if (ret)
2707                 return ret;
2708         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2709                 return 0;
2710         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2711
2712         /*
2713          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2714          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2715          * this combination.
2716          */
2717         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2718              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2719               event->attr.precise_ip > 0))
2720                 return -EOPNOTSUPP;
2721
2722         if (event_is_checkpointed(event)) {
2723                 /*
2724                  * Sampling of checkpointed events can cause situations where
2725                  * the CPU constantly aborts because of a overflow, which is
2726                  * then checkpointed back and ignored. Forbid checkpointing
2727                  * for sampling.
2728                  *
2729                  * But still allow a long sampling period, so that perf stat
2730                  * from KVM works.
2731                  */
2732                 if (event->attr.sample_period > 0 &&
2733                     event->attr.sample_period < 0x7fffffff)
2734                         return -EOPNOTSUPP;
2735         }
2736         return 0;
2737 }
2738
2739 static struct event_constraint counter2_constraint =
2740                         EVENT_CONSTRAINT(0, 0x4, 0);
2741
2742 static struct event_constraint *
2743 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2744                           struct perf_event *event)
2745 {
2746         struct event_constraint *c;
2747
2748         c = intel_get_event_constraints(cpuc, idx, event);
2749
2750         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2751         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2752                 if (c->idxmsk64 & (1U << 2))
2753                         return &counter2_constraint;
2754                 return &emptyconstraint;
2755         }
2756
2757         return c;
2758 }
2759
2760 /*
2761  * Broadwell:
2762  *
2763  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2764  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2765  * the two to enforce a minimum period of 128 (the smallest value that has bits
2766  * 0-5 cleared and >= 100).
2767  *
2768  * Because of how the code in x86_perf_event_set_period() works, the truncation
2769  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2770  * to make up for the 'lost' events due to carrying the 'error' in period_left.
2771  *
2772  * Therefore the effective (average) period matches the requested period,
2773  * despite coarser hardware granularity.
2774  */
2775 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2776 {
2777         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2778                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
2779                 if (left < 128)
2780                         left = 128;
2781                 left &= ~0x3fu;
2782         }
2783         return left;
2784 }
2785
2786 PMU_FORMAT_ATTR(event,  "config:0-7"    );
2787 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
2788 PMU_FORMAT_ATTR(edge,   "config:18"     );
2789 PMU_FORMAT_ATTR(pc,     "config:19"     );
2790 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
2791 PMU_FORMAT_ATTR(inv,    "config:23"     );
2792 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
2793 PMU_FORMAT_ATTR(in_tx,  "config:32");
2794 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2795
2796 static struct attribute *intel_arch_formats_attr[] = {
2797         &format_attr_event.attr,
2798         &format_attr_umask.attr,
2799         &format_attr_edge.attr,
2800         &format_attr_pc.attr,
2801         &format_attr_inv.attr,
2802         &format_attr_cmask.attr,
2803         NULL,
2804 };
2805
2806 ssize_t intel_event_sysfs_show(char *page, u64 config)
2807 {
2808         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2809
2810         return x86_event_sysfs_show(page, config, event);
2811 }
2812
2813 struct intel_shared_regs *allocate_shared_regs(int cpu)
2814 {
2815         struct intel_shared_regs *regs;
2816         int i;
2817
2818         regs = kzalloc_node(sizeof(struct intel_shared_regs),
2819                             GFP_KERNEL, cpu_to_node(cpu));
2820         if (regs) {
2821                 /*
2822                  * initialize the locks to keep lockdep happy
2823                  */
2824                 for (i = 0; i < EXTRA_REG_MAX; i++)
2825                         raw_spin_lock_init(&regs->regs[i].lock);
2826
2827                 regs->core_id = -1;
2828         }
2829         return regs;
2830 }
2831
2832 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2833 {
2834         struct intel_excl_cntrs *c;
2835
2836         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2837                          GFP_KERNEL, cpu_to_node(cpu));
2838         if (c) {
2839                 raw_spin_lock_init(&c->lock);
2840                 c->core_id = -1;
2841         }
2842         return c;
2843 }
2844
2845 static int intel_pmu_cpu_prepare(int cpu)
2846 {
2847         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2848
2849         if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2850                 cpuc->shared_regs = allocate_shared_regs(cpu);
2851                 if (!cpuc->shared_regs)
2852                         goto err;
2853         }
2854
2855         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2856                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2857
2858                 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2859                 if (!cpuc->constraint_list)
2860                         goto err_shared_regs;
2861
2862                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2863                 if (!cpuc->excl_cntrs)
2864                         goto err_constraint_list;
2865
2866                 cpuc->excl_thread_id = 0;
2867         }
2868
2869         return NOTIFY_OK;
2870
2871 err_constraint_list:
2872         kfree(cpuc->constraint_list);
2873         cpuc->constraint_list = NULL;
2874
2875 err_shared_regs:
2876         kfree(cpuc->shared_regs);
2877         cpuc->shared_regs = NULL;
2878
2879 err:
2880         return NOTIFY_BAD;
2881 }
2882
2883 static void intel_pmu_cpu_starting(int cpu)
2884 {
2885         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2886         int core_id = topology_core_id(cpu);
2887         int i;
2888
2889         init_debug_store_on_cpu(cpu);
2890         /*
2891          * Deal with CPUs that don't clear their LBRs on power-up.
2892          */
2893         intel_pmu_lbr_reset();
2894
2895         cpuc->lbr_sel = NULL;
2896
2897         if (!cpuc->shared_regs)
2898                 return;
2899
2900         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
2901                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2902                         struct intel_shared_regs *pc;
2903
2904                         pc = per_cpu(cpu_hw_events, i).shared_regs;
2905                         if (pc && pc->core_id == core_id) {
2906                                 cpuc->kfree_on_online[0] = cpuc->shared_regs;
2907                                 cpuc->shared_regs = pc;
2908                                 break;
2909                         }
2910                 }
2911                 cpuc->shared_regs->core_id = core_id;
2912                 cpuc->shared_regs->refcnt++;
2913         }
2914
2915         if (x86_pmu.lbr_sel_map)
2916                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2917
2918         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2919                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
2920                         struct intel_excl_cntrs *c;
2921
2922                         c = per_cpu(cpu_hw_events, i).excl_cntrs;
2923                         if (c && c->core_id == core_id) {
2924                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2925                                 cpuc->excl_cntrs = c;
2926                                 cpuc->excl_thread_id = 1;
2927                                 break;
2928                         }
2929                 }
2930                 cpuc->excl_cntrs->core_id = core_id;
2931                 cpuc->excl_cntrs->refcnt++;
2932         }
2933 }
2934
2935 static void free_excl_cntrs(int cpu)
2936 {
2937         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2938         struct intel_excl_cntrs *c;
2939
2940         c = cpuc->excl_cntrs;
2941         if (c) {
2942                 if (c->core_id == -1 || --c->refcnt == 0)
2943                         kfree(c);
2944                 cpuc->excl_cntrs = NULL;
2945                 kfree(cpuc->constraint_list);
2946                 cpuc->constraint_list = NULL;
2947         }
2948 }
2949
2950 static void intel_pmu_cpu_dying(int cpu)
2951 {
2952         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2953         struct intel_shared_regs *pc;
2954
2955         pc = cpuc->shared_regs;
2956         if (pc) {
2957                 if (pc->core_id == -1 || --pc->refcnt == 0)
2958                         kfree(pc);
2959                 cpuc->shared_regs = NULL;
2960         }
2961
2962         free_excl_cntrs(cpu);
2963
2964         fini_debug_store_on_cpu(cpu);
2965 }
2966
2967 static void intel_pmu_sched_task(struct perf_event_context *ctx,
2968                                  bool sched_in)
2969 {
2970         if (x86_pmu.pebs_active)
2971                 intel_pmu_pebs_sched_task(ctx, sched_in);
2972         if (x86_pmu.lbr_nr)
2973                 intel_pmu_lbr_sched_task(ctx, sched_in);
2974 }
2975
2976 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2977
2978 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2979
2980 PMU_FORMAT_ATTR(frontend, "config1:0-23");
2981
2982 static struct attribute *intel_arch3_formats_attr[] = {
2983         &format_attr_event.attr,
2984         &format_attr_umask.attr,
2985         &format_attr_edge.attr,
2986         &format_attr_pc.attr,
2987         &format_attr_any.attr,
2988         &format_attr_inv.attr,
2989         &format_attr_cmask.attr,
2990         &format_attr_in_tx.attr,
2991         &format_attr_in_tx_cp.attr,
2992
2993         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2994         &format_attr_ldlat.attr, /* PEBS load latency */
2995         NULL,
2996 };
2997
2998 static struct attribute *skl_format_attr[] = {
2999         &format_attr_frontend.attr,
3000         NULL,
3001 };
3002
3003 static __initconst const struct x86_pmu core_pmu = {
3004         .name                   = "core",
3005         .handle_irq             = x86_pmu_handle_irq,
3006         .disable_all            = x86_pmu_disable_all,
3007         .enable_all             = core_pmu_enable_all,
3008         .enable                 = core_pmu_enable_event,
3009         .disable                = x86_pmu_disable_event,
3010         .hw_config              = x86_pmu_hw_config,
3011         .schedule_events        = x86_schedule_events,
3012         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
3013         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
3014         .event_map              = intel_pmu_event_map,
3015         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
3016         .apic                   = 1,
3017         .free_running_flags     = PEBS_FREERUNNING_FLAGS,
3018
3019         /*
3020          * Intel PMCs cannot be accessed sanely above 32-bit width,
3021          * so we install an artificial 1<<31 period regardless of
3022          * the generic event period:
3023          */
3024         .max_period             = (1ULL<<31) - 1,
3025         .get_event_constraints  = intel_get_event_constraints,
3026         .put_event_constraints  = intel_put_event_constraints,
3027         .event_constraints      = intel_core_event_constraints,
3028         .guest_get_msrs         = core_guest_get_msrs,
3029         .format_attrs           = intel_arch_formats_attr,
3030         .events_sysfs_show      = intel_event_sysfs_show,
3031
3032         /*
3033          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3034          * together with PMU version 1 and thus be using core_pmu with
3035          * shared_regs. We need following callbacks here to allocate
3036          * it properly.
3037          */
3038         .cpu_prepare            = intel_pmu_cpu_prepare,
3039         .cpu_starting           = intel_pmu_cpu_starting,
3040         .cpu_dying              = intel_pmu_cpu_dying,
3041 };
3042
3043 static __initconst const struct x86_pmu intel_pmu = {
3044         .name                   = "Intel",
3045         .handle_irq             = intel_pmu_handle_irq,
3046         .disable_all            = intel_pmu_disable_all,
3047         .enable_all             = intel_pmu_enable_all,
3048         .enable                 = intel_pmu_enable_event,
3049         .disable                = intel_pmu_disable_event,
3050         .hw_config              = intel_pmu_hw_config,
3051         .schedule_events        = x86_schedule_events,
3052         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
3053         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
3054         .event_map              = intel_pmu_event_map,
3055         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
3056         .apic                   = 1,
3057         .free_running_flags     = PEBS_FREERUNNING_FLAGS,
3058         /*
3059          * Intel PMCs cannot be accessed sanely above 32 bit width,
3060          * so we install an artificial 1<<31 period regardless of
3061          * the generic event period:
3062          */
3063         .max_period             = (1ULL << 31) - 1,
3064         .get_event_constraints  = intel_get_event_constraints,
3065         .put_event_constraints  = intel_put_event_constraints,
3066         .pebs_aliases           = intel_pebs_aliases_core2,
3067
3068         .format_attrs           = intel_arch3_formats_attr,
3069         .events_sysfs_show      = intel_event_sysfs_show,
3070
3071         .cpu_prepare            = intel_pmu_cpu_prepare,
3072         .cpu_starting           = intel_pmu_cpu_starting,
3073         .cpu_dying              = intel_pmu_cpu_dying,
3074         .guest_get_msrs         = intel_guest_get_msrs,
3075         .sched_task             = intel_pmu_sched_task,
3076 };
3077
3078 static __init void intel_clovertown_quirk(void)
3079 {
3080         /*
3081          * PEBS is unreliable due to:
3082          *
3083          *   AJ67  - PEBS may experience CPL leaks
3084          *   AJ68  - PEBS PMI may be delayed by one event
3085          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3086          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3087          *
3088          * AJ67 could be worked around by restricting the OS/USR flags.
3089          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3090          *
3091          * AJ106 could possibly be worked around by not allowing LBR
3092          *       usage from PEBS, including the fixup.
3093          * AJ68  could possibly be worked around by always programming
3094          *       a pebs_event_reset[0] value and coping with the lost events.
3095          *
3096          * But taken together it might just make sense to not enable PEBS on
3097          * these chips.
3098          */
3099         pr_warn("PEBS disabled due to CPU errata\n");
3100         x86_pmu.pebs = 0;
3101         x86_pmu.pebs_constraints = NULL;
3102 }
3103
3104 static int intel_snb_pebs_broken(int cpu)
3105 {
3106         u32 rev = UINT_MAX; /* default to broken for unknown models */
3107
3108         switch (cpu_data(cpu).x86_model) {
3109         case 42: /* SNB */
3110                 rev = 0x28;
3111                 break;
3112
3113         case 45: /* SNB-EP */
3114                 switch (cpu_data(cpu).x86_mask) {
3115                 case 6: rev = 0x618; break;
3116                 case 7: rev = 0x70c; break;
3117                 }
3118         }
3119
3120         return (cpu_data(cpu).microcode < rev);
3121 }
3122
3123 static void intel_snb_check_microcode(void)
3124 {
3125         int pebs_broken = 0;
3126         int cpu;
3127
3128         get_online_cpus();
3129         for_each_online_cpu(cpu) {
3130                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3131                         break;
3132         }
3133         put_online_cpus();
3134
3135         if (pebs_broken == x86_pmu.pebs_broken)
3136                 return;
3137
3138         /*
3139          * Serialized by the microcode lock..
3140          */
3141         if (x86_pmu.pebs_broken) {
3142                 pr_info("PEBS enabled due to microcode update\n");
3143                 x86_pmu.pebs_broken = 0;
3144         } else {
3145                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3146                 x86_pmu.pebs_broken = 1;
3147         }
3148 }
3149
3150 /*
3151  * Under certain circumstances, access certain MSR may cause #GP.
3152  * The function tests if the input MSR can be safely accessed.
3153  */
3154 static bool check_msr(unsigned long msr, u64 mask)
3155 {
3156         u64 val_old, val_new, val_tmp;
3157
3158         /*
3159          * Read the current value, change it and read it back to see if it
3160          * matches, this is needed to detect certain hardware emulators
3161          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3162          */
3163         if (rdmsrl_safe(msr, &val_old))
3164                 return false;
3165
3166         /*
3167          * Only change the bits which can be updated by wrmsrl.
3168          */
3169         val_tmp = val_old ^ mask;
3170         if (wrmsrl_safe(msr, val_tmp) ||
3171             rdmsrl_safe(msr, &val_new))
3172                 return false;
3173
3174         if (val_new != val_tmp)
3175                 return false;
3176
3177         /* Here it's sure that the MSR can be safely accessed.
3178          * Restore the old value and return.
3179          */
3180         wrmsrl(msr, val_old);
3181
3182         return true;
3183 }
3184
3185 static __init void intel_sandybridge_quirk(void)
3186 {
3187         x86_pmu.check_microcode = intel_snb_check_microcode;
3188         intel_snb_check_microcode();
3189 }
3190
3191 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3192         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3193         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3194         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3195         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3196         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3197         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3198         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3199 };
3200
3201 static __init void intel_arch_events_quirk(void)
3202 {
3203         int bit;
3204
3205         /* disable event that reported as not presend by cpuid */
3206         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3207                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3208                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3209                         intel_arch_events_map[bit].name);
3210         }
3211 }
3212
3213 static __init void intel_nehalem_quirk(void)
3214 {
3215         union cpuid10_ebx ebx;
3216
3217         ebx.full = x86_pmu.events_maskl;
3218         if (ebx.split.no_branch_misses_retired) {
3219                 /*
3220                  * Erratum AAJ80 detected, we work it around by using
3221                  * the BR_MISP_EXEC.ANY event. This will over-count
3222                  * branch-misses, but it's still much better than the
3223                  * architectural event which is often completely bogus:
3224                  */
3225                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3226                 ebx.split.no_branch_misses_retired = 0;
3227                 x86_pmu.events_maskl = ebx.full;
3228                 pr_info("CPU erratum AAJ80 worked around\n");
3229         }
3230 }
3231
3232 /*
3233  * enable software workaround for errata:
3234  * SNB: BJ122
3235  * IVB: BV98
3236  * HSW: HSD29
3237  *
3238  * Only needed when HT is enabled. However detecting
3239  * if HT is enabled is difficult (model specific). So instead,
3240  * we enable the workaround in the early boot, and verify if
3241  * it is needed in a later initcall phase once we have valid
3242  * topology information to check if HT is actually enabled
3243  */
3244 static __init void intel_ht_bug(void)
3245 {
3246         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3247
3248         x86_pmu.start_scheduling = intel_start_scheduling;
3249         x86_pmu.commit_scheduling = intel_commit_scheduling;
3250         x86_pmu.stop_scheduling = intel_stop_scheduling;
3251 }
3252
3253 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
3254 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
3255
3256 /* Haswell special events */
3257 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
3258 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
3259 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
3260 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
3261 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
3262 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
3263 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
3264 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
3265 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
3266 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
3267 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
3268 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
3269
3270 static struct attribute *hsw_events_attrs[] = {
3271         EVENT_PTR(tx_start),
3272         EVENT_PTR(tx_commit),
3273         EVENT_PTR(tx_abort),
3274         EVENT_PTR(tx_capacity),
3275         EVENT_PTR(tx_conflict),
3276         EVENT_PTR(el_start),
3277         EVENT_PTR(el_commit),
3278         EVENT_PTR(el_abort),
3279         EVENT_PTR(el_capacity),
3280         EVENT_PTR(el_conflict),
3281         EVENT_PTR(cycles_t),
3282         EVENT_PTR(cycles_ct),
3283         EVENT_PTR(mem_ld_hsw),
3284         EVENT_PTR(mem_st_hsw),
3285         NULL
3286 };
3287
3288 __init int intel_pmu_init(void)
3289 {
3290         union cpuid10_edx edx;
3291         union cpuid10_eax eax;
3292         union cpuid10_ebx ebx;
3293         struct event_constraint *c;
3294         unsigned int unused;
3295         struct extra_reg *er;
3296         int version, i;
3297
3298         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3299                 switch (boot_cpu_data.x86) {
3300                 case 0x6:
3301                         return p6_pmu_init();
3302                 case 0xb:
3303                         return knc_pmu_init();
3304                 case 0xf:
3305                         return p4_pmu_init();
3306                 }
3307                 return -ENODEV;
3308         }
3309
3310         /*
3311          * Check whether the Architectural PerfMon supports
3312          * Branch Misses Retired hw_event or not.
3313          */
3314         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3315         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3316                 return -ENODEV;
3317
3318         version = eax.split.version_id;
3319         if (version < 2)
3320                 x86_pmu = core_pmu;
3321         else
3322                 x86_pmu = intel_pmu;
3323
3324         x86_pmu.version                 = version;
3325         x86_pmu.num_counters            = eax.split.num_counters;
3326         x86_pmu.cntval_bits             = eax.split.bit_width;
3327         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
3328
3329         x86_pmu.events_maskl            = ebx.full;
3330         x86_pmu.events_mask_len         = eax.split.mask_length;
3331
3332         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3333
3334         /*
3335          * Quirk: v2 perfmon does not report fixed-purpose events, so
3336          * assume at least 3 events:
3337          */
3338         if (version > 1)
3339                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
3340
3341         if (boot_cpu_has(X86_FEATURE_PDCM)) {
3342                 u64 capabilities;
3343
3344                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3345                 x86_pmu.intel_cap.capabilities = capabilities;
3346         }
3347
3348         intel_ds_init();
3349
3350         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3351
3352         /*
3353          * Install the hw-cache-events table:
3354          */
3355         switch (boot_cpu_data.x86_model) {
3356         case 14: /* 65nm Core "Yonah" */
3357                 pr_cont("Core events, ");
3358                 break;
3359
3360         case 15: /* 65nm Core2 "Merom"          */
3361                 x86_add_quirk(intel_clovertown_quirk);
3362         case 22: /* 65nm Core2 "Merom-L"        */
3363         case 23: /* 45nm Core2 "Penryn"         */
3364         case 29: /* 45nm Core2 "Dunnington (MP) */
3365                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3366                        sizeof(hw_cache_event_ids));
3367
3368                 intel_pmu_lbr_init_core();
3369
3370                 x86_pmu.event_constraints = intel_core2_event_constraints;
3371                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3372                 pr_cont("Core2 events, ");
3373                 break;
3374
3375         case 30: /* 45nm Nehalem    */
3376         case 26: /* 45nm Nehalem-EP */
3377         case 46: /* 45nm Nehalem-EX */
3378                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3379                        sizeof(hw_cache_event_ids));
3380                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3381                        sizeof(hw_cache_extra_regs));
3382
3383                 intel_pmu_lbr_init_nhm();
3384
3385                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3386                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3387                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3388                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3389
3390                 x86_pmu.cpu_events = nhm_events_attrs;
3391
3392                 /* UOPS_ISSUED.STALLED_CYCLES */
3393                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3394                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3395                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3396                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3397                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3398
3399                 x86_add_quirk(intel_nehalem_quirk);
3400
3401                 pr_cont("Nehalem events, ");
3402                 break;
3403
3404         case 28: /* 45nm Atom "Pineview"   */
3405         case 38: /* 45nm Atom "Lincroft"   */
3406         case 39: /* 32nm Atom "Penwell"    */
3407         case 53: /* 32nm Atom "Cloverview" */
3408         case 54: /* 32nm Atom "Cedarview"  */
3409                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3410                        sizeof(hw_cache_event_ids));
3411
3412                 intel_pmu_lbr_init_atom();
3413
3414                 x86_pmu.event_constraints = intel_gen_event_constraints;
3415                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3416                 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
3417                 pr_cont("Atom events, ");
3418                 break;
3419
3420         case 55: /* 22nm Atom "Silvermont"                */
3421         case 76: /* 14nm Atom "Airmont"                   */
3422         case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3423                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3424                         sizeof(hw_cache_event_ids));
3425                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3426                        sizeof(hw_cache_extra_regs));
3427
3428                 intel_pmu_lbr_init_atom();
3429
3430                 x86_pmu.event_constraints = intel_slm_event_constraints;
3431                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3432                 x86_pmu.extra_regs = intel_slm_extra_regs;
3433                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3434                 pr_cont("Silvermont events, ");
3435                 break;
3436
3437         case 37: /* 32nm Westmere    */
3438         case 44: /* 32nm Westmere-EP */
3439         case 47: /* 32nm Westmere-EX */
3440                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3441                        sizeof(hw_cache_event_ids));
3442                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3443                        sizeof(hw_cache_extra_regs));
3444
3445                 intel_pmu_lbr_init_nhm();
3446
3447                 x86_pmu.event_constraints = intel_westmere_event_constraints;
3448                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3449                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3450                 x86_pmu.extra_regs = intel_westmere_extra_regs;
3451                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3452
3453                 x86_pmu.cpu_events = nhm_events_attrs;
3454
3455                 /* UOPS_ISSUED.STALLED_CYCLES */
3456                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3457                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3458                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3459                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3460                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3461
3462                 pr_cont("Westmere events, ");
3463                 break;
3464
3465         case 42: /* 32nm SandyBridge         */
3466         case 45: /* 32nm SandyBridge-E/EN/EP */
3467                 x86_add_quirk(intel_sandybridge_quirk);
3468                 x86_add_quirk(intel_ht_bug);
3469                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3470                        sizeof(hw_cache_event_ids));
3471                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3472                        sizeof(hw_cache_extra_regs));
3473
3474                 intel_pmu_lbr_init_snb();
3475
3476                 x86_pmu.event_constraints = intel_snb_event_constraints;
3477                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3478                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3479                 if (boot_cpu_data.x86_model == 45)
3480                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3481                 else
3482                         x86_pmu.extra_regs = intel_snb_extra_regs;
3483
3484
3485                 /* all extra regs are per-cpu when HT is on */
3486                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3487                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3488
3489                 x86_pmu.cpu_events = snb_events_attrs;
3490
3491                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3492                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3493                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3494                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3495                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3496                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3497
3498                 pr_cont("SandyBridge events, ");
3499                 break;
3500
3501         case 58: /* 22nm IvyBridge       */
3502         case 62: /* 22nm IvyBridge-EP/EX */
3503                 x86_add_quirk(intel_ht_bug);
3504                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3505                        sizeof(hw_cache_event_ids));
3506                 /* dTLB-load-misses on IVB is different than SNB */
3507                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3508
3509                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3510                        sizeof(hw_cache_extra_regs));
3511
3512                 intel_pmu_lbr_init_snb();
3513
3514                 x86_pmu.event_constraints = intel_ivb_event_constraints;
3515                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3516                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3517                 x86_pmu.pebs_prec_dist = true;
3518                 if (boot_cpu_data.x86_model == 62)
3519                         x86_pmu.extra_regs = intel_snbep_extra_regs;
3520                 else
3521                         x86_pmu.extra_regs = intel_snb_extra_regs;
3522                 /* all extra regs are per-cpu when HT is on */
3523                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3524                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3525
3526                 x86_pmu.cpu_events = snb_events_attrs;
3527
3528                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3529                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3530                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3531
3532                 pr_cont("IvyBridge events, ");
3533                 break;
3534
3535
3536         case 60: /* 22nm Haswell Core */
3537         case 63: /* 22nm Haswell Server */
3538         case 69: /* 22nm Haswell ULT */
3539         case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3540                 x86_add_quirk(intel_ht_bug);
3541                 x86_pmu.late_ack = true;
3542                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3543                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3544
3545                 intel_pmu_lbr_init_hsw();
3546
3547                 x86_pmu.event_constraints = intel_hsw_event_constraints;
3548                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3549                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3550                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3551                 x86_pmu.pebs_prec_dist = true;
3552                 /* all extra regs are per-cpu when HT is on */
3553                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3554                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3555
3556                 x86_pmu.hw_config = hsw_hw_config;
3557                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3558                 x86_pmu.cpu_events = hsw_events_attrs;
3559                 x86_pmu.lbr_double_abort = true;
3560                 pr_cont("Haswell events, ");
3561                 break;
3562
3563         case 61: /* 14nm Broadwell Core-M */
3564         case 86: /* 14nm Broadwell Xeon D */
3565         case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3566         case 79: /* 14nm Broadwell Server */
3567                 x86_pmu.late_ack = true;
3568                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3569                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3570
3571                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3572                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3573                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
3574                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3575                                                                           HSW_SNOOP_DRAM;
3576                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3577                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3578                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3579                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3580
3581                 intel_pmu_lbr_init_hsw();
3582
3583                 x86_pmu.event_constraints = intel_bdw_event_constraints;
3584                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3585                 x86_pmu.extra_regs = intel_snbep_extra_regs;
3586                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3587                 x86_pmu.pebs_prec_dist = true;
3588                 /* all extra regs are per-cpu when HT is on */
3589                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3590                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3591
3592                 x86_pmu.hw_config = hsw_hw_config;
3593                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3594                 x86_pmu.cpu_events = hsw_events_attrs;
3595                 x86_pmu.limit_period = bdw_limit_period;
3596                 pr_cont("Broadwell events, ");
3597                 break;
3598
3599         case 87: /* Knights Landing Xeon Phi */
3600                 memcpy(hw_cache_event_ids,
3601                        slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3602                 memcpy(hw_cache_extra_regs,
3603                        knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3604                 intel_pmu_lbr_init_knl();
3605
3606                 x86_pmu.event_constraints = intel_slm_event_constraints;
3607                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3608                 x86_pmu.extra_regs = intel_knl_extra_regs;
3609
3610                 /* all extra regs are per-cpu when HT is on */
3611                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3612                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3613
3614                 pr_cont("Knights Landing events, ");
3615                 break;
3616
3617         case 78: /* 14nm Skylake Mobile */
3618         case 94: /* 14nm Skylake Desktop */
3619                 x86_pmu.late_ack = true;
3620                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3621                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3622                 intel_pmu_lbr_init_skl();
3623
3624                 x86_pmu.event_constraints = intel_skl_event_constraints;
3625                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3626                 x86_pmu.extra_regs = intel_skl_extra_regs;
3627                 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3628                 x86_pmu.pebs_prec_dist = true;
3629                 /* all extra regs are per-cpu when HT is on */
3630                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3631                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3632
3633                 x86_pmu.hw_config = hsw_hw_config;
3634                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3635                 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3636                                                   skl_format_attr);
3637                 WARN_ON(!x86_pmu.format_attrs);
3638                 x86_pmu.cpu_events = hsw_events_attrs;
3639                 pr_cont("Skylake events, ");
3640                 break;
3641
3642         default:
3643                 switch (x86_pmu.version) {
3644                 case 1:
3645                         x86_pmu.event_constraints = intel_v1_event_constraints;
3646                         pr_cont("generic architected perfmon v1, ");
3647                         break;
3648                 default:
3649                         /*
3650                          * default constraints for v2 and up
3651                          */
3652                         x86_pmu.event_constraints = intel_gen_event_constraints;
3653                         pr_cont("generic architected perfmon, ");
3654                         break;
3655                 }
3656         }
3657
3658         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3659                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3660                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3661                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3662         }
3663         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3664
3665         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3666                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3667                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3668                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3669         }
3670
3671         x86_pmu.intel_ctrl |=
3672                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3673
3674         if (x86_pmu.event_constraints) {
3675                 /*
3676                  * event on fixed counter2 (REF_CYCLES) only works on this
3677                  * counter, so do not extend mask to generic counters
3678                  */
3679                 for_each_event_constraint(c, x86_pmu.event_constraints) {
3680                         if (c->cmask == FIXED_EVENT_FLAGS
3681                             && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3682                                 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3683                         }
3684                         c->idxmsk64 &=
3685                                 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3686                         c->weight = hweight64(c->idxmsk64);
3687                 }
3688         }
3689
3690         /*
3691          * Access LBR MSR may cause #GP under certain circumstances.
3692          * E.g. KVM doesn't support LBR MSR
3693          * Check all LBT MSR here.
3694          * Disable LBR access if any LBR MSRs can not be accessed.
3695          */
3696         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3697                 x86_pmu.lbr_nr = 0;
3698         for (i = 0; i < x86_pmu.lbr_nr; i++) {
3699                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3700                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3701                         x86_pmu.lbr_nr = 0;
3702         }
3703
3704         /*
3705          * Access extra MSR may cause #GP under certain circumstances.
3706          * E.g. KVM doesn't support offcore event
3707          * Check all extra_regs here.
3708          */
3709         if (x86_pmu.extra_regs) {
3710                 for (er = x86_pmu.extra_regs; er->msr; er++) {
3711                         er->extra_msr_access = check_msr(er->msr, 0x11UL);
3712                         /* Disable LBR select mapping */
3713                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3714                                 x86_pmu.lbr_sel_map = NULL;
3715                 }
3716         }
3717
3718         /* Support full width counters using alternative MSR range */
3719         if (x86_pmu.intel_cap.full_width_write) {
3720                 x86_pmu.max_period = x86_pmu.cntval_mask;
3721                 x86_pmu.perfctr = MSR_IA32_PMC0;
3722                 pr_cont("full-width counters, ");
3723         }
3724
3725         return 0;
3726 }
3727
3728 /*
3729  * HT bug: phase 2 init
3730  * Called once we have valid topology information to check
3731  * whether or not HT is enabled
3732  * If HT is off, then we disable the workaround
3733  */
3734 static __init int fixup_ht_bug(void)
3735 {
3736         int cpu = smp_processor_id();
3737         int w, c;
3738         /*
3739          * problem not present on this CPU model, nothing to do
3740          */
3741         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3742                 return 0;
3743
3744         w = cpumask_weight(topology_sibling_cpumask(cpu));
3745         if (w > 1) {
3746                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3747                 return 0;
3748         }
3749
3750         if (lockup_detector_suspend() != 0) {
3751                 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3752                 return 0;
3753         }
3754
3755         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3756
3757         x86_pmu.start_scheduling = NULL;
3758         x86_pmu.commit_scheduling = NULL;
3759         x86_pmu.stop_scheduling = NULL;
3760
3761         lockup_detector_resume();
3762
3763         get_online_cpus();
3764
3765         for_each_online_cpu(c) {
3766                 free_excl_cntrs(c);
3767         }
3768
3769         put_online_cpus();
3770         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3771         return 0;
3772 }
3773 subsys_initcall(fixup_ht_bug)